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1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */2/*3 * Wave5 series multi-standard codec IP - wave5 backend definitions4 *5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC6 */7 8#ifndef __WAVE5_FUNCTION_H__9#define __WAVE5_FUNCTION_H__10 11#define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h) (ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8))12#define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h) (ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4))13 14/*15 * Bitstream buffer option: Explicit End16 * When set to 1 the VPU assumes that the bitstream has at least one frame and17 * will read until the end of the bitstream buffer.18 * When set to 0 the VPU will not read the last few bytes.19 * This option can be set anytime but cannot be cleared during processing.20 * It can be set to force finish decoding even though there is not enough21 * bitstream data for a full frame.22 */23#define BSOPTION_ENABLE_EXPLICIT_END BIT(0)24#define BSOPTION_HIGHLIGHT_STREAM_END BIT(1)25/*26 * When RD_PTR_VALID_FLAG is 0 Wave515 ignores RD_PTR value and starts to27 * decode from the access unit end position of the last decoded picture in28 * bitstream buffer.29 */30#define BSOPTION_RD_PTR_VALID_FLAG BIT(31)31 32/*33 * Currently the driver only supports hardware with little endian but for source34 * picture format, the bitstream and the report parameter the hardware works35 * with the opposite endianness, thus hard-code big endian for the register36 * writes37 */38#define PIC_SRC_ENDIANNESS_BIG_ENDIAN 0xf39#define BITSTREAM_ENDIANNESS_BIG_ENDIAN 0xf40#define REPORT_PARAM_ENDIANNESS_BIG_ENDIAN 0xf41 42#define WTL_RIGHT_JUSTIFIED 043#define WTL_LEFT_JUSTIFIED 144#define WTL_PIXEL_8BIT 045#define WTL_PIXEL_16BIT 146#define WTL_PIXEL_32BIT 247 48/* Mirror & rotation modes of the PRP (pre-processing) module */49#define NONE_ROTATE 0x050#define ROT_CLOCKWISE_90 0x351#define ROT_CLOCKWISE_180 0x552#define ROT_CLOCKWISE_270 0x753#define MIR_HOR_FLIP 0x1154#define MIR_VER_FLIP 0x955#define MIR_HOR_VER_FLIP (MIR_HOR_FLIP | MIR_VER_FLIP)56 57bool wave5_vpu_is_init(struct vpu_device *vpu_dev);58 59unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev);60 61int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision);62 63int wave5_vpu_init(struct device *dev, u8 *fw, size_t size);64 65int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode);66 67int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param);68 69int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos);70 71int wave5_vpu_hw_flush_instance(struct vpu_instance *inst);72 73int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst,74 struct frame_buffer *fb_arr, enum tiled_map_type map_type,75 unsigned int count);76 77int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size);78 79int wave5_vpu_dec_init_seq(struct vpu_instance *inst);80 81int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info);82 83int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res);84 85int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result);86 87int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res);88 89int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index);90 91int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index);92 93int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags);94 95dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst);96 97int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr);98 99/***< WAVE5 encoder >******/100 101int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,102 struct enc_open_param *open_param);103 104int wave5_vpu_enc_init_seq(struct vpu_instance *inst);105 106int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info);107 108int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,109 struct frame_buffer *fb_arr, enum tiled_map_type map_type,110 unsigned int count);111 112int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res);113 114int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result);115 116int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res);117 118int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param);119 120#endif /* __WAVE5_FUNCTION_H__ */121