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1// SPDX-License-Identifier: GPL-2.02/*3 * Imagination E5010 JPEG Encoder driver.4 *5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/6 *7 * Author: David Huang <d-huang@ti.com>8 * Author: Devarsh Thakkar <devarsht@ti.com>9 */10 11#include <linux/io.h>12#include <linux/iopoll.h>13#include <linux/dev_printk.h>14#include "e5010-jpeg-enc-hw.h"15 16static void write_reg_field(void __iomem *base, unsigned int offset, u32 mask,17 unsigned int shift, u32 value)18{19 u32 reg;20 21 value <<= shift;22 if (mask != 0xffffffff) {23 reg = readl(base + offset);24 value = (value & mask) | (reg & ~mask);25 }26 writel(value, (base + offset));27}28 29static int write_reg_field_not_busy(void __iomem *jasper_base, void __iomem *wr_base,30 unsigned int offset, u32 mask, unsigned int shift,31 u32 value)32{33 int ret;34 u32 val;35 36 ret = readl_poll_timeout_atomic(jasper_base + JASPER_STATUS_OFFSET, val,37 (val & JASPER_STATUS_CR_JASPER_BUSY_MASK) == 0,38 2000, 50000);39 if (ret)40 return ret;41 42 write_reg_field(wr_base, offset, mask, shift, value);43 44 return 0;45}46 47void e5010_reset(struct device *dev, void __iomem *core_base, void __iomem *mmu_base)48{49 int ret = 0;50 u32 val;51 52 write_reg_field(core_base, JASPER_RESET_OFFSET,53 JASPER_RESET_CR_CORE_RESET_MASK,54 JASPER_RESET_CR_CORE_RESET_SHIFT, 1);55 56 write_reg_field(mmu_base, MMU_MMU_CONTROL1_OFFSET,57 MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK,58 MMU_MMU_CONTROL1_MMU_SOFT_RESET_SHIFT, 1);59 60 ret = readl_poll_timeout_atomic(mmu_base + MMU_MMU_CONTROL1_OFFSET, val,61 (val & MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK) == 0,62 2000, 50000);63 if (ret)64 dev_warn(dev, "MMU soft reset timed out, forcing system soft reset\n");65 66 write_reg_field(core_base, JASPER_RESET_OFFSET,67 JASPER_RESET_CR_SYS_RESET_MASK,68 JASPER_RESET_CR_SYS_RESET_SHIFT, 1);69}70 71void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable)72{73 /* Bypass MMU */74 write_reg_field(mmu_base,75 MMU_MMU_ADDRESS_CONTROL_OFFSET,76 MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_MASK,77 MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_SHIFT,78 enable);79}80 81int e5010_hw_enable_output_address_error_irq(void __iomem *core_base, u32 enable)82{83 return write_reg_field_not_busy(core_base, core_base,84 JASPER_INTERRUPT_MASK_OFFSET,85 JASPER_INTERRUPT_MASK_CR_OUTPUT_ADDRESS_ERROR_ENABLE_MASK,86 JASPER_INTERRUPT_MASK_CR_OUTPUT_ADDRESS_ERROR_ENABLE_SHIFT,87 enable);88}89 90bool e5010_hw_pic_done_irq(void __iomem *core_base)91{92 u32 reg;93 94 reg = readl(core_base + JASPER_INTERRUPT_STATUS_OFFSET);95 return reg & JASPER_INTERRUPT_STATUS_CR_PICTURE_DONE_IRQ_MASK;96}97 98bool e5010_hw_output_address_irq(void __iomem *core_base)99{100 u32 reg;101 102 reg = readl(core_base + JASPER_INTERRUPT_STATUS_OFFSET);103 return reg & JASPER_INTERRUPT_STATUS_CR_OUTPUT_ADDRESS_ERROR_IRQ_MASK;104}105 106int e5010_hw_enable_picture_done_irq(void __iomem *core_base, u32 enable)107{108 return write_reg_field_not_busy(core_base, core_base,109 JASPER_INTERRUPT_MASK_OFFSET,110 JASPER_INTERRUPT_MASK_CR_PICTURE_DONE_ENABLE_MASK,111 JASPER_INTERRUPT_MASK_CR_PICTURE_DONE_ENABLE_SHIFT,112 enable);113}114 115int e5010_hw_enable_auto_clock_gating(void __iomem *core_base, u32 enable)116{117 return write_reg_field_not_busy(core_base, core_base,118 JASPER_CLK_CONTROL_OFFSET,119 JASPER_CLK_CONTROL_CR_JASPER_AUTO_CLKG_ENABLE_MASK,120 JASPER_CLK_CONTROL_CR_JASPER_AUTO_CLKG_ENABLE_SHIFT,121 enable);122}123 124int e5010_hw_enable_manual_clock_gating(void __iomem *core_base, u32 enable)125{126 return write_reg_field_not_busy(core_base, core_base,127 JASPER_CLK_CONTROL_OFFSET,128 JASPER_CLK_CONTROL_CR_JASPER_MAN_CLKG_ENABLE_MASK,129 JASPER_CLK_CONTROL_CR_JASPER_MAN_CLKG_ENABLE_SHIFT, 0);130}131 132int e5010_hw_enable_crc_check(void __iomem *core_base, u32 enable)133{134 return write_reg_field_not_busy(core_base, core_base,135 JASPER_CRC_CTRL_OFFSET,136 JASPER_CRC_CTRL_JASPER_CRC_ENABLE_MASK,137 JASPER_CRC_CTRL_JASPER_CRC_ENABLE_SHIFT, enable);138}139 140int e5010_hw_set_input_source_to_memory(void __iomem *core_base, u32 set)141{142 return write_reg_field_not_busy(core_base, core_base,143 JASPER_INPUT_CTRL0_OFFSET,144 JASPER_INPUT_CTRL0_CR_INPUT_SOURCE_MASK,145 JASPER_INPUT_CTRL0_CR_INPUT_SOURCE_SHIFT, set);146}147 148int e5010_hw_set_input_luma_addr(void __iomem *core_base, u32 val)149{150 return write_reg_field_not_busy(core_base, core_base,151 INPUT_LUMA_BASE_OFFSET,152 INPUT_LUMA_BASE_CR_INPUT_LUMA_BASE_MASK, 0, val);153}154 155int e5010_hw_set_input_chroma_addr(void __iomem *core_base, u32 val)156{157 return write_reg_field_not_busy(core_base, core_base,158 INPUT_CHROMA_BASE_OFFSET,159 INPUT_CHROMA_BASE_CR_INPUT_CHROMA_BASE_MASK, 0, val);160}161 162int e5010_hw_set_output_base_addr(void __iomem *core_base, u32 val)163{164 return write_reg_field_not_busy(core_base, core_base,165 JASPER_OUTPUT_BASE_OFFSET,166 JASPER_OUTPUT_BASE_CR_OUTPUT_BASE_MASK,167 JASPER_OUTPUT_BASE_CR_OUTPUT_BASE_SHIFT, val);168}169 170int e5010_hw_set_horizontal_size(void __iomem *core_base, u32 val)171{172 return write_reg_field_not_busy(core_base, core_base,173 JASPER_IMAGE_SIZE_OFFSET,174 JASPER_IMAGE_SIZE_CR_IMAGE_HORIZONTAL_SIZE_MASK,175 JASPER_IMAGE_SIZE_CR_IMAGE_HORIZONTAL_SIZE_SHIFT,176 val);177}178 179int e5010_hw_set_vertical_size(void __iomem *core_base, u32 val)180{181 return write_reg_field_not_busy(core_base, core_base,182 JASPER_IMAGE_SIZE_OFFSET,183 JASPER_IMAGE_SIZE_CR_IMAGE_VERTICAL_SIZE_MASK,184 JASPER_IMAGE_SIZE_CR_IMAGE_VERTICAL_SIZE_SHIFT,185 val);186}187 188int e5010_hw_set_luma_stride(void __iomem *core_base, u32 bytesperline)189{190 u32 val = bytesperline / 64;191 192 return write_reg_field_not_busy(core_base, core_base,193 JASPER_INPUT_CTRL1_OFFSET,194 JASPER_INPUT_CTRL1_CR_INPUT_LUMA_STRIDE_MASK,195 JASPER_INPUT_CTRL1_CR_INPUT_LUMA_STRIDE_SHIFT,196 val);197}198 199int e5010_hw_set_chroma_stride(void __iomem *core_base, u32 bytesperline)200{201 u32 val = bytesperline / 64;202 203 return write_reg_field_not_busy(core_base, core_base,204 JASPER_INPUT_CTRL1_OFFSET,205 JASPER_INPUT_CTRL1_CR_INPUT_CHROMA_STRIDE_MASK,206 JASPER_INPUT_CTRL1_CR_INPUT_CHROMA_STRIDE_SHIFT,207 val);208}209 210int e5010_hw_set_input_subsampling(void __iomem *core_base, u32 val)211{212 return write_reg_field_not_busy(core_base, core_base,213 JASPER_INPUT_CTRL0_OFFSET,214 JASPER_INPUT_CTRL0_CR_INPUT_SUBSAMPLING_MASK,215 JASPER_INPUT_CTRL0_CR_INPUT_SUBSAMPLING_SHIFT,216 val);217}218 219int e5010_hw_set_chroma_order(void __iomem *core_base, u32 val)220{221 return write_reg_field_not_busy(core_base, core_base,222 JASPER_INPUT_CTRL0_OFFSET,223 JASPER_INPUT_CTRL0_CR_INPUT_CHROMA_ORDER_MASK,224 JASPER_INPUT_CTRL0_CR_INPUT_CHROMA_ORDER_SHIFT,225 val);226}227 228void e5010_hw_set_output_max_size(void __iomem *core_base, u32 val)229{230 write_reg_field(core_base, JASPER_OUTPUT_MAX_SIZE_OFFSET,231 JASPER_OUTPUT_MAX_SIZE_CR_OUTPUT_MAX_SIZE_MASK,232 JASPER_OUTPUT_MAX_SIZE_CR_OUTPUT_MAX_SIZE_SHIFT,233 val);234}235 236int e5010_hw_set_qpvalue(void __iomem *core_base, u32 offset, u32 val)237{238 return write_reg_field_not_busy(core_base, core_base, offset, 0xffffffff, 0, val);239}240 241void e5010_hw_clear_output_error(void __iomem *core_base, u32 clear)242{243 /* Make sure interrupts are clear */244 write_reg_field(core_base, JASPER_INTERRUPT_CLEAR_OFFSET,245 JASPER_INTERRUPT_CLEAR_CR_OUTPUT_ERROR_CLEAR_MASK,246 JASPER_INTERRUPT_CLEAR_CR_OUTPUT_ERROR_CLEAR_SHIFT, clear);247}248 249void e5010_hw_clear_picture_done(void __iomem *core_base, u32 clear)250{251 write_reg_field(core_base,252 JASPER_INTERRUPT_CLEAR_OFFSET,253 JASPER_INTERRUPT_CLEAR_CR_PICTURE_DONE_CLEAR_MASK,254 JASPER_INTERRUPT_CLEAR_CR_PICTURE_DONE_CLEAR_SHIFT, clear);255}256 257int e5010_hw_get_output_size(void __iomem *core_base)258{259 return readl(core_base + JASPER_OUTPUT_SIZE_OFFSET);260}261 262void e5010_hw_encode_start(void __iomem *core_base, u32 start)263{264 write_reg_field(core_base, JASPER_CORE_CTRL_OFFSET,265 JASPER_CORE_CTRL_CR_JASPER_ENCODE_START_MASK,266 JASPER_CORE_CTRL_CR_JASPER_ENCODE_START_SHIFT, start);267}268