312 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Imagination E5010 JPEG Encoder driver.4 *5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/6 *7 * Author: David Huang <d-huang@ti.com>8 * Author: Devarsh Thakkar <devarsht@ti.com>9 */10 11#ifndef _E5010_MMU_REGS_H12#define _E5010_MMU_REGS_H13 14#define MMU_MMU_DIR_BASE_ADDR_OFFSET (0x0020)15#define MMU_MMU_DIR_BASE_ADDR_STRIDE (4)16#define MMU_MMU_DIR_BASE_ADDR_NO_ENTRIES (4)17 18#define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK (0xFFFFFFFF)19#define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT (0)20 21#define MMU_MMU_TILE_CFG_OFFSET (0x0040)22#define MMU_MMU_TILE_CFG_STRIDE (4)23#define MMU_MMU_TILE_CFG_NO_ENTRIES (4)24 25#define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK (0x00000010)26#define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_SHIFT (4)27 28#define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK (0x00000008)29#define MMU_MMU_TILE_CFG_TILE_ENABLE_SHIFT (3)30 31#define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK (0x00000007)32#define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT (0)33 34#define MMU_MMU_TILE_MIN_ADDR_OFFSET (0x0050)35#define MMU_MMU_TILE_MIN_ADDR_STRIDE (4)36#define MMU_MMU_TILE_MIN_ADDR_NO_ENTRIES (4)37 38#define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK (0xFFFFFFFF)39#define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_SHIFT (0)40 41#define MMU_MMU_TILE_MAX_ADDR_OFFSET (0x0060)42#define MMU_MMU_TILE_MAX_ADDR_STRIDE (4)43#define MMU_MMU_TILE_MAX_ADDR_NO_ENTRIES (4)44 45#define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_MASK (0xFFFFFFFF)46#define MMU_MMU_TILE_MAX_ADDR_TILE_MAX_ADDR_SHIFT (0)47 48#define MMU_MMU_CONTROL0_OFFSET (0x0000)49 50#define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_MASK (0x00000001)51#define MMU_MMU_CONTROL0_MMU_TILING_SCHEME_SHIFT (0)52 53#define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_MASK (0x00000100)54#define MMU_MMU_CONTROL0_MMU_CACHE_POLICY_SHIFT (8)55 56#define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_MASK (0x00000200)57#define MMU_MMU_CONTROL0_FORCE_CACHE_POLICY_BYPASS_SHIFT (9)58 59#define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_MASK (0x00001000)60#define MMU_MMU_CONTROL0_STALL_ON_PROTOCOL_FAULT_SHIFT (12)61 62#define MMU_MMU_CONTROL1_OFFSET (0x0008)63 64#define MMU_MMU_CONTROL1_MMU_FLUSH_MASK (0x00000008)65#define MMU_MMU_CONTROL1_MMU_FLUSH_SHIFT (3)66#define MMU_MMU_CONTROL1_MMU_FLUSH_NO_REPS (4)67#define MMU_MMU_CONTROL1_MMU_FLUSH_SIZE (1)68 69#define MMU_MMU_CONTROL1_MMU_INVALDC_MASK (0x00000800)70#define MMU_MMU_CONTROL1_MMU_INVALDC_SHIFT (11)71#define MMU_MMU_CONTROL1_MMU_INVALDC_NO_REPS (4)72#define MMU_MMU_CONTROL1_MMU_INVALDC_SIZE (1)73 74#define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_MASK (0x00010000)75#define MMU_MMU_CONTROL1_MMU_FAULT_CLEAR_SHIFT (16)76 77#define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_MASK (0x00100000)78#define MMU_MMU_CONTROL1_PROTOCOL_FAULT_CLEAR_SHIFT (20)79 80#define MMU_MMU_CONTROL1_MMU_PAUSE_SET_MASK (0x01000000)81#define MMU_MMU_CONTROL1_MMU_PAUSE_SET_SHIFT (24)82 83#define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_MASK (0x02000000)84#define MMU_MMU_CONTROL1_MMU_PAUSE_CLEAR_SHIFT (25)85 86#define MMU_MMU_CONTROL1_MMU_SOFT_RESET_MASK (0x10000000)87#define MMU_MMU_CONTROL1_MMU_SOFT_RESET_SHIFT (28)88 89#define MMU_MMU_BANK_INDEX_OFFSET (0x0010)90 91#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_MASK (0xC0000000)92#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SHIFT (30)93#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_NO_REPS (16)94#define MMU_MMU_BANK_INDEX_MMU_BANK_INDEX_SIZE (2)95 96#define MMU_REQUEST_PRIORITY_ENABLE_OFFSET (0x0018)97 98#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_MASK (0x00008000)99#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_SHIFT (15)100#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_NO_REPS (16)101#define MMU_REQUEST_PRIORITY_ENABLE_CMD_PRIORITY_ENABLE_SIZE (1)102 103#define MMU_REQUEST_PRIORITY_ENABLE_CMD_MMU_PRIORITY_ENABLE_MASK (0x00010000)104#define MMU_REQUEST_PRIORITY_ENABLE_CMD_MMU_PRIORITY_ENABLE_SHIFT (16)105 106#define MMU_REQUEST_LIMITED_THROUGHPUT_OFFSET (0x001C)107 108#define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_MASK (0x000003FF)109#define MMU_REQUEST_LIMITED_THROUGHPUT_LIMITED_WORDS_SHIFT (0)110 111#define MMU_REQUEST_LIMITED_THROUGHPUT_REQUEST_GAP_MASK (0x0FFF0000)112#define MMU_REQUEST_LIMITED_THROUGHPUT_REQUEST_GAP_SHIFT (16)113 114#define MMU_MMU_ADDRESS_CONTROL_OFFSET (0x0070)115#define MMU_MMU_ADDRESS_CONTROL_TRUSTED (IMG_TRUE)116 117#define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_MASK (0x00000001)118#define MMU_MMU_ADDRESS_CONTROL_MMU_BYPASS_SHIFT (0)119 120#define MMU_MMU_ADDRESS_CONTROL_MMU_ENABLE_EXT_ADDRESSING_MASK (0x00000010)121#define MMU_MMU_ADDRESS_CONTROL_MMU_ENABLE_EXT_ADDRESSING_SHIFT (4)122 123#define MMU_MMU_ADDRESS_CONTROL_UPPER_ADDRESS_FIXED_MASK (0x00FF0000)124#define MMU_MMU_ADDRESS_CONTROL_UPPER_ADDRESS_FIXED_SHIFT (16)125 126#define MMU_MMU_CONFIG0_OFFSET (0x0080)127 128#define MMU_MMU_CONFIG0_NUM_REQUESTORS_MASK (0x0000000F)129#define MMU_MMU_CONFIG0_NUM_REQUESTORS_SHIFT (0)130 131#define MMU_MMU_CONFIG0_EXTENDED_ADDR_RANGE_MASK (0x000000F0)132#define MMU_MMU_CONFIG0_EXTENDED_ADDR_RANGE_SHIFT (4)133 134#define MMU_MMU_CONFIG0_GROUP_OVERRIDE_SIZE_MASK (0x00000700)135#define MMU_MMU_CONFIG0_GROUP_OVERRIDE_SIZE_SHIFT (8)136 137#define MMU_MMU_CONFIG0_ADDR_COHERENCY_SUPPORTED_MASK (0x00001000)138#define MMU_MMU_CONFIG0_ADDR_COHERENCY_SUPPORTED_SHIFT (12)139 140#define MMU_MMU_CONFIG0_MMU_SUPPORTED_MASK (0x00002000)141#define MMU_MMU_CONFIG0_MMU_SUPPORTED_SHIFT (13)142 143#define MMU_MMU_CONFIG0_TILE_ADDR_GRANULARITY_MASK (0x001F0000)144#define MMU_MMU_CONFIG0_TILE_ADDR_GRANULARITY_SHIFT (16)145 146#define MMU_MMU_CONFIG0_NO_READ_REORDER_MASK (0x00200000)147#define MMU_MMU_CONFIG0_NO_READ_REORDER_SHIFT (21)148 149#define MMU_MMU_CONFIG0_TAGS_SUPPORTED_MASK (0xFFC00000)150#define MMU_MMU_CONFIG0_TAGS_SUPPORTED_SHIFT (22)151 152#define MMU_MMU_CONFIG1_OFFSET (0x0084)153 154#define MMU_MMU_CONFIG1_PAGE_SIZE_MASK (0x0000000F)155#define MMU_MMU_CONFIG1_PAGE_SIZE_SHIFT (0)156 157#define MMU_MMU_CONFIG1_PAGE_CACHE_ENTRIES_MASK (0x0000FF00)158#define MMU_MMU_CONFIG1_PAGE_CACHE_ENTRIES_SHIFT (8)159 160#define MMU_MMU_CONFIG1_DIR_CACHE_ENTRIES_MASK (0x001F0000)161#define MMU_MMU_CONFIG1_DIR_CACHE_ENTRIES_SHIFT (16)162 163#define MMU_MMU_CONFIG1_BANDWIDTH_COUNT_SUPPORTED_MASK (0x01000000)164#define MMU_MMU_CONFIG1_BANDWIDTH_COUNT_SUPPORTED_SHIFT (24)165 166#define MMU_MMU_CONFIG1_STALL_COUNT_SUPPORTED_MASK (0x02000000)167#define MMU_MMU_CONFIG1_STALL_COUNT_SUPPORTED_SHIFT (25)168 169#define MMU_MMU_CONFIG1_LATENCY_COUNT_SUPPORTED_MASK (0x04000000)170#define MMU_MMU_CONFIG1_LATENCY_COUNT_SUPPORTED_SHIFT (26)171 172#define MMU_MMU_STATUS0_OFFSET (0x0088)173 174#define MMU_MMU_STATUS0_MMU_PF_N_RW_MASK (0x00000001)175#define MMU_MMU_STATUS0_MMU_PF_N_RW_SHIFT (0)176 177#define MMU_MMU_STATUS0_MMU_FAULT_ADDR_MASK (0xFFFFF000)178#define MMU_MMU_STATUS0_MMU_FAULT_ADDR_SHIFT (12)179 180#define MMU_MMU_STATUS1_OFFSET (0x008C)181 182#define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_MASK (0x0000FFFF)183#define MMU_MMU_STATUS1_MMU_FAULT_REQ_STAT_SHIFT (0)184 185#define MMU_MMU_STATUS1_MMU_FAULT_REQ_ID_MASK (0x000F0000)186#define MMU_MMU_STATUS1_MMU_FAULT_REQ_ID_SHIFT (16)187 188#define MMU_MMU_STATUS1_MMU_FAULT_INDEX_MASK (0x03000000)189#define MMU_MMU_STATUS1_MMU_FAULT_INDEX_SHIFT (24)190 191#define MMU_MMU_STATUS1_MMU_FAULT_RNW_MASK (0x10000000)192#define MMU_MMU_STATUS1_MMU_FAULT_RNW_SHIFT (28)193 194#define MMU_MMU_MEM_REQ_OFFSET (0x0090)195 196#define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_MASK (0x000003FF)197#define MMU_MMU_MEM_REQ_TAG_OUTSTANDING_SHIFT (0)198 199#define MMU_MMU_MEM_REQ_EXT_WRRESP_FAULT_MASK (0x00001000)200#define MMU_MMU_MEM_REQ_EXT_WRRESP_FAULT_SHIFT (12)201 202#define MMU_MMU_MEM_REQ_EXT_RDRESP_FAULT_MASK (0x00002000)203#define MMU_MMU_MEM_REQ_EXT_RDRESP_FAULT_SHIFT (13)204 205#define MMU_MMU_MEM_REQ_EXT_READ_BURST_FAULT_MASK (0x00004000)206#define MMU_MMU_MEM_REQ_EXT_READ_BURST_FAULT_SHIFT (14)207 208#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_MASK (0x80000000)209#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_SHIFT (31)210#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_NO_REPS (16)211#define MMU_MMU_MEM_REQ_INT_PROTOCOL_FAULT_SIZE (1)212 213#define MMU_MMU_FAULT_SELECT_OFFSET (0x00A0)214 215#define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_MASK (0x0000000F)216#define MMU_MMU_FAULT_SELECT_MMU_FAULT_SELECT_SHIFT (0)217 218#define MMU_PROTOCOL_FAULT_OFFSET (0x00A8)219 220#define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_MASK (0x00000001)221#define MMU_PROTOCOL_FAULT_FAULT_PAGE_BREAK_SHIFT (0)222 223#define MMU_PROTOCOL_FAULT_FAULT_WRITE_MASK (0x00000010)224#define MMU_PROTOCOL_FAULT_FAULT_WRITE_SHIFT (4)225 226#define MMU_PROTOCOL_FAULT_FAULT_READ_MASK (0x00000020)227#define MMU_PROTOCOL_FAULT_FAULT_READ_SHIFT (5)228 229#define MMU_TOTAL_READ_REQ_OFFSET (0x0100)230 231#define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_MASK (0xFFFFFFFF)232#define MMU_TOTAL_READ_REQ_TOTAL_READ_REQ_SHIFT (0)233 234#define MMU_TOTAL_WRITE_REQ_OFFSET (0x0104)235 236#define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_MASK (0xFFFFFFFF)237#define MMU_TOTAL_WRITE_REQ_TOTAL_WRITE_REQ_SHIFT (0)238 239#define MMU_READS_LESS_64_REQ_OFFSET (0x0108)240 241#define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_MASK (0xFFFFFFFF)242#define MMU_READS_LESS_64_REQ_READS_LESS_64_REQ_SHIFT (0)243 244#define MMU_WRITES_LESS_64_REQ_OFFSET (0x010C)245 246#define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_MASK (0xFFFFFFFF)247#define MMU_WRITES_LESS_64_REQ_WRITES_LESS_64_REQ_SHIFT (0)248 249#define MMU_EXT_CMD_STALL_OFFSET (0x0120)250 251#define MMU_EXT_CMD_STALL_EXT_CMD_STALL_MASK (0xFFFFFFFF)252#define MMU_EXT_CMD_STALL_EXT_CMD_STALL_SHIFT (0)253 254#define MMU_WRITE_REQ_STALL_OFFSET (0x0124)255 256#define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_MASK (0xFFFFFFFF)257#define MMU_WRITE_REQ_STALL_WRITE_REQ_STALL_SHIFT (0)258 259#define MMU_MMU_MISS_STALL_OFFSET (0x0128)260 261#define MMU_MMU_MISS_STALL_MMU_MISS_STALL_MASK (0xFFFFFFFF)262#define MMU_MMU_MISS_STALL_MMU_MISS_STALL_SHIFT (0)263 264#define MMU_ADDRESS_STALL_OFFSET (0x012C)265 266#define MMU_ADDRESS_STALL_ADDRESS_STALL_MASK (0xFFFFFFFF)267#define MMU_ADDRESS_STALL_ADDRESS_STALL_SHIFT (0)268 269#define MMU_TAG_STALL_OFFSET (0x0130)270 271#define MMU_TAG_STALL_TAG_STALL_MASK (0xFFFFFFFF)272#define MMU_TAG_STALL_TAG_STALL_SHIFT (0)273 274#define MMU_PEAK_READ_OUTSTANDING_OFFSET (0x0140)275 276#define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_MASK (0x000003FF)277#define MMU_PEAK_READ_OUTSTANDING_PEAK_TAG_OUTSTANDING_SHIFT (0)278 279#define MMU_PEAK_READ_OUTSTANDING_PEAK_READ_LATENCY_MASK (0xFFFF0000)280#define MMU_PEAK_READ_OUTSTANDING_PEAK_READ_LATENCY_SHIFT (16)281 282#define MMU_AVERAGE_READ_LATENCY_OFFSET (0x0144)283 284#define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_MASK (0xFFFFFFFF)285#define MMU_AVERAGE_READ_LATENCY_AVERAGE_READ_LATENCY_SHIFT (0)286 287#define MMU_STATISTICS_CONTROL_OFFSET (0x0160)288 289#define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_MASK (0x00000001)290#define MMU_STATISTICS_CONTROL_BANDWIDTH_STATS_INIT_SHIFT (0)291 292#define MMU_STATISTICS_CONTROL_STALL_STATS_INIT_MASK (0x00000002)293#define MMU_STATISTICS_CONTROL_STALL_STATS_INIT_SHIFT (1)294 295#define MMU_STATISTICS_CONTROL_LATENCY_STATS_INIT_MASK (0x00000004)296#define MMU_STATISTICS_CONTROL_LATENCY_STATS_INIT_SHIFT (2)297 298#define MMU_MMU_VERSION_OFFSET (0x01D0)299 300#define MMU_MMU_VERSION_MMU_MAJOR_REV_MASK (0x00FF0000)301#define MMU_MMU_VERSION_MMU_MAJOR_REV_SHIFT (16)302 303#define MMU_MMU_VERSION_MMU_MINOR_REV_MASK (0x0000FF00)304#define MMU_MMU_VERSION_MMU_MINOR_REV_SHIFT (8)305 306#define MMU_MMU_VERSION_MMU_MAINT_REV_MASK (0x000000FF)307#define MMU_MMU_VERSION_MMU_MAINT_REV_SHIFT (0)308 309#define MMU_BYTE_SIZE (0x01D4)310 311#endif312