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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2023 MediaTek Inc.4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>5 */6 7#include "mtk-img-ipi.h"8#include "mtk-mdp3-cfg.h"9#include "mtk-mdp3-core.h"10#include "mtk-mdp3-comp.h"11#include "mtk-mdp3-regs.h"12 13enum mt8183_mdp_comp_id {14 /* ISP */15 MT8183_MDP_COMP_WPEI = 0,16 MT8183_MDP_COMP_WPEO, /* 1 */17 MT8183_MDP_COMP_WPEI2, /* 2 */18 MT8183_MDP_COMP_WPEO2, /* 3 */19 MT8183_MDP_COMP_ISP_IMGI, /* 4 */20 MT8183_MDP_COMP_ISP_IMGO, /* 5 */21 MT8183_MDP_COMP_ISP_IMG2O, /* 6 */22 23 /* IPU */24 MT8183_MDP_COMP_IPUI, /* 7 */25 MT8183_MDP_COMP_IPUO, /* 8 */26 27 /* MDP */28 MT8183_MDP_COMP_CAMIN, /* 9 */29 MT8183_MDP_COMP_CAMIN2, /* 10 */30 MT8183_MDP_COMP_RDMA0, /* 11 */31 MT8183_MDP_COMP_AAL0, /* 12 */32 MT8183_MDP_COMP_CCORR0, /* 13 */33 MT8183_MDP_COMP_RSZ0, /* 14 */34 MT8183_MDP_COMP_RSZ1, /* 15 */35 MT8183_MDP_COMP_TDSHP0, /* 16 */36 MT8183_MDP_COMP_COLOR0, /* 17 */37 MT8183_MDP_COMP_PATH0_SOUT, /* 18 */38 MT8183_MDP_COMP_PATH1_SOUT, /* 19 */39 MT8183_MDP_COMP_WROT0, /* 20 */40 MT8183_MDP_COMP_WDMA, /* 21 */41 42 /* Dummy Engine */43 MT8183_MDP_COMP_RDMA1, /* 22 */44 MT8183_MDP_COMP_RSZ2, /* 23 */45 MT8183_MDP_COMP_TDSHP1, /* 24 */46 MT8183_MDP_COMP_WROT1, /* 25 */47};48 49enum mt8188_mdp_comp_id {50 /* MT8188 Comp id */51 /* ISP */52 MT8188_MDP_COMP_WPEI = 0,53 MT8188_MDP_COMP_WPEO, /* 1 */54 55 /* MDP */56 MT8188_MDP_COMP_CAMIN, /* 2 */57 MT8188_MDP_COMP_RDMA0, /* 3 */58 MT8188_MDP_COMP_RDMA2, /* 4 */59 MT8188_MDP_COMP_RDMA3, /* 5 */60 MT8188_MDP_COMP_FG0, /* 6 */61 MT8188_MDP_COMP_FG2, /* 7 */62 MT8188_MDP_COMP_FG3, /* 8 */63 MT8188_MDP_COMP_TO_SVPP2MOUT, /* 9 */64 MT8188_MDP_COMP_TO_SVPP3MOUT, /* 10 */65 MT8188_MDP_COMP_TO_WARP0MOUT, /* 11 */66 MT8188_MDP_COMP_VPP0_SOUT, /* 12 */67 MT8188_MDP_COMP_VPP1_SOUT, /* 13 */68 MT8188_MDP_COMP_PQ0_SOUT, /* 14 */69 MT8188_MDP_COMP_HDR0, /* 15 */70 MT8188_MDP_COMP_HDR2, /* 16 */71 MT8188_MDP_COMP_HDR3, /* 17 */72 MT8188_MDP_COMP_AAL0, /* 18 */73 MT8188_MDP_COMP_AAL2, /* 19 */74 MT8188_MDP_COMP_AAL3, /* 20 */75 MT8188_MDP_COMP_RSZ0, /* 21 */76 MT8188_MDP_COMP_RSZ2, /* 22 */77 MT8188_MDP_COMP_RSZ3, /* 23 */78 MT8188_MDP_COMP_TDSHP0, /* 24 */79 MT8188_MDP_COMP_TDSHP2, /* 25 */80 MT8188_MDP_COMP_TDSHP3, /* 26 */81 MT8188_MDP_COMP_COLOR0, /* 27 */82 MT8188_MDP_COMP_COLOR2, /* 28 */83 MT8188_MDP_COMP_COLOR3, /* 29 */84 MT8188_MDP_COMP_OVL0, /* 30 */85 MT8188_MDP_COMP_PAD0, /* 31 */86 MT8188_MDP_COMP_PAD2, /* 32 */87 MT8188_MDP_COMP_PAD3, /* 33 */88 MT8188_MDP_COMP_TCC0, /* 34 */89 MT8188_MDP_COMP_WROT0, /* 35 */90 MT8188_MDP_COMP_WROT2, /* 36 */91 MT8188_MDP_COMP_WROT3, /* 37 */92 MT8188_MDP_COMP_MERGE2, /* 38 */93 MT8188_MDP_COMP_MERGE3, /* 39 */94};95 96enum mt8195_mdp_comp_id {97 /* MT8195 Comp id */98 /* ISP */99 MT8195_MDP_COMP_WPEI = 0,100 MT8195_MDP_COMP_WPEO, /* 1 */101 MT8195_MDP_COMP_WPEI2, /* 2 */102 MT8195_MDP_COMP_WPEO2, /* 3 */103 104 /* MDP */105 MT8195_MDP_COMP_CAMIN, /* 4 */106 MT8195_MDP_COMP_CAMIN2, /* 5 */107 MT8195_MDP_COMP_SPLIT, /* 6 */108 MT8195_MDP_COMP_SPLIT2, /* 7 */109 MT8195_MDP_COMP_RDMA0, /* 8 */110 MT8195_MDP_COMP_RDMA1, /* 9 */111 MT8195_MDP_COMP_RDMA2, /* 10 */112 MT8195_MDP_COMP_RDMA3, /* 11 */113 MT8195_MDP_COMP_STITCH, /* 12 */114 MT8195_MDP_COMP_FG0, /* 13 */115 MT8195_MDP_COMP_FG1, /* 14 */116 MT8195_MDP_COMP_FG2, /* 15 */117 MT8195_MDP_COMP_FG3, /* 16 */118 MT8195_MDP_COMP_TO_SVPP2MOUT, /* 17 */119 MT8195_MDP_COMP_TO_SVPP3MOUT, /* 18 */120 MT8195_MDP_COMP_TO_WARP0MOUT, /* 19 */121 MT8195_MDP_COMP_TO_WARP1MOUT, /* 20 */122 MT8195_MDP_COMP_VPP0_SOUT, /* 21 */123 MT8195_MDP_COMP_VPP1_SOUT, /* 22 */124 MT8195_MDP_COMP_PQ0_SOUT, /* 23 */125 MT8195_MDP_COMP_PQ1_SOUT, /* 24 */126 MT8195_MDP_COMP_HDR0, /* 25 */127 MT8195_MDP_COMP_HDR1, /* 26 */128 MT8195_MDP_COMP_HDR2, /* 27 */129 MT8195_MDP_COMP_HDR3, /* 28 */130 MT8195_MDP_COMP_AAL0, /* 29 */131 MT8195_MDP_COMP_AAL1, /* 30 */132 MT8195_MDP_COMP_AAL2, /* 31 */133 MT8195_MDP_COMP_AAL3, /* 32 */134 MT8195_MDP_COMP_RSZ0, /* 33 */135 MT8195_MDP_COMP_RSZ1, /* 34 */136 MT8195_MDP_COMP_RSZ2, /* 35 */137 MT8195_MDP_COMP_RSZ3, /* 36 */138 MT8195_MDP_COMP_TDSHP0, /* 37 */139 MT8195_MDP_COMP_TDSHP1, /* 38 */140 MT8195_MDP_COMP_TDSHP2, /* 39 */141 MT8195_MDP_COMP_TDSHP3, /* 40 */142 MT8195_MDP_COMP_COLOR0, /* 41 */143 MT8195_MDP_COMP_COLOR1, /* 42 */144 MT8195_MDP_COMP_COLOR2, /* 43 */145 MT8195_MDP_COMP_COLOR3, /* 44 */146 MT8195_MDP_COMP_OVL0, /* 45 */147 MT8195_MDP_COMP_OVL1, /* 46 */148 MT8195_MDP_COMP_PAD0, /* 47 */149 MT8195_MDP_COMP_PAD1, /* 48 */150 MT8195_MDP_COMP_PAD2, /* 49 */151 MT8195_MDP_COMP_PAD3, /* 50 */152 MT8195_MDP_COMP_TCC0, /* 51 */153 MT8195_MDP_COMP_TCC1, /* 52 */154 MT8195_MDP_COMP_WROT0, /* 53 */155 MT8195_MDP_COMP_WROT1, /* 54 */156 MT8195_MDP_COMP_WROT2, /* 55 */157 MT8195_MDP_COMP_WROT3, /* 56 */158 MT8195_MDP_COMP_MERGE2, /* 57 */159 MT8195_MDP_COMP_MERGE3, /* 58 */160 161 MT8195_MDP_COMP_VDO0DL0, /* 59 */162 MT8195_MDP_COMP_VDO1DL0, /* 60 */163 MT8195_MDP_COMP_VDO0DL1, /* 61 */164 MT8195_MDP_COMP_VDO1DL1, /* 62 */165};166 167static const struct of_device_id mt8183_mdp_probe_infra[MDP_INFRA_MAX] = {168 [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8183-mmsys" },169 [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8183-disp-mutex" },170 [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8183-scp" }171};172 173static const struct of_device_id mt8188_mdp_probe_infra[MDP_INFRA_MAX] = {174 [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8188-vppsys0" },175 [MDP_INFRA_MMSYS2] = { .compatible = "mediatek,mt8188-vppsys1" },176 [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8188-vpp-mutex" },177 [MDP_INFRA_MUTEX2] = { .compatible = "mediatek,mt8188-vpp-mutex" },178};179 180static const struct of_device_id mt8195_mdp_probe_infra[MDP_INFRA_MAX] = {181 [MDP_INFRA_MMSYS] = { .compatible = "mediatek,mt8195-vppsys0" },182 [MDP_INFRA_MMSYS2] = { .compatible = "mediatek,mt8195-vppsys1" },183 [MDP_INFRA_MUTEX] = { .compatible = "mediatek,mt8195-vpp-mutex" },184 [MDP_INFRA_MUTEX2] = { .compatible = "mediatek,mt8195-vpp-mutex" },185 [MDP_INFRA_SCP] = { .compatible = "mediatek,mt8195-scp" }186};187 188static const struct mdp_platform_config mt8183_plat_cfg = {189 .rdma_support_10bit = true,190 .rdma_rsz1_sram_sharing = true,191 .rdma_upsample_repeat_only = true,192 .rdma_event_num = 1,193 .rsz_disable_dcm_small_sample = false,194 .wrot_filter_constraint = false,195 .wrot_event_num = 1,196};197 198static const struct mdp_platform_config mt8195_plat_cfg = {199 .rdma_support_10bit = true,200 .rdma_rsz1_sram_sharing = false,201 .rdma_upsample_repeat_only = false,202 .rdma_esl_setting = true,203 .rdma_event_num = 4,204 .rsz_disable_dcm_small_sample = false,205 .rsz_etc_control = true,206 .wrot_filter_constraint = false,207 .wrot_event_num = 4,208 .tdshp_hist_num = 17,209 .tdshp_constrain = true,210 .tdshp_contour = true,211};212 213static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = {214 [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0,215 [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0,216 [MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1,217 [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0,218 [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0,219 [MDP_COMP_WDMA] = MUTEX_MOD_IDX_MDP_WDMA,220 [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0,221 [MDP_COMP_CCORR0] = MUTEX_MOD_IDX_MDP_CCORR0,222};223 224static const u32 mt8188_mutex_idx[MDP_MAX_COMP_COUNT] = {225 [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0,226 [MDP_COMP_RDMA2] = MUTEX_MOD_IDX_MDP_RDMA2,227 [MDP_COMP_RDMA3] = MUTEX_MOD_IDX_MDP_RDMA3,228 [MDP_COMP_FG0] = MUTEX_MOD_IDX_MDP_FG0,229 [MDP_COMP_FG2] = MUTEX_MOD_IDX_MDP_FG2,230 [MDP_COMP_FG3] = MUTEX_MOD_IDX_MDP_FG3,231 [MDP_COMP_HDR0] = MUTEX_MOD_IDX_MDP_HDR0,232 [MDP_COMP_HDR2] = MUTEX_MOD_IDX_MDP_HDR2,233 [MDP_COMP_HDR3] = MUTEX_MOD_IDX_MDP_HDR3,234 [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0,235 [MDP_COMP_AAL2] = MUTEX_MOD_IDX_MDP_AAL2,236 [MDP_COMP_AAL3] = MUTEX_MOD_IDX_MDP_AAL3,237 [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0,238 [MDP_COMP_RSZ2] = MUTEX_MOD_IDX_MDP_RSZ2,239 [MDP_COMP_RSZ3] = MUTEX_MOD_IDX_MDP_RSZ3,240 [MDP_COMP_MERGE2] = MUTEX_MOD_IDX_MDP_MERGE2,241 [MDP_COMP_MERGE3] = MUTEX_MOD_IDX_MDP_MERGE3,242 [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0,243 [MDP_COMP_TDSHP2] = MUTEX_MOD_IDX_MDP_TDSHP2,244 [MDP_COMP_TDSHP3] = MUTEX_MOD_IDX_MDP_TDSHP3,245 [MDP_COMP_COLOR0] = MUTEX_MOD_IDX_MDP_COLOR0,246 [MDP_COMP_COLOR2] = MUTEX_MOD_IDX_MDP_COLOR2,247 [MDP_COMP_COLOR3] = MUTEX_MOD_IDX_MDP_COLOR3,248 [MDP_COMP_OVL0] = MUTEX_MOD_IDX_MDP_OVL0,249 [MDP_COMP_PAD0] = MUTEX_MOD_IDX_MDP_PAD0,250 [MDP_COMP_PAD2] = MUTEX_MOD_IDX_MDP_PAD2,251 [MDP_COMP_PAD3] = MUTEX_MOD_IDX_MDP_PAD3,252 [MDP_COMP_TCC0] = MUTEX_MOD_IDX_MDP_TCC0,253 [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0,254 [MDP_COMP_WROT2] = MUTEX_MOD_IDX_MDP_WROT2,255 [MDP_COMP_WROT3] = MUTEX_MOD_IDX_MDP_WROT3,256};257 258static const u32 mt8195_mutex_idx[MDP_MAX_COMP_COUNT] = {259 [MDP_COMP_RDMA0] = MUTEX_MOD_IDX_MDP_RDMA0,260 [MDP_COMP_RDMA1] = MUTEX_MOD_IDX_MDP_RDMA1,261 [MDP_COMP_RDMA2] = MUTEX_MOD_IDX_MDP_RDMA2,262 [MDP_COMP_RDMA3] = MUTEX_MOD_IDX_MDP_RDMA3,263 [MDP_COMP_STITCH] = MUTEX_MOD_IDX_MDP_STITCH0,264 [MDP_COMP_FG0] = MUTEX_MOD_IDX_MDP_FG0,265 [MDP_COMP_FG1] = MUTEX_MOD_IDX_MDP_FG1,266 [MDP_COMP_FG2] = MUTEX_MOD_IDX_MDP_FG2,267 [MDP_COMP_FG3] = MUTEX_MOD_IDX_MDP_FG3,268 [MDP_COMP_HDR0] = MUTEX_MOD_IDX_MDP_HDR0,269 [MDP_COMP_HDR1] = MUTEX_MOD_IDX_MDP_HDR1,270 [MDP_COMP_HDR2] = MUTEX_MOD_IDX_MDP_HDR2,271 [MDP_COMP_HDR3] = MUTEX_MOD_IDX_MDP_HDR3,272 [MDP_COMP_AAL0] = MUTEX_MOD_IDX_MDP_AAL0,273 [MDP_COMP_AAL1] = MUTEX_MOD_IDX_MDP_AAL1,274 [MDP_COMP_AAL2] = MUTEX_MOD_IDX_MDP_AAL2,275 [MDP_COMP_AAL3] = MUTEX_MOD_IDX_MDP_AAL3,276 [MDP_COMP_RSZ0] = MUTEX_MOD_IDX_MDP_RSZ0,277 [MDP_COMP_RSZ1] = MUTEX_MOD_IDX_MDP_RSZ1,278 [MDP_COMP_RSZ2] = MUTEX_MOD_IDX_MDP_RSZ2,279 [MDP_COMP_RSZ3] = MUTEX_MOD_IDX_MDP_RSZ3,280 [MDP_COMP_MERGE2] = MUTEX_MOD_IDX_MDP_MERGE2,281 [MDP_COMP_MERGE3] = MUTEX_MOD_IDX_MDP_MERGE3,282 [MDP_COMP_TDSHP0] = MUTEX_MOD_IDX_MDP_TDSHP0,283 [MDP_COMP_TDSHP1] = MUTEX_MOD_IDX_MDP_TDSHP1,284 [MDP_COMP_TDSHP2] = MUTEX_MOD_IDX_MDP_TDSHP2,285 [MDP_COMP_TDSHP3] = MUTEX_MOD_IDX_MDP_TDSHP3,286 [MDP_COMP_COLOR0] = MUTEX_MOD_IDX_MDP_COLOR0,287 [MDP_COMP_COLOR1] = MUTEX_MOD_IDX_MDP_COLOR1,288 [MDP_COMP_COLOR2] = MUTEX_MOD_IDX_MDP_COLOR2,289 [MDP_COMP_COLOR3] = MUTEX_MOD_IDX_MDP_COLOR3,290 [MDP_COMP_OVL0] = MUTEX_MOD_IDX_MDP_OVL0,291 [MDP_COMP_OVL1] = MUTEX_MOD_IDX_MDP_OVL1,292 [MDP_COMP_PAD0] = MUTEX_MOD_IDX_MDP_PAD0,293 [MDP_COMP_PAD1] = MUTEX_MOD_IDX_MDP_PAD1,294 [MDP_COMP_PAD2] = MUTEX_MOD_IDX_MDP_PAD2,295 [MDP_COMP_PAD3] = MUTEX_MOD_IDX_MDP_PAD3,296 [MDP_COMP_TCC0] = MUTEX_MOD_IDX_MDP_TCC0,297 [MDP_COMP_TCC1] = MUTEX_MOD_IDX_MDP_TCC1,298 [MDP_COMP_WROT0] = MUTEX_MOD_IDX_MDP_WROT0,299 [MDP_COMP_WROT1] = MUTEX_MOD_IDX_MDP_WROT1,300 [MDP_COMP_WROT2] = MUTEX_MOD_IDX_MDP_WROT2,301 [MDP_COMP_WROT3] = MUTEX_MOD_IDX_MDP_WROT3,302};303 304static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = {305 [MDP_COMP_WPEI] = {306 {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, MDP_MM_SUBSYS_0},307 {0, 0, 0}308 },309 [MDP_COMP_WPEO] = {310 {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO, MDP_MM_SUBSYS_0},311 {0, 0, 0}312 },313 [MDP_COMP_WPEI2] = {314 {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2, MDP_MM_SUBSYS_0},315 {0, 0, 0}316 },317 [MDP_COMP_WPEO2] = {318 {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2, MDP_MM_SUBSYS_0},319 {0, 0, 0}320 },321 [MDP_COMP_ISP_IMGI] = {322 {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI, MDP_MM_SUBSYS_0},323 {0, 0, 4}324 },325 [MDP_COMP_ISP_IMGO] = {326 {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO, MDP_MM_SUBSYS_0},327 {0, 0, 4}328 },329 [MDP_COMP_ISP_IMG2O] = {330 {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O, MDP_MM_SUBSYS_0},331 {0, 0, 0}332 },333 [MDP_COMP_CAMIN] = {334 {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0},335 {2, 2, 1}336 },337 [MDP_COMP_CAMIN2] = {338 {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2, MDP_MM_SUBSYS_0},339 {2, 4, 1}340 },341 [MDP_COMP_RDMA0] = {342 {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0},343 {2, 0, 0}344 },345 [MDP_COMP_CCORR0] = {346 {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0, MDP_MM_SUBSYS_0},347 {1, 0, 0}348 },349 [MDP_COMP_RSZ0] = {350 {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0},351 {1, 0, 0}352 },353 [MDP_COMP_RSZ1] = {354 {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1, MDP_MM_SUBSYS_0},355 {1, 0, 0}356 },357 [MDP_COMP_TDSHP0] = {358 {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0},359 {0, 0, 0}360 },361 [MDP_COMP_PATH0_SOUT] = {362 {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT, MDP_MM_SUBSYS_0},363 {0, 0, 0}364 },365 [MDP_COMP_PATH1_SOUT] = {366 {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT, MDP_MM_SUBSYS_0},367 {0, 0, 0}368 },369 [MDP_COMP_WROT0] = {370 {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0, MDP_MM_SUBSYS_0},371 {1, 0, 0}372 },373 [MDP_COMP_WDMA] = {374 {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA, MDP_MM_SUBSYS_0},375 {1, 0, 0}376 },377};378 379static const struct mdp_comp_data mt8188_mdp_comp_data[MDP_MAX_COMP_COUNT] = {380 [MDP_COMP_WPEI] = {381 {MDP_COMP_TYPE_WPEI, 0, MT8188_MDP_COMP_WPEI, MDP_MM_SUBSYS_0},382 {0, 0, 0}383 },384 [MDP_COMP_WPEO] = {385 {MDP_COMP_TYPE_EXTO, 0, MT8188_MDP_COMP_WPEO, MDP_MM_SUBSYS_0},386 {0, 0, 0}387 },388 [MDP_COMP_CAMIN] = {389 {MDP_COMP_TYPE_DL_PATH, 0, MT8188_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0},390 {3, 3, 0}391 },392 [MDP_COMP_RDMA0] = {393 {MDP_COMP_TYPE_RDMA, 0, MT8188_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0},394 {3, 0, 0}395 },396 [MDP_COMP_RDMA2] = {397 {MDP_COMP_TYPE_RDMA, 1, MT8188_MDP_COMP_RDMA2, MDP_MM_SUBSYS_1},398 {3, 0, 0}399 },400 [MDP_COMP_RDMA3] = {401 {MDP_COMP_TYPE_RDMA, 2, MT8188_MDP_COMP_RDMA3, MDP_MM_SUBSYS_1},402 {3, 0, 0}403 },404 [MDP_COMP_FG0] = {405 {MDP_COMP_TYPE_FG, 0, MT8188_MDP_COMP_FG0, MDP_MM_SUBSYS_0},406 {1, 0, 0}407 },408 [MDP_COMP_FG2] = {409 {MDP_COMP_TYPE_FG, 1, MT8188_MDP_COMP_FG2, MDP_MM_SUBSYS_1},410 {1, 0, 0}411 },412 [MDP_COMP_FG3] = {413 {MDP_COMP_TYPE_FG, 2, MT8188_MDP_COMP_FG3, MDP_MM_SUBSYS_1},414 {1, 0, 0}415 },416 [MDP_COMP_HDR0] = {417 {MDP_COMP_TYPE_HDR, 0, MT8188_MDP_COMP_HDR0, MDP_MM_SUBSYS_0},418 {1, 0, 0}419 },420 [MDP_COMP_HDR2] = {421 {MDP_COMP_TYPE_HDR, 1, MT8188_MDP_COMP_HDR2, MDP_MM_SUBSYS_1},422 {1, 0, 0}423 },424 [MDP_COMP_HDR3] = {425 {MDP_COMP_TYPE_HDR, 2, MT8188_MDP_COMP_HDR3, MDP_MM_SUBSYS_1},426 {1, 0, 0}427 },428 [MDP_COMP_AAL0] = {429 {MDP_COMP_TYPE_AAL, 0, MT8188_MDP_COMP_AAL0, MDP_MM_SUBSYS_0},430 {1, 0, 0}431 },432 [MDP_COMP_AAL2] = {433 {MDP_COMP_TYPE_AAL, 1, MT8188_MDP_COMP_AAL2, MDP_MM_SUBSYS_1},434 {1, 0, 0}435 },436 [MDP_COMP_AAL3] = {437 {MDP_COMP_TYPE_AAL, 2, MT8188_MDP_COMP_AAL3, MDP_MM_SUBSYS_1},438 {1, 0, 0}439 },440 [MDP_COMP_RSZ0] = {441 {MDP_COMP_TYPE_RSZ, 0, MT8188_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0},442 {1, 0, 0}443 },444 [MDP_COMP_RSZ2] = {445 {MDP_COMP_TYPE_RSZ, 1, MT8188_MDP_COMP_RSZ2, MDP_MM_SUBSYS_1},446 {2, 0, 0},447 {MDP_COMP_MERGE2, true, true}448 },449 [MDP_COMP_RSZ3] = {450 {MDP_COMP_TYPE_RSZ, 2, MT8188_MDP_COMP_RSZ3, MDP_MM_SUBSYS_1},451 {2, 0, 0},452 {MDP_COMP_MERGE3, true, true}453 },454 [MDP_COMP_TDSHP0] = {455 {MDP_COMP_TYPE_TDSHP, 0, MT8188_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0},456 {1, 0, 0}457 },458 [MDP_COMP_TDSHP2] = {459 {MDP_COMP_TYPE_TDSHP, 1, MT8188_MDP_COMP_TDSHP2, MDP_MM_SUBSYS_1},460 {1, 0, 0}461 },462 [MDP_COMP_TDSHP3] = {463 {MDP_COMP_TYPE_TDSHP, 2, MT8188_MDP_COMP_TDSHP3, MDP_MM_SUBSYS_1},464 {1, 0, 0}465 },466 [MDP_COMP_COLOR0] = {467 {MDP_COMP_TYPE_COLOR, 0, MT8188_MDP_COMP_COLOR0, MDP_MM_SUBSYS_0},468 {1, 0, 0}469 },470 [MDP_COMP_COLOR2] = {471 {MDP_COMP_TYPE_COLOR, 1, MT8188_MDP_COMP_COLOR2, MDP_MM_SUBSYS_1},472 {1, 0, 0}473 },474 [MDP_COMP_COLOR3] = {475 {MDP_COMP_TYPE_COLOR, 2, MT8188_MDP_COMP_COLOR3, MDP_MM_SUBSYS_1},476 {1, 0, 0}477 },478 [MDP_COMP_OVL0] = {479 {MDP_COMP_TYPE_OVL, 0, MT8188_MDP_COMP_OVL0, MDP_MM_SUBSYS_0},480 {1, 0, 0}481 },482 [MDP_COMP_PAD0] = {483 {MDP_COMP_TYPE_PAD, 0, MT8188_MDP_COMP_PAD0, MDP_MM_SUBSYS_0},484 {1, 0, 0}485 },486 [MDP_COMP_PAD2] = {487 {MDP_COMP_TYPE_PAD, 1, MT8188_MDP_COMP_PAD2, MDP_MM_SUBSYS_1},488 {1, 0, 0}489 },490 [MDP_COMP_PAD3] = {491 {MDP_COMP_TYPE_PAD, 2, MT8188_MDP_COMP_PAD3, MDP_MM_SUBSYS_1},492 {1, 0, 0}493 },494 [MDP_COMP_TCC0] = {495 {MDP_COMP_TYPE_TCC, 0, MT8188_MDP_COMP_TCC0, MDP_MM_SUBSYS_0},496 {1, 0, 0}497 },498 [MDP_COMP_WROT0] = {499 {MDP_COMP_TYPE_WROT, 0, MT8188_MDP_COMP_WROT0, MDP_MM_SUBSYS_0},500 {1, 0, 0}501 },502 [MDP_COMP_WROT2] = {503 {MDP_COMP_TYPE_WROT, 1, MT8188_MDP_COMP_WROT2, MDP_MM_SUBSYS_1},504 {1, 0, 0}505 },506 [MDP_COMP_WROT3] = {507 {MDP_COMP_TYPE_WROT, 2, MT8188_MDP_COMP_WROT3, MDP_MM_SUBSYS_1},508 {1, 0, 0}509 },510 [MDP_COMP_MERGE2] = {511 {MDP_COMP_TYPE_MERGE, 0, MT8188_MDP_COMP_MERGE2, MDP_MM_SUBSYS_1},512 {1, 0, 0}513 },514 [MDP_COMP_MERGE3] = {515 {MDP_COMP_TYPE_MERGE, 1, MT8188_MDP_COMP_MERGE3, MDP_MM_SUBSYS_1},516 {1, 0, 0}517 },518 [MDP_COMP_PQ0_SOUT] = {519 {MDP_COMP_TYPE_DUMMY, 0, MT8188_MDP_COMP_PQ0_SOUT, MDP_MM_SUBSYS_0},520 {0, 0, 0}521 },522 [MDP_COMP_TO_WARP0MOUT] = {523 {MDP_COMP_TYPE_DUMMY, 1, MT8188_MDP_COMP_TO_WARP0MOUT, MDP_MM_SUBSYS_0},524 {0, 0, 0}525 },526 [MDP_COMP_TO_SVPP2MOUT] = {527 {MDP_COMP_TYPE_DUMMY, 2, MT8188_MDP_COMP_TO_SVPP2MOUT, MDP_MM_SUBSYS_1},528 {0, 0, 0}529 },530 [MDP_COMP_TO_SVPP3MOUT] = {531 {MDP_COMP_TYPE_DUMMY, 3, MT8188_MDP_COMP_TO_SVPP3MOUT, MDP_MM_SUBSYS_1},532 {0, 0, 0}533 },534 [MDP_COMP_VPP0_SOUT] = {535 {MDP_COMP_TYPE_PATH, 0, MT8188_MDP_COMP_VPP0_SOUT, MDP_MM_SUBSYS_1},536 {2, 6, 0}537 },538 [MDP_COMP_VPP1_SOUT] = {539 {MDP_COMP_TYPE_PATH, 1, MT8188_MDP_COMP_VPP1_SOUT, MDP_MM_SUBSYS_0},540 {2, 8, 0}541 },542};543 544static const struct mdp_comp_data mt8195_mdp_comp_data[MDP_MAX_COMP_COUNT] = {545 [MDP_COMP_WPEI] = {546 {MDP_COMP_TYPE_WPEI, 0, MT8195_MDP_COMP_WPEI, MDP_MM_SUBSYS_0},547 {0, 0, 0}548 },549 [MDP_COMP_WPEO] = {550 {MDP_COMP_TYPE_EXTO, 2, MT8195_MDP_COMP_WPEO, MDP_MM_SUBSYS_0},551 {0, 0, 0}552 },553 [MDP_COMP_WPEI2] = {554 {MDP_COMP_TYPE_WPEI, 1, MT8195_MDP_COMP_WPEI2, MDP_MM_SUBSYS_0},555 {0, 0, 0}556 },557 [MDP_COMP_WPEO2] = {558 {MDP_COMP_TYPE_EXTO, 3, MT8195_MDP_COMP_WPEO2, MDP_MM_SUBSYS_0},559 {0, 0, 0}560 },561 [MDP_COMP_CAMIN] = {562 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0},563 {3, 3, 0}564 },565 [MDP_COMP_CAMIN2] = {566 {MDP_COMP_TYPE_DL_PATH, 1, MT8195_MDP_COMP_CAMIN2, MDP_MM_SUBSYS_0},567 {3, 6, 0}568 },569 [MDP_COMP_SPLIT] = {570 {MDP_COMP_TYPE_SPLIT, 0, MT8195_MDP_COMP_SPLIT, MDP_MM_SUBSYS_1},571 {7, 0, 0}572 },573 [MDP_COMP_SPLIT2] = {574 {MDP_COMP_TYPE_SPLIT, 1, MT8195_MDP_COMP_SPLIT2, MDP_MM_SUBSYS_1},575 {7, 0, 0}576 },577 [MDP_COMP_RDMA0] = {578 {MDP_COMP_TYPE_RDMA, 0, MT8195_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0},579 {3, 0, 0}580 },581 [MDP_COMP_RDMA1] = {582 {MDP_COMP_TYPE_RDMA, 1, MT8195_MDP_COMP_RDMA1, MDP_MM_SUBSYS_1},583 {3, 0, 0}584 },585 [MDP_COMP_RDMA2] = {586 {MDP_COMP_TYPE_RDMA, 2, MT8195_MDP_COMP_RDMA2, MDP_MM_SUBSYS_1},587 {3, 0, 0}588 },589 [MDP_COMP_RDMA3] = {590 {MDP_COMP_TYPE_RDMA, 3, MT8195_MDP_COMP_RDMA3, MDP_MM_SUBSYS_1},591 {3, 0, 0}592 },593 [MDP_COMP_STITCH] = {594 {MDP_COMP_TYPE_STITCH, 0, MT8195_MDP_COMP_STITCH, MDP_MM_SUBSYS_0},595 {1, 0, 0}596 },597 [MDP_COMP_FG0] = {598 {MDP_COMP_TYPE_FG, 0, MT8195_MDP_COMP_FG0, MDP_MM_SUBSYS_0},599 {1, 0, 0}600 },601 [MDP_COMP_FG1] = {602 {MDP_COMP_TYPE_FG, 1, MT8195_MDP_COMP_FG1, MDP_MM_SUBSYS_1},603 {1, 0, 0}604 },605 [MDP_COMP_FG2] = {606 {MDP_COMP_TYPE_FG, 2, MT8195_MDP_COMP_FG2, MDP_MM_SUBSYS_1},607 {1, 0, 0}608 },609 [MDP_COMP_FG3] = {610 {MDP_COMP_TYPE_FG, 3, MT8195_MDP_COMP_FG3, MDP_MM_SUBSYS_1},611 {1, 0, 0}612 },613 [MDP_COMP_HDR0] = {614 {MDP_COMP_TYPE_HDR, 0, MT8195_MDP_COMP_HDR0, MDP_MM_SUBSYS_0},615 {1, 0, 0}616 },617 [MDP_COMP_HDR1] = {618 {MDP_COMP_TYPE_HDR, 1, MT8195_MDP_COMP_HDR1, MDP_MM_SUBSYS_1},619 {1, 0, 0}620 },621 [MDP_COMP_HDR2] = {622 {MDP_COMP_TYPE_HDR, 2, MT8195_MDP_COMP_HDR2, MDP_MM_SUBSYS_1},623 {1, 0, 0}624 },625 [MDP_COMP_HDR3] = {626 {MDP_COMP_TYPE_HDR, 3, MT8195_MDP_COMP_HDR3, MDP_MM_SUBSYS_1},627 {1, 0, 0}628 },629 [MDP_COMP_AAL0] = {630 {MDP_COMP_TYPE_AAL, 0, MT8195_MDP_COMP_AAL0, MDP_MM_SUBSYS_0},631 {1, 0, 0}632 },633 [MDP_COMP_AAL1] = {634 {MDP_COMP_TYPE_AAL, 1, MT8195_MDP_COMP_AAL1, MDP_MM_SUBSYS_1},635 {1, 0, 0}636 },637 [MDP_COMP_AAL2] = {638 {MDP_COMP_TYPE_AAL, 2, MT8195_MDP_COMP_AAL2, MDP_MM_SUBSYS_1},639 {1, 0, 0}640 },641 [MDP_COMP_AAL3] = {642 {MDP_COMP_TYPE_AAL, 3, MT8195_MDP_COMP_AAL3, MDP_MM_SUBSYS_1},643 {1, 0, 0}644 },645 [MDP_COMP_RSZ0] = {646 {MDP_COMP_TYPE_RSZ, 0, MT8195_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0},647 {1, 0, 0}648 },649 [MDP_COMP_RSZ1] = {650 {MDP_COMP_TYPE_RSZ, 1, MT8195_MDP_COMP_RSZ1, MDP_MM_SUBSYS_1},651 {1, 0, 0}652 },653 [MDP_COMP_RSZ2] = {654 {MDP_COMP_TYPE_RSZ, 2, MT8195_MDP_COMP_RSZ2, MDP_MM_SUBSYS_1},655 {2, 0, 0},656 {MDP_COMP_MERGE2, true, true}657 },658 [MDP_COMP_RSZ3] = {659 {MDP_COMP_TYPE_RSZ, 3, MT8195_MDP_COMP_RSZ3, MDP_MM_SUBSYS_1},660 {2, 0, 0},661 {MDP_COMP_MERGE3, true, true}662 },663 [MDP_COMP_TDSHP0] = {664 {MDP_COMP_TYPE_TDSHP, 0, MT8195_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0},665 {1, 0, 0}666 },667 [MDP_COMP_TDSHP1] = {668 {MDP_COMP_TYPE_TDSHP, 1, MT8195_MDP_COMP_TDSHP1, MDP_MM_SUBSYS_1},669 {1, 0, 0}670 },671 [MDP_COMP_TDSHP2] = {672 {MDP_COMP_TYPE_TDSHP, 2, MT8195_MDP_COMP_TDSHP2, MDP_MM_SUBSYS_1},673 {1, 0, 0}674 },675 [MDP_COMP_TDSHP3] = {676 {MDP_COMP_TYPE_TDSHP, 3, MT8195_MDP_COMP_TDSHP3, MDP_MM_SUBSYS_1},677 {1, 0, 0}678 },679 [MDP_COMP_COLOR0] = {680 {MDP_COMP_TYPE_COLOR, 0, MT8195_MDP_COMP_COLOR0, MDP_MM_SUBSYS_0},681 {1, 0, 0}682 },683 [MDP_COMP_COLOR1] = {684 {MDP_COMP_TYPE_COLOR, 1, MT8195_MDP_COMP_COLOR1, MDP_MM_SUBSYS_1},685 {1, 0, 0}686 },687 [MDP_COMP_COLOR2] = {688 {MDP_COMP_TYPE_COLOR, 2, MT8195_MDP_COMP_COLOR2, MDP_MM_SUBSYS_1},689 {1, 0, 0}690 },691 [MDP_COMP_COLOR3] = {692 {MDP_COMP_TYPE_COLOR, 3, MT8195_MDP_COMP_COLOR3, MDP_MM_SUBSYS_1},693 {1, 0, 0}694 },695 [MDP_COMP_OVL0] = {696 {MDP_COMP_TYPE_OVL, 0, MT8195_MDP_COMP_OVL0, MDP_MM_SUBSYS_0},697 {1, 0, 0}698 },699 [MDP_COMP_OVL1] = {700 {MDP_COMP_TYPE_OVL, 1, MT8195_MDP_COMP_OVL1, MDP_MM_SUBSYS_1},701 {1, 0, 0}702 },703 [MDP_COMP_PAD0] = {704 {MDP_COMP_TYPE_PAD, 0, MT8195_MDP_COMP_PAD0, MDP_MM_SUBSYS_0},705 {1, 0, 0}706 },707 [MDP_COMP_PAD1] = {708 {MDP_COMP_TYPE_PAD, 1, MT8195_MDP_COMP_PAD1, MDP_MM_SUBSYS_1},709 {1, 0, 0}710 },711 [MDP_COMP_PAD2] = {712 {MDP_COMP_TYPE_PAD, 2, MT8195_MDP_COMP_PAD2, MDP_MM_SUBSYS_1},713 {1, 0, 0}714 },715 [MDP_COMP_PAD3] = {716 {MDP_COMP_TYPE_PAD, 3, MT8195_MDP_COMP_PAD3, MDP_MM_SUBSYS_1},717 {1, 0, 0}718 },719 [MDP_COMP_TCC0] = {720 {MDP_COMP_TYPE_TCC, 0, MT8195_MDP_COMP_TCC0, MDP_MM_SUBSYS_0},721 {1, 0, 0}722 },723 [MDP_COMP_TCC1] = {724 {MDP_COMP_TYPE_TCC, 1, MT8195_MDP_COMP_TCC1, MDP_MM_SUBSYS_1},725 {1, 0, 0}726 },727 [MDP_COMP_WROT0] = {728 {MDP_COMP_TYPE_WROT, 0, MT8195_MDP_COMP_WROT0, MDP_MM_SUBSYS_0},729 {1, 0, 0}730 },731 [MDP_COMP_WROT1] = {732 {MDP_COMP_TYPE_WROT, 1, MT8195_MDP_COMP_WROT1, MDP_MM_SUBSYS_1},733 {1, 0, 0}734 },735 [MDP_COMP_WROT2] = {736 {MDP_COMP_TYPE_WROT, 2, MT8195_MDP_COMP_WROT2, MDP_MM_SUBSYS_1},737 {1, 0, 0}738 },739 [MDP_COMP_WROT3] = {740 {MDP_COMP_TYPE_WROT, 3, MT8195_MDP_COMP_WROT3, MDP_MM_SUBSYS_1},741 {1, 0, 0}742 },743 [MDP_COMP_MERGE2] = {744 {MDP_COMP_TYPE_MERGE, 0, MT8195_MDP_COMP_MERGE2, MDP_MM_SUBSYS_1},745 {1, 0, 0}746 },747 [MDP_COMP_MERGE3] = {748 {MDP_COMP_TYPE_MERGE, 1, MT8195_MDP_COMP_MERGE3, MDP_MM_SUBSYS_1},749 {1, 0, 0}750 },751 [MDP_COMP_PQ0_SOUT] = {752 {MDP_COMP_TYPE_DUMMY, 0, MT8195_MDP_COMP_PQ0_SOUT, MDP_MM_SUBSYS_0},753 {0, 0, 0}754 },755 [MDP_COMP_PQ1_SOUT] = {756 {MDP_COMP_TYPE_DUMMY, 1, MT8195_MDP_COMP_PQ1_SOUT, MDP_MM_SUBSYS_1},757 {0, 0, 0}758 },759 [MDP_COMP_TO_WARP0MOUT] = {760 {MDP_COMP_TYPE_DUMMY, 2, MT8195_MDP_COMP_TO_WARP0MOUT, MDP_MM_SUBSYS_0},761 {0, 0, 0}762 },763 [MDP_COMP_TO_WARP1MOUT] = {764 {MDP_COMP_TYPE_DUMMY, 3, MT8195_MDP_COMP_TO_WARP1MOUT, MDP_MM_SUBSYS_0},765 {0, 0, 0}766 },767 [MDP_COMP_TO_SVPP2MOUT] = {768 {MDP_COMP_TYPE_DUMMY, 4, MT8195_MDP_COMP_TO_SVPP2MOUT, MDP_MM_SUBSYS_1},769 {0, 0, 0}770 },771 [MDP_COMP_TO_SVPP3MOUT] = {772 {MDP_COMP_TYPE_DUMMY, 5, MT8195_MDP_COMP_TO_SVPP3MOUT, MDP_MM_SUBSYS_1},773 {0, 0, 0}774 },775 [MDP_COMP_VPP0_SOUT] = {776 {MDP_COMP_TYPE_PATH, 0, MT8195_MDP_COMP_VPP0_SOUT, MDP_MM_SUBSYS_1},777 {4, 9, 0}778 },779 [MDP_COMP_VPP1_SOUT] = {780 {MDP_COMP_TYPE_PATH, 1, MT8195_MDP_COMP_VPP1_SOUT, MDP_MM_SUBSYS_0},781 {2, 13, 0}782 },783 [MDP_COMP_VDO0DL0] = {784 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL0, MDP_MM_SUBSYS_1},785 {1, 15, 0}786 },787 [MDP_COMP_VDO1DL0] = {788 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL0, MDP_MM_SUBSYS_1},789 {1, 17, 0}790 },791 [MDP_COMP_VDO0DL1] = {792 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO0DL1, MDP_MM_SUBSYS_1},793 {1, 18, 0}794 },795 [MDP_COMP_VDO1DL1] = {796 {MDP_COMP_TYPE_DL_PATH, 0, MT8195_MDP_COMP_VDO1DL1, MDP_MM_SUBSYS_1},797 {1, 16, 0}798 },799};800 801static const struct of_device_id mt8183_sub_comp_dt_ids[] = {802 {803 .compatible = "mediatek,mt8183-mdp3-wdma",804 .data = (void *)MDP_COMP_TYPE_PATH,805 }, {806 .compatible = "mediatek,mt8183-mdp3-wrot",807 .data = (void *)MDP_COMP_TYPE_PATH,808 },809 {}810};811 812static const struct of_device_id mt8195_sub_comp_dt_ids[] = {813 {}814};815 816/*817 * All 10-bit related formats are not added in the basic format list,818 * please add the corresponding format settings before use.819 */820static const struct mdp_format mt8183_formats[] = {821 {822 .pixelformat = V4L2_PIX_FMT_GREY,823 .mdp_color = MDP_COLOR_GREY,824 .depth = { 8 },825 .row_depth = { 8 },826 .num_planes = 1,827 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,828 }, {829 .pixelformat = V4L2_PIX_FMT_RGB565X,830 .mdp_color = MDP_COLOR_BGR565,831 .depth = { 16 },832 .row_depth = { 16 },833 .num_planes = 1,834 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,835 }, {836 .pixelformat = V4L2_PIX_FMT_RGB565,837 .mdp_color = MDP_COLOR_RGB565,838 .depth = { 16 },839 .row_depth = { 16 },840 .num_planes = 1,841 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,842 }, {843 .pixelformat = V4L2_PIX_FMT_RGB24,844 .mdp_color = MDP_COLOR_RGB888,845 .depth = { 24 },846 .row_depth = { 24 },847 .num_planes = 1,848 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,849 }, {850 .pixelformat = V4L2_PIX_FMT_BGR24,851 .mdp_color = MDP_COLOR_BGR888,852 .depth = { 24 },853 .row_depth = { 24 },854 .num_planes = 1,855 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,856 }, {857 .pixelformat = V4L2_PIX_FMT_ABGR32,858 .mdp_color = MDP_COLOR_BGRA8888,859 .depth = { 32 },860 .row_depth = { 32 },861 .num_planes = 1,862 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,863 }, {864 .pixelformat = V4L2_PIX_FMT_ARGB32,865 .mdp_color = MDP_COLOR_ARGB8888,866 .depth = { 32 },867 .row_depth = { 32 },868 .num_planes = 1,869 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,870 }, {871 .pixelformat = V4L2_PIX_FMT_UYVY,872 .mdp_color = MDP_COLOR_UYVY,873 .depth = { 16 },874 .row_depth = { 16 },875 .num_planes = 1,876 .walign = 1,877 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,878 }, {879 .pixelformat = V4L2_PIX_FMT_VYUY,880 .mdp_color = MDP_COLOR_VYUY,881 .depth = { 16 },882 .row_depth = { 16 },883 .num_planes = 1,884 .walign = 1,885 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,886 }, {887 .pixelformat = V4L2_PIX_FMT_YUYV,888 .mdp_color = MDP_COLOR_YUYV,889 .depth = { 16 },890 .row_depth = { 16 },891 .num_planes = 1,892 .walign = 1,893 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,894 }, {895 .pixelformat = V4L2_PIX_FMT_YVYU,896 .mdp_color = MDP_COLOR_YVYU,897 .depth = { 16 },898 .row_depth = { 16 },899 .num_planes = 1,900 .walign = 1,901 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,902 }, {903 .pixelformat = V4L2_PIX_FMT_YUV420,904 .mdp_color = MDP_COLOR_I420,905 .depth = { 12 },906 .row_depth = { 8 },907 .num_planes = 1,908 .walign = 1,909 .halign = 1,910 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,911 }, {912 .pixelformat = V4L2_PIX_FMT_YVU420,913 .mdp_color = MDP_COLOR_YV12,914 .depth = { 12 },915 .row_depth = { 8 },916 .num_planes = 1,917 .walign = 1,918 .halign = 1,919 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,920 }, {921 .pixelformat = V4L2_PIX_FMT_NV12,922 .mdp_color = MDP_COLOR_NV12,923 .depth = { 12 },924 .row_depth = { 8 },925 .num_planes = 1,926 .walign = 1,927 .halign = 1,928 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,929 }, {930 .pixelformat = V4L2_PIX_FMT_NV21,931 .mdp_color = MDP_COLOR_NV21,932 .depth = { 12 },933 .row_depth = { 8 },934 .num_planes = 1,935 .walign = 1,936 .halign = 1,937 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,938 }, {939 .pixelformat = V4L2_PIX_FMT_NV16,940 .mdp_color = MDP_COLOR_NV16,941 .depth = { 16 },942 .row_depth = { 8 },943 .num_planes = 1,944 .walign = 1,945 .flags = MDP_FMT_FLAG_OUTPUT,946 }, {947 .pixelformat = V4L2_PIX_FMT_NV61,948 .mdp_color = MDP_COLOR_NV61,949 .depth = { 16 },950 .row_depth = { 8 },951 .num_planes = 1,952 .walign = 1,953 .flags = MDP_FMT_FLAG_OUTPUT,954 }, {955 .pixelformat = V4L2_PIX_FMT_NV24,956 .mdp_color = MDP_COLOR_NV24,957 .depth = { 24 },958 .row_depth = { 8 },959 .num_planes = 1,960 .flags = MDP_FMT_FLAG_OUTPUT,961 }, {962 .pixelformat = V4L2_PIX_FMT_NV42,963 .mdp_color = MDP_COLOR_NV42,964 .depth = { 24 },965 .row_depth = { 8 },966 .num_planes = 1,967 .flags = MDP_FMT_FLAG_OUTPUT,968 }, {969 .pixelformat = V4L2_PIX_FMT_MT21C,970 .mdp_color = MDP_COLOR_420_BLK_UFO,971 .depth = { 8, 4 },972 .row_depth = { 8, 8 },973 .num_planes = 2,974 .walign = 4,975 .halign = 5,976 .flags = MDP_FMT_FLAG_OUTPUT,977 }, {978 .pixelformat = V4L2_PIX_FMT_MM21,979 .mdp_color = MDP_COLOR_420_BLK,980 .depth = { 8, 4 },981 .row_depth = { 8, 8 },982 .num_planes = 2,983 .walign = 4,984 .halign = 5,985 .flags = MDP_FMT_FLAG_OUTPUT,986 }, {987 .pixelformat = V4L2_PIX_FMT_NV12M,988 .mdp_color = MDP_COLOR_NV12,989 .depth = { 8, 4 },990 .row_depth = { 8, 8 },991 .num_planes = 2,992 .walign = 1,993 .halign = 1,994 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,995 }, {996 .pixelformat = V4L2_PIX_FMT_NV21M,997 .mdp_color = MDP_COLOR_NV21,998 .depth = { 8, 4 },999 .row_depth = { 8, 8 },1000 .num_planes = 2,1001 .walign = 1,1002 .halign = 1,1003 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1004 }, {1005 .pixelformat = V4L2_PIX_FMT_NV16M,1006 .mdp_color = MDP_COLOR_NV16,1007 .depth = { 8, 8 },1008 .row_depth = { 8, 8 },1009 .num_planes = 2,1010 .walign = 1,1011 .flags = MDP_FMT_FLAG_OUTPUT,1012 }, {1013 .pixelformat = V4L2_PIX_FMT_NV61M,1014 .mdp_color = MDP_COLOR_NV61,1015 .depth = { 8, 8 },1016 .row_depth = { 8, 8 },1017 .num_planes = 2,1018 .walign = 1,1019 .flags = MDP_FMT_FLAG_OUTPUT,1020 }, {1021 .pixelformat = V4L2_PIX_FMT_YUV420M,1022 .mdp_color = MDP_COLOR_I420,1023 .depth = { 8, 2, 2 },1024 .row_depth = { 8, 4, 4 },1025 .num_planes = 3,1026 .walign = 1,1027 .halign = 1,1028 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1029 }, {1030 .pixelformat = V4L2_PIX_FMT_YVU420M,1031 .mdp_color = MDP_COLOR_YV12,1032 .depth = { 8, 2, 2 },1033 .row_depth = { 8, 4, 4 },1034 .num_planes = 3,1035 .walign = 1,1036 .halign = 1,1037 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1038 }1039};1040 1041static const struct mdp_format mt8195_formats[] = {1042 {1043 .pixelformat = V4L2_PIX_FMT_GREY,1044 .mdp_color = MDP_COLOR_GREY,1045 .depth = { 8 },1046 .row_depth = { 8 },1047 .num_planes = 1,1048 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1049 }, {1050 .pixelformat = V4L2_PIX_FMT_RGB565X,1051 .mdp_color = MDP_COLOR_BGR565,1052 .depth = { 16 },1053 .row_depth = { 16 },1054 .num_planes = 1,1055 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1056 }, {1057 .pixelformat = V4L2_PIX_FMT_RGB565,1058 .mdp_color = MDP_COLOR_RGB565,1059 .depth = { 16 },1060 .row_depth = { 16 },1061 .num_planes = 1,1062 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1063 }, {1064 .pixelformat = V4L2_PIX_FMT_RGB24,1065 .mdp_color = MDP_COLOR_RGB888,1066 .depth = { 24 },1067 .row_depth = { 24 },1068 .num_planes = 1,1069 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1070 }, {1071 .pixelformat = V4L2_PIX_FMT_BGR24,1072 .mdp_color = MDP_COLOR_BGR888,1073 .depth = { 24 },1074 .row_depth = { 24 },1075 .num_planes = 1,1076 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1077 }, {1078 .pixelformat = V4L2_PIX_FMT_ABGR32,1079 .mdp_color = MDP_COLOR_BGRA8888,1080 .depth = { 32 },1081 .row_depth = { 32 },1082 .num_planes = 1,1083 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1084 }, {1085 .pixelformat = V4L2_PIX_FMT_ARGB32,1086 .mdp_color = MDP_COLOR_ARGB8888,1087 .depth = { 32 },1088 .row_depth = { 32 },1089 .num_planes = 1,1090 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1091 }, {1092 .pixelformat = V4L2_PIX_FMT_UYVY,1093 .mdp_color = MDP_COLOR_UYVY,1094 .depth = { 16 },1095 .row_depth = { 16 },1096 .num_planes = 1,1097 .walign = 1,1098 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1099 }, {1100 .pixelformat = V4L2_PIX_FMT_VYUY,1101 .mdp_color = MDP_COLOR_VYUY,1102 .depth = { 16 },1103 .row_depth = { 16 },1104 .num_planes = 1,1105 .walign = 1,1106 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1107 }, {1108 .pixelformat = V4L2_PIX_FMT_YUYV,1109 .mdp_color = MDP_COLOR_YUYV,1110 .depth = { 16 },1111 .row_depth = { 16 },1112 .num_planes = 1,1113 .walign = 1,1114 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1115 }, {1116 .pixelformat = V4L2_PIX_FMT_YVYU,1117 .mdp_color = MDP_COLOR_YVYU,1118 .depth = { 16 },1119 .row_depth = { 16 },1120 .num_planes = 1,1121 .walign = 1,1122 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1123 }, {1124 .pixelformat = V4L2_PIX_FMT_YUV420,1125 .mdp_color = MDP_COLOR_I420,1126 .depth = { 12 },1127 .row_depth = { 8 },1128 .num_planes = 1,1129 .walign = 1,1130 .halign = 1,1131 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1132 }, {1133 .pixelformat = V4L2_PIX_FMT_YVU420,1134 .mdp_color = MDP_COLOR_YV12,1135 .depth = { 12 },1136 .row_depth = { 8 },1137 .num_planes = 1,1138 .walign = 1,1139 .halign = 1,1140 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1141 }, {1142 .pixelformat = V4L2_PIX_FMT_NV12,1143 .mdp_color = MDP_COLOR_NV12,1144 .depth = { 12 },1145 .row_depth = { 8 },1146 .num_planes = 1,1147 .walign = 1,1148 .halign = 1,1149 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1150 }, {1151 .pixelformat = V4L2_PIX_FMT_NV21,1152 .mdp_color = MDP_COLOR_NV21,1153 .depth = { 12 },1154 .row_depth = { 8 },1155 .num_planes = 1,1156 .walign = 1,1157 .halign = 1,1158 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1159 }, {1160 .pixelformat = V4L2_PIX_FMT_NV16,1161 .mdp_color = MDP_COLOR_NV16,1162 .depth = { 16 },1163 .row_depth = { 8 },1164 .num_planes = 1,1165 .walign = 1,1166 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1167 }, {1168 .pixelformat = V4L2_PIX_FMT_NV61,1169 .mdp_color = MDP_COLOR_NV61,1170 .depth = { 16 },1171 .row_depth = { 8 },1172 .num_planes = 1,1173 .walign = 1,1174 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1175 }, {1176 .pixelformat = V4L2_PIX_FMT_NV12M,1177 .mdp_color = MDP_COLOR_NV12,1178 .depth = { 8, 4 },1179 .row_depth = { 8, 8 },1180 .num_planes = 2,1181 .walign = 1,1182 .halign = 1,1183 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1184 }, {1185 .pixelformat = V4L2_PIX_FMT_MM21,1186 .mdp_color = MDP_COLOR_420_BLK,1187 .depth = { 8, 4 },1188 .row_depth = { 8, 8 },1189 .num_planes = 2,1190 .walign = 6,1191 .halign = 6,1192 .flags = MDP_FMT_FLAG_OUTPUT,1193 }, {1194 .pixelformat = V4L2_PIX_FMT_NV21M,1195 .mdp_color = MDP_COLOR_NV21,1196 .depth = { 8, 4 },1197 .row_depth = { 8, 8 },1198 .num_planes = 2,1199 .walign = 1,1200 .halign = 1,1201 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1202 }, {1203 .pixelformat = V4L2_PIX_FMT_NV16M,1204 .mdp_color = MDP_COLOR_NV16,1205 .depth = { 8, 8 },1206 .row_depth = { 8, 8 },1207 .num_planes = 2,1208 .walign = 1,1209 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1210 }, {1211 .pixelformat = V4L2_PIX_FMT_NV61M,1212 .mdp_color = MDP_COLOR_NV61,1213 .depth = { 8, 8 },1214 .row_depth = { 8, 8 },1215 .num_planes = 2,1216 .walign = 1,1217 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1218 }, {1219 .pixelformat = V4L2_PIX_FMT_YUV420M,1220 .mdp_color = MDP_COLOR_I420,1221 .depth = { 8, 2, 2 },1222 .row_depth = { 8, 4, 4 },1223 .num_planes = 3,1224 .walign = 1,1225 .halign = 1,1226 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1227 }, {1228 .pixelformat = V4L2_PIX_FMT_YVU420M,1229 .mdp_color = MDP_COLOR_YV12,1230 .depth = { 8, 2, 2 },1231 .row_depth = { 8, 4, 4 },1232 .num_planes = 3,1233 .walign = 1,1234 .halign = 1,1235 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1236 }, {1237 .pixelformat = V4L2_PIX_FMT_YUV422M,1238 .mdp_color = MDP_COLOR_I422,1239 .depth = { 8, 4, 4 },1240 .row_depth = { 8, 4, 4 },1241 .num_planes = 3,1242 .walign = 1,1243 .halign = 1,1244 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1245 }, {1246 .pixelformat = V4L2_PIX_FMT_YVU422M,1247 .mdp_color = MDP_COLOR_YV16,1248 .depth = { 8, 4, 4 },1249 .row_depth = { 8, 4, 4 },1250 .num_planes = 3,1251 .walign = 1,1252 .halign = 1,1253 .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,1254 }1255};1256 1257static const struct mdp_limit mt8183_mdp_def_limit = {1258 .out_limit = {1259 .wmin = 16,1260 .hmin = 16,1261 .wmax = 8176,1262 .hmax = 8176,1263 },1264 .cap_limit = {1265 .wmin = 2,1266 .hmin = 2,1267 .wmax = 8176,1268 .hmax = 8176,1269 },1270 .h_scale_up_max = 32,1271 .v_scale_up_max = 32,1272 .h_scale_down_max = 20,1273 .v_scale_down_max = 128,1274};1275 1276static const struct mdp_limit mt8195_mdp_def_limit = {1277 .out_limit = {1278 .wmin = 64,1279 .hmin = 64,1280 .wmax = 8192,1281 .hmax = 8192,1282 },1283 .cap_limit = {1284 .wmin = 64,1285 .hmin = 64,1286 .wmax = 8192,1287 .hmax = 8192,1288 },1289 .h_scale_up_max = 64,1290 .v_scale_up_max = 64,1291 .h_scale_down_max = 128,1292 .v_scale_down_max = 128,1293};1294 1295static const struct mdp_pipe_info mt8183_pipe_info[] = {1296 [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0},1297 [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1},1298 [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, MDP_MM_SUBSYS_0, 2},1299 [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3}1300};1301 1302static const struct mdp_pipe_info mt8188_pipe_info[] = {1303 [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0},1304 [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 1},1305 [MDP_PIPE_RDMA2] = {MDP_PIPE_RDMA2, MDP_MM_SUBSYS_1, 0},1306 [MDP_PIPE_RDMA3] = {MDP_PIPE_RDMA3, MDP_MM_SUBSYS_1, 1},1307 [MDP_PIPE_VPP1_SOUT] = {MDP_PIPE_VPP1_SOUT, MDP_MM_SUBSYS_0, 2},1308 [MDP_PIPE_VPP0_SOUT] = {MDP_PIPE_VPP0_SOUT, MDP_MM_SUBSYS_1, 2},1309};1310 1311static const struct mdp_pipe_info mt8195_pipe_info[] = {1312 [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0},1313 [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1},1314 [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, MDP_MM_SUBSYS_0, 2},1315 [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3},1316 [MDP_PIPE_RDMA1] = {MDP_PIPE_RDMA1, MDP_MM_SUBSYS_1, 0},1317 [MDP_PIPE_RDMA2] = {MDP_PIPE_RDMA2, MDP_MM_SUBSYS_1, 1},1318 [MDP_PIPE_RDMA3] = {MDP_PIPE_RDMA3, MDP_MM_SUBSYS_1, 2},1319 [MDP_PIPE_SPLIT] = {MDP_PIPE_SPLIT, MDP_MM_SUBSYS_1, 3},1320 [MDP_PIPE_SPLIT2] = {MDP_PIPE_SPLIT2, MDP_MM_SUBSYS_1, 4},1321 [MDP_PIPE_VPP1_SOUT] = {MDP_PIPE_VPP1_SOUT, MDP_MM_SUBSYS_0, 4},1322 [MDP_PIPE_VPP0_SOUT] = {MDP_PIPE_VPP0_SOUT, MDP_MM_SUBSYS_1, 5},1323};1324 1325static const struct v4l2_rect mt8195_mdp_pp_criteria = {1326 .width = 1920,1327 .height = 1080,1328};1329 1330const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {1331 .mdp_plat_id = MT8183,1332 .mdp_con_res = 0x14001000,1333 .mdp_probe_infra = mt8183_mdp_probe_infra,1334 .mdp_cfg = &mt8183_plat_cfg,1335 .mdp_mutex_table_idx = mt8183_mutex_idx,1336 .comp_data = mt8183_mdp_comp_data,1337 .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data),1338 .mdp_sub_comp_dt_ids = mt8183_sub_comp_dt_ids,1339 .format = mt8183_formats,1340 .format_len = ARRAY_SIZE(mt8183_formats),1341 .def_limit = &mt8183_mdp_def_limit,1342 .pipe_info = mt8183_pipe_info,1343 .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info),1344 .pp_used = MDP_PP_USED_1,1345};1346 1347const struct mtk_mdp_driver_data mt8188_mdp_driver_data = {1348 .mdp_plat_id = MT8188,1349 .mdp_con_res = 0x14001000,1350 .mdp_probe_infra = mt8188_mdp_probe_infra,1351 .mdp_sub_comp_dt_ids = mt8195_sub_comp_dt_ids,1352 .mdp_cfg = &mt8195_plat_cfg,1353 .mdp_mutex_table_idx = mt8188_mutex_idx,1354 .comp_data = mt8188_mdp_comp_data,1355 .comp_data_len = ARRAY_SIZE(mt8188_mdp_comp_data),1356 .format = mt8195_formats,1357 .format_len = ARRAY_SIZE(mt8195_formats),1358 .def_limit = &mt8195_mdp_def_limit,1359 .pipe_info = mt8188_pipe_info,1360 .pipe_info_len = ARRAY_SIZE(mt8188_pipe_info),1361 .pp_criteria = &mt8195_mdp_pp_criteria,1362 .pp_used = MDP_PP_USED_2,1363};1364 1365const struct mtk_mdp_driver_data mt8195_mdp_driver_data = {1366 .mdp_plat_id = MT8195,1367 .mdp_con_res = 0x14001000,1368 .mdp_probe_infra = mt8195_mdp_probe_infra,1369 .mdp_sub_comp_dt_ids = mt8195_sub_comp_dt_ids,1370 .mdp_cfg = &mt8195_plat_cfg,1371 .mdp_mutex_table_idx = mt8195_mutex_idx,1372 .comp_data = mt8195_mdp_comp_data,1373 .comp_data_len = ARRAY_SIZE(mt8195_mdp_comp_data),1374 .format = mt8195_formats,1375 .format_len = ARRAY_SIZE(mt8195_formats),1376 .def_limit = &mt8195_mdp_def_limit,1377 .pipe_info = mt8195_pipe_info,1378 .pipe_info_len = ARRAY_SIZE(mt8195_pipe_info),1379 .pp_criteria = &mt8195_mdp_pp_criteria,1380 .pp_used = MDP_PP_USED_2,1381};1382 1383s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id)1384{1385 if (!mdp_dev)1386 return MDP_COMP_NONE;1387 if (id <= MDP_COMP_NONE || id >= MDP_MAX_COMP_COUNT)1388 return MDP_COMP_NONE;1389 1390 return mdp_dev->mdp_data->comp_data[id].match.inner_id;1391}1392 1393enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 inner_id)1394{1395 enum mtk_mdp_comp_id public_id = MDP_COMP_NONE;1396 u32 i;1397 1398 if (IS_ERR(mdp_dev) || !inner_id)1399 goto err_public_id;1400 1401 for (i = 0; i < MDP_MAX_COMP_COUNT; i++) {1402 if (mdp_dev->mdp_data->comp_data[i].match.inner_id == inner_id) {1403 public_id = i;1404 return public_id;1405 }1406 }1407 1408err_public_id:1409 return public_id;1410}1411 1412bool mdp_cfg_comp_is_dummy(struct mdp_dev *mdp_dev, s32 inner_id)1413{1414 enum mtk_mdp_comp_id id = mdp_cfg_get_id_public(mdp_dev, inner_id);1415 enum mdp_comp_type type = mdp_dev->mdp_data->comp_data[id].match.type;1416 1417 return (type == MDP_COMP_TYPE_DUMMY);1418}1419