32 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>5 */6 7#ifndef __MDP_REG_HDR_H__8#define __MDP_REG_HDR_H__9 10#define MDP_HDR_TOP (0x000)11#define MDP_HDR_RELAY (0x004)12#define MDP_HDR_SIZE_0 (0x014)13#define MDP_HDR_SIZE_1 (0x018)14#define MDP_HDR_SIZE_2 (0x01C)15#define MDP_HDR_HIST_CTRL_0 (0x020)16#define MDP_HDR_HIST_CTRL_1 (0x024)17#define MDP_HDR_HIST_ADDR (0x0DC)18#define MDP_HDR_TILE_POS (0x118)19 20/* MASK */21#define MDP_HDR_RELAY_MASK (0x01)22#define MDP_HDR_TOP_MASK (0xFF0FEB6D)23#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF)24#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF)25#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF)26#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF)27#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF)28#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F)29#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF)30 31#endif // __MDP_REG_HDR_H__32