90 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>5 */6 7#ifndef __MDP_REG_RDMA_H__8#define __MDP_REG_RDMA_H__9 10#define MDP_RDMA_EN 0x00011#define MDP_RDMA_RESET 0x00812#define MDP_RDMA_CON 0x02013#define MDP_RDMA_GMCIF_CON 0x02814#define MDP_RDMA_SRC_CON 0x03015#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x06016#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x06817#define MDP_RDMA_MF_SRC_SIZE 0x07018#define MDP_RDMA_MF_CLIP_SIZE 0x07819#define MDP_RDMA_MF_OFFSET_1 0x08020#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x09021#define MDP_RDMA_SRC_END_0 0x10022#define MDP_RDMA_SRC_END_1 0x10823#define MDP_RDMA_SRC_END_2 0x11024#define MDP_RDMA_SRC_OFFSET_0 0x11825#define MDP_RDMA_SRC_OFFSET_1 0x12026#define MDP_RDMA_SRC_OFFSET_2 0x12827#define MDP_RDMA_SRC_OFFSET_0_P 0x14828#define MDP_RDMA_TRANSFORM_0 0x20029#define MDP_RDMA_DMABUF_CON_0 0x24030#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x24831#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x25032#define MDP_RDMA_DMABUF_CON_1 0x25833#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x26034#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x26835#define MDP_RDMA_DMABUF_CON_2 0x27036#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x27837#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x28038#define MDP_RDMA_DMABUF_CON_3 0x28839#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x29040#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x29841#define MDP_RDMA_RESV_DUMMY_0 0x2a042#define MDP_RDMA_MON_STA_1 0x40843#define MDP_RDMA_SRC_BASE_0 0xf0044#define MDP_RDMA_SRC_BASE_1 0xf0845#define MDP_RDMA_SRC_BASE_2 0xf1046#define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y 0xf2047#define MDP_RDMA_UFO_DEC_LENGTH_BASE_C 0xf2848 49/* MASK */50#define MDP_RDMA_EN_MASK 0x0000000151#define MDP_RDMA_RESET_MASK 0x0000000152#define MDP_RDMA_CON_MASK 0x0000111053#define MDP_RDMA_GMCIF_CON_MASK 0xfffb377154#define MDP_RDMA_SRC_CON_MASK 0xf3ffffff55#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff56#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK 0x001fffff57#define MDP_RDMA_MF_SRC_SIZE_MASK 0x1fff1fff58#define MDP_RDMA_MF_CLIP_SIZE_MASK 0x1fff1fff59#define MDP_RDMA_MF_OFFSET_1_MASK 0x003f001f60#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff61#define MDP_RDMA_SRC_END_0_MASK 0xffffffff62#define MDP_RDMA_SRC_END_1_MASK 0xffffffff63#define MDP_RDMA_SRC_END_2_MASK 0xffffffff64#define MDP_RDMA_SRC_OFFSET_0_MASK 0xffffffff65#define MDP_RDMA_SRC_OFFSET_1_MASK 0xffffffff66#define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff67#define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff68#define MDP_RDMA_TRANSFORM_0_MASK 0xff11077769#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff70#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff71#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff72#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f73#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff74#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff75#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f76#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff77#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff78#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f79#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff80#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff81#define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff82#define MDP_RDMA_MON_STA_1_MASK 0xffffffff83#define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff84#define MDP_RDMA_SRC_BASE_1_MASK 0xffffffff85#define MDP_RDMA_SRC_BASE_2_MASK 0xffffffff86#define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y_MASK 0xffffffff87#define MDP_RDMA_UFO_DEC_LENGTH_BASE_C_MASK 0xffffffff88 89#endif // __MDP_REG_RDMA_H__90