35 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>5 */6 7#ifndef __MDP_REG_TDSHP_H__8#define __MDP_REG_TDSHP_H__9 10#define MDP_HIST_CFG_00 (0x064)11#define MDP_HIST_CFG_01 (0x068)12#define MDP_TDSHP_CTRL (0x100)13#define MDP_TDSHP_CFG (0x110)14#define MDP_TDSHP_INPUT_SIZE (0x120)15#define MDP_TDSHP_OUTPUT_OFFSET (0x124)16#define MDP_TDSHP_OUTPUT_SIZE (0x128)17#define MDP_LUMA_HIST_INIT (0x200)18#define MDP_DC_TWO_D_W1_RESULT_INIT (0x260)19#define MDP_CONTOUR_HIST_INIT (0x398)20 21/* MASK */22#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF)23#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF)24#define MDP_LUMA_HIST_MASK (0xFFFFFFFF)25#define MDP_TDSHP_CTRL_MASK (0x07)26#define MDP_TDSHP_CFG_MASK (0x03F7)27#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF)28#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF)29#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF)30#define MDP_LUMA_HIST_INIT_MASK (0xFFFFFFFF)31#define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF)32#define MDP_CONTOUR_HIST_INIT_MASK (0xFFFFFFFF)33 34#endif // __MDP_REG_TDSHP_H__35