48 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>5 */6 7#ifndef __MDP_REG_WDMA_H__8#define __MDP_REG_WDMA_H__9 10#define WDMA_EN 0x00811#define WDMA_RST 0x00c12#define WDMA_CFG 0x01413#define WDMA_SRC_SIZE 0x01814#define WDMA_CLIP_SIZE 0x01c15#define WDMA_CLIP_COORD 0x02016#define WDMA_DST_W_IN_BYTE 0x02817#define WDMA_ALPHA 0x02c18#define WDMA_BUF_CON2 0x03c19#define WDMA_DST_UV_PITCH 0x07820#define WDMA_DST_ADDR_OFFSET 0x08021#define WDMA_DST_U_ADDR_OFFSET 0x08422#define WDMA_DST_V_ADDR_OFFSET 0x08823#define WDMA_FLOW_CTRL_DBG 0x0a024#define WDMA_DST_ADDR 0xf0025#define WDMA_DST_U_ADDR 0xf0426#define WDMA_DST_V_ADDR 0xf0827 28/* MASK */29#define WDMA_EN_MASK 0x0000000130#define WDMA_RST_MASK 0x0000000131#define WDMA_CFG_MASK 0xff03bff032#define WDMA_SRC_SIZE_MASK 0x3fff3fff33#define WDMA_CLIP_SIZE_MASK 0x3fff3fff34#define WDMA_CLIP_COORD_MASK 0x3fff3fff35#define WDMA_DST_W_IN_BYTE_MASK 0x0000ffff36#define WDMA_ALPHA_MASK 0x800000ff37#define WDMA_BUF_CON2_MASK 0xffffffff38#define WDMA_DST_UV_PITCH_MASK 0x0000ffff39#define WDMA_DST_ADDR_OFFSET_MASK 0x0fffffff40#define WDMA_DST_U_ADDR_OFFSET_MASK 0x0fffffff41#define WDMA_DST_V_ADDR_OFFSET_MASK 0x0fffffff42#define WDMA_FLOW_CTRL_DBG_MASK 0x0000f3ff43#define WDMA_DST_ADDR_MASK 0xffffffff44#define WDMA_DST_U_ADDR_MASK 0xffffffff45#define WDMA_DST_V_ADDR_MASK 0xffffffff46 47#endif // __MDP_REG_WDMA_H__48