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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>5 */6 7#ifndef __MTK_MDP3_CORE_H__8#define __MTK_MDP3_CORE_H__9 10#include <media/v4l2-device.h>11#include <media/v4l2-mem2mem.h>12#include <linux/soc/mediatek/mtk-mmsys.h>13#include <linux/soc/mediatek/mtk-mutex.h>14#include "mtk-mdp3-comp.h"15#include "mtk-mdp3-vpu.h"16 17#define MDP_MODULE_NAME "mtk-mdp3"18#define MDP_DEVICE_NAME "MediaTek MDP3"19#define MDP_PHANDLE_NAME "mediatek,mdp3"20 21enum mdp_infra_id {22 /*23 * Due to the sequential nature of function "mdp_mm_subsys_deploy",24 * adding new enum. necessitates careful consideration.25 */26 MDP_INFRA_MMSYS,27 MDP_INFRA_MMSYS2,28 MDP_INFRA_MUTEX,29 MDP_INFRA_MUTEX2,30 MDP_INFRA_SCP,31 MDP_INFRA_MAX32};33 34enum mdp_mm_subsys_id {35 MDP_MM_SUBSYS_0,36 MDP_MM_SUBSYS_1,37 MDP_MM_SUBSYS_MAX,38};39 40enum mdp_buffer_usage {41 MDP_BUFFER_USAGE_HW_READ,42 MDP_BUFFER_USAGE_MDP,43 MDP_BUFFER_USAGE_MDP2,44 MDP_BUFFER_USAGE_ISP,45 MDP_BUFFER_USAGE_WPE,46};47 48struct mdp_platform_config {49 bool rdma_support_10bit;50 bool rdma_rsz1_sram_sharing;51 bool rdma_upsample_repeat_only;52 bool rdma_esl_setting;53 u32 rdma_event_num;54 bool rsz_disable_dcm_small_sample;55 bool rsz_etc_control;56 bool wrot_filter_constraint;57 bool wrot_support_10bit;58 u32 wrot_event_num;59 u32 tdshp_hist_num;60 bool tdshp_constrain;61 bool tdshp_contour;62};63 64/* indicate which mutex is used by each pipepline */65enum mdp_pipe_id {66 MDP_PIPE_WPEI,67 MDP_PIPE_WPEI2,68 MDP_PIPE_IMGI,69 MDP_PIPE_RDMA0,70 MDP_PIPE_RDMA1,71 MDP_PIPE_RDMA2,72 MDP_PIPE_RDMA3,73 MDP_PIPE_SPLIT,74 MDP_PIPE_SPLIT2,75 MDP_PIPE_VPP0_SOUT,76 MDP_PIPE_VPP1_SOUT,77 MDP_PIPE_MAX78};79 80/* MDP parallel pipe control */81enum {82 MDP_PP_USED_1 = 1,83 MDP_PP_USED_2 = 2,84};85 86#define MDP_PP_MAX MDP_PP_USED_287 88struct mtk_mdp_driver_data {89 const int mdp_plat_id;90 const resource_size_t mdp_con_res;91 const struct of_device_id *mdp_probe_infra;92 const struct mdp_platform_config *mdp_cfg;93 const u32 *mdp_mutex_table_idx;94 const struct mdp_comp_data *comp_data;95 unsigned int comp_data_len;96 const struct of_device_id *mdp_sub_comp_dt_ids;97 const struct mdp_format *format;98 unsigned int format_len;99 const struct mdp_limit *def_limit;100 const struct mdp_pipe_info *pipe_info;101 unsigned int pipe_info_len;102 const struct v4l2_rect *pp_criteria;103 const u8 pp_used;104};105 106struct mdp_mm_subsys {107 struct device *mmsys;108 struct device *mutex;109 struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX];110};111 112struct mdp_dev {113 struct platform_device *pdev;114 struct mdp_mm_subsys mm_subsys[MDP_MM_SUBSYS_MAX];115 struct mdp_comp *comp[MDP_MAX_COMP_COUNT];116 const struct mtk_mdp_driver_data *mdp_data;117 118 struct workqueue_struct *job_wq;119 struct workqueue_struct *clock_wq;120 struct mdp_vpu_dev vpu;121 struct mtk_scp *scp;122 struct rproc *rproc_handle;123 /* synchronization protect for accessing vpu working buffer info */124 struct mutex vpu_lock;125 s32 vpu_count;126 u32 id_count;127 struct ida mdp_ida;128 struct cmdq_client *cmdq_clt[MDP_PP_MAX];129 wait_queue_head_t callback_wq;130 131 struct v4l2_device v4l2_dev;132 struct video_device *m2m_vdev;133 struct v4l2_m2m_dev *m2m_dev;134 /* synchronization protect for m2m device operation */135 struct mutex m2m_lock;136 atomic_t suspended;137 refcount_t job_count;138};139 140struct mdp_pipe_info {141 enum mdp_pipe_id pipe_id;142 enum mdp_mm_subsys_id sub_id;143 u32 mutex_id;144};145 146int mdp_vpu_get_locked(struct mdp_dev *mdp);147void mdp_vpu_put_locked(struct mdp_dev *mdp);148int mdp_vpu_register(struct mdp_dev *mdp);149void mdp_vpu_unregister(struct mdp_dev *mdp);150void mdp_video_device_release(struct video_device *vdev);151 152#endif /* __MTK_MDP3_CORE_H__ */153