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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * i.MX8QXP/i.MX8QM JPEG encoder/decoder v4l2 driver4 *5 * Copyright 2018-2019 NXP6 */7 8#ifndef _MXC_JPEG_HW_H9#define _MXC_JPEG_HW_H10 11/* JPEG Decoder/Encoder Wrapper Register Map */12#define GLB_CTRL 0x013#define COM_STATUS 0x414#define BUF_BASE0 0x1415#define BUF_BASE1 0x1816#define LINE_PITCH 0x1C17#define STM_BUFBASE 0x2018#define STM_BUFSIZE 0x2419#define IMGSIZE 0x2820#define STM_CTRL 0x2C21 22/* CAST JPEG-Decoder/Encoder Status Register Map (read-only)*/23#define CAST_STATUS0 0x10024#define CAST_STATUS1 0x10425#define CAST_STATUS2 0x10826#define CAST_STATUS3 0x10c27#define CAST_STATUS4 0x11028#define CAST_STATUS5 0x11429#define CAST_STATUS6 0x11830#define CAST_STATUS7 0x11c31#define CAST_STATUS8 0x12032#define CAST_STATUS9 0x12433#define CAST_STATUS10 0x12834#define CAST_STATUS11 0x12c35#define CAST_STATUS12 0x13036#define CAST_STATUS13 0x13437/* the following are for encoder only */38#define CAST_STATUS14 0x13839#define CAST_STATUS15 0x13c40#define CAST_STATUS16 0x14041#define CAST_STATUS17 0x14442#define CAST_STATUS18 0x14843#define CAST_STATUS19 0x14c44 45/* CAST JPEG-Decoder Control Register Map (write-only) */46#define CAST_CTRL CAST_STATUS1347 48/* CAST JPEG-Encoder Control Register Map (write-only) */49#define CAST_MODE CAST_STATUS050#define CAST_CFG_MODE CAST_STATUS151#define CAST_QUALITY CAST_STATUS252#define CAST_RSVD CAST_STATUS353#define CAST_REC_REGS_SEL CAST_STATUS454#define CAST_LUMTH CAST_STATUS555#define CAST_CHRTH CAST_STATUS656#define CAST_NOMFRSIZE_LO CAST_STATUS1657#define CAST_NOMFRSIZE_HI CAST_STATUS1758#define CAST_OFBSIZE_LO CAST_STATUS1859#define CAST_OFBSIZE_HI CAST_STATUS1960 61/* JPEG-Decoder Wrapper Slot Registers 0..3 */62#define SLOT_BASE 0x1000063#define SLOT_STATUS 0x064#define SLOT_IRQ_EN 0x465#define SLOT_BUF_PTR 0x866#define SLOT_CUR_DESCPT_PTR 0xC67#define SLOT_NXT_DESCPT_PTR 0x1068#define MXC_SLOT_OFFSET(slot, offset) ((SLOT_BASE * ((slot) + 1)) + (offset))69 70/* GLB_CTRL fields */71#define GLB_CTRL_JPG_EN 0x172#define GLB_CTRL_SFT_RST (0x1 << 1)73#define GLB_CTRL_DEC_GO (0x1 << 2)74#define GLB_CTRL_L_ENDIAN(le) ((le) << 3)75#define GLB_CTRL_SLOT_EN(slot) (0x1 << ((slot) + 4))76 77/* COM_STAUS fields */78#define COM_STATUS_DEC_ONGOING(r) (((r) & (1 << 31)) >> 31)79#define COM_STATUS_CUR_SLOT(r) (((r) & (0x3 << 29)) >> 29)80 81/* STM_CTRL fields */82#define STM_CTRL_PIXEL_PRECISION (0x1 << 2)83#define STM_CTRL_IMAGE_FORMAT(img_fmt) ((img_fmt) << 3)84#define STM_CTRL_IMAGE_FORMAT_MASK (0xF << 3)85#define STM_CTRL_BITBUF_PTR_CLR(clr) ((clr) << 7)86#define STM_CTRL_AUTO_START(go) ((go) << 8)87#define STM_CTRL_CONFIG_MOD(mod) ((mod) << 9)88 89/* SLOT_STATUS fields for slots 0..3 */90#define SLOT_STATUS_FRMDONE (0x1 << 3)91#define SLOT_STATUS_ENC_CONFIG_ERR (0x1 << 8)92 93/* SLOT_IRQ_EN fields TBD */94 95#define MXC_NXT_DESCPT_EN 0x196#define MXC_DEC_EXIT_IDLE_MODE 0x497 98/* JPEG-Decoder Wrapper - STM_CTRL Register Fields */99#define MXC_PIXEL_PRECISION(precision) ((precision) / 8 << 2)100enum mxc_jpeg_image_format {101 MXC_JPEG_INVALID = -1,102 MXC_JPEG_YUV420 = 0x0, /* 2 Plannar, Y=1st plane UV=2nd plane */103 MXC_JPEG_YUV422 = 0x1, /* 1 Plannar, YUYV sequence */104 MXC_JPEG_BGR = 0x2, /* BGR packed format */105 MXC_JPEG_YUV444 = 0x3, /* 1 Plannar, YUVYUV sequence */106 MXC_JPEG_GRAY = 0x4, /* Y8 or Y12 or Single Component */107 MXC_JPEG_RESERVED = 0x5,108 MXC_JPEG_ABGR = 0x6,109};110 111#include "mxc-jpeg.h"112void print_descriptor_info(struct device *dev, struct mxc_jpeg_desc *desc);113void print_cast_status(struct device *dev, void __iomem *reg,114 unsigned int mode);115void print_wrapper_info(struct device *dev, void __iomem *reg);116void mxc_jpeg_sw_reset(void __iomem *reg);117int mxc_jpeg_enable(void __iomem *reg);118void mxc_jpeg_enc_mode_conf(struct device *dev, void __iomem *reg, u8 extseq);119void mxc_jpeg_enc_mode_go(struct device *dev, void __iomem *reg, u8 extseq);120void mxc_jpeg_enc_set_quality(struct device *dev, void __iomem *reg, u8 quality);121void mxc_jpeg_dec_mode_go(struct device *dev, void __iomem *reg);122void mxc_jpeg_enable_slot(void __iomem *reg, int slot);123void mxc_jpeg_set_l_endian(void __iomem *reg, int le);124void mxc_jpeg_enable_irq(void __iomem *reg, int slot);125void mxc_jpeg_disable_irq(void __iomem *reg, int slot);126void mxc_jpeg_set_bufsize(struct mxc_jpeg_desc *desc, u32 bufsize);127void mxc_jpeg_set_res(struct mxc_jpeg_desc *desc, u16 w, u16 h);128void mxc_jpeg_set_line_pitch(struct mxc_jpeg_desc *desc, u32 line_pitch);129void mxc_jpeg_set_desc(u32 desc, void __iomem *reg, int slot);130void mxc_jpeg_clr_desc(void __iomem *reg, int slot);131#endif132