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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Freescale PXP Register Definitions4 *5 * based on pxp_dma_v3.h, Xml Revision: 1.77, Template Revision: 1.36 *7 * Copyright 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.8 */9 10#ifndef __IMX_PXP_H__11#define __IMX_PXP_H__12 13#define HW_PXP_CTRL (0x00000000)14#define HW_PXP_CTRL_SET (0x00000004)15#define HW_PXP_CTRL_CLR (0x00000008)16#define HW_PXP_CTRL_TOG (0x0000000c)17 18#define BM_PXP_CTRL_SFTRST 0x8000000019#define BF_PXP_CTRL_SFTRST(v) \20 (((v) << 31) & BM_PXP_CTRL_SFTRST)21#define BM_PXP_CTRL_CLKGATE 0x4000000022#define BF_PXP_CTRL_CLKGATE(v) \23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)24#define BM_PXP_CTRL_RSVD4 0x2000000025#define BF_PXP_CTRL_RSVD4(v) \26 (((v) << 29) & BM_PXP_CTRL_RSVD4)27#define BM_PXP_CTRL_EN_REPEAT 0x1000000028#define BF_PXP_CTRL_EN_REPEAT(v) \29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)30#define BM_PXP_CTRL_ENABLE_ROTATE1 0x0800000031#define BF_PXP_CTRL_ENABLE_ROTATE1(v) \32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)33#define BM_PXP_CTRL_ENABLE_ROTATE0 0x0400000034#define BF_PXP_CTRL_ENABLE_ROTATE0(v) \35 (((v) << 26) & BM_PXP_CTRL_ENABLE_ROTATE0)36#define BM_PXP_CTRL_ENABLE_LUT 0x0200000037#define BF_PXP_CTRL_ENABLE_LUT(v) \38 (((v) << 25) & BM_PXP_CTRL_ENABLE_LUT)39#define BM_PXP_CTRL_ENABLE_CSC2 0x0100000040#define BF_PXP_CTRL_ENABLE_CSC2(v) \41 (((v) << 24) & BM_PXP_CTRL_ENABLE_CSC2)42#define BM_PXP_CTRL_BLOCK_SIZE 0x0080000043#define BF_PXP_CTRL_BLOCK_SIZE(v) \44 (((v) << 23) & BM_PXP_CTRL_BLOCK_SIZE)45#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x046#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x147#define BM_PXP_CTRL_RSVD1 0x0040000048#define BF_PXP_CTRL_RSVD1(v) \49 (((v) << 22) & BM_PXP_CTRL_RSVD1)50#define BM_PXP_CTRL_ENABLE_ALPHA_B 0x0020000051#define BF_PXP_CTRL_ENABLE_ALPHA_B(v) \52 (((v) << 21) & BM_PXP_CTRL_ENABLE_ALPHA_B)53#define BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE 0x0010000054#define BF_PXP_CTRL_ENABLE_INPUT_FETCH_STORE(v) \55 (((v) << 20) & BM_PXP_CTRL_ENABLE_INPUT_FETCH_STORE)56#define BM_PXP_CTRL_ENABLE_WFE_B 0x0008000057#define BF_PXP_CTRL_ENABLE_WFE_B(v) \58 (((v) << 19) & BM_PXP_CTRL_ENABLE_WFE_B)59#define BM_PXP_CTRL_ENABLE_WFE_A 0x0004000060#define BF_PXP_CTRL_ENABLE_WFE_A(v) \61 (((v) << 18) & BM_PXP_CTRL_ENABLE_WFE_A)62#define BM_PXP_CTRL_ENABLE_DITHER 0x0002000063#define BF_PXP_CTRL_ENABLE_DITHER(v) \64 (((v) << 17) & BM_PXP_CTRL_ENABLE_DITHER)65#define BM_PXP_CTRL_ENABLE_PS_AS_OUT 0x0001000066#define BF_PXP_CTRL_ENABLE_PS_AS_OUT(v) \67 (((v) << 16) & BM_PXP_CTRL_ENABLE_PS_AS_OUT)68#define BM_PXP_CTRL_VFLIP1 0x0000800069#define BF_PXP_CTRL_VFLIP1(v) \70 (((v) << 15) & BM_PXP_CTRL_VFLIP1)71#define BM_PXP_CTRL_HFLIP1 0x0000400072#define BF_PXP_CTRL_HFLIP1(v) \73 (((v) << 14) & BM_PXP_CTRL_HFLIP1)74#define BP_PXP_CTRL_ROTATE1 1275#define BM_PXP_CTRL_ROTATE1 0x0000300076#define BF_PXP_CTRL_ROTATE1(v) \77 (((v) << 12) & BM_PXP_CTRL_ROTATE1)78#define BV_PXP_CTRL_ROTATE1__ROT_0 0x079#define BV_PXP_CTRL_ROTATE1__ROT_90 0x180#define BV_PXP_CTRL_ROTATE1__ROT_180 0x281#define BV_PXP_CTRL_ROTATE1__ROT_270 0x382#define BM_PXP_CTRL_VFLIP0 0x0000080083#define BF_PXP_CTRL_VFLIP0(v) \84 (((v) << 11) & BM_PXP_CTRL_VFLIP0)85#define BM_PXP_CTRL_HFLIP0 0x0000040086#define BF_PXP_CTRL_HFLIP0(v) \87 (((v) << 10) & BM_PXP_CTRL_HFLIP0)88#define BP_PXP_CTRL_ROTATE0 889#define BM_PXP_CTRL_ROTATE0 0x0000030090#define BF_PXP_CTRL_ROTATE0(v) \91 (((v) << 8) & BM_PXP_CTRL_ROTATE0)92#define BV_PXP_CTRL_ROTATE0__ROT_0 0x093#define BV_PXP_CTRL_ROTATE0__ROT_90 0x194#define BV_PXP_CTRL_ROTATE0__ROT_180 0x295#define BV_PXP_CTRL_ROTATE0__ROT_270 0x396#define BP_PXP_CTRL_RSVD0 697#define BM_PXP_CTRL_RSVD0 0x000000C098#define BF_PXP_CTRL_RSVD0(v) \99 (((v) << 6) & BM_PXP_CTRL_RSVD0)100#define BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP 0x00000020101#define BF_PXP_CTRL_HANDSHAKE_ABORT_SKIP(v) \102 (((v) << 5) & BM_PXP_CTRL_HANDSHAKE_ABORT_SKIP)103#define BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE 0x00000010104#define BF_PXP_CTRL_ENABLE_LCD0_HANDSHAKE(v) \105 (((v) << 4) & BM_PXP_CTRL_ENABLE_LCD0_HANDSHAKE)106#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008107#define BF_PXP_CTRL_LUT_DMA_IRQ_ENABLE(v) \108 (((v) << 3) & BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE)109#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004110#define BF_PXP_CTRL_NEXT_IRQ_ENABLE(v) \111 (((v) << 2) & BM_PXP_CTRL_NEXT_IRQ_ENABLE)112#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002113#define BF_PXP_CTRL_IRQ_ENABLE(v) \114 (((v) << 1) & BM_PXP_CTRL_IRQ_ENABLE)115#define BM_PXP_CTRL_ENABLE 0x00000001116#define BF_PXP_CTRL_ENABLE(v) \117 (((v) << 0) & BM_PXP_CTRL_ENABLE)118 119#define HW_PXP_STAT (0x00000010)120#define HW_PXP_STAT_SET (0x00000014)121#define HW_PXP_STAT_CLR (0x00000018)122#define HW_PXP_STAT_TOG (0x0000001c)123 124#define BP_PXP_STAT_BLOCKX 24125#define BM_PXP_STAT_BLOCKX 0xFF000000126#define BF_PXP_STAT_BLOCKX(v) \127 (((v) << 24) & BM_PXP_STAT_BLOCKX)128#define BP_PXP_STAT_BLOCKY 16129#define BM_PXP_STAT_BLOCKY 0x00FF0000130#define BF_PXP_STAT_BLOCKY(v) \131 (((v) << 16) & BM_PXP_STAT_BLOCKY)132#define BP_PXP_STAT_AXI_ERROR_ID_1 12133#define BM_PXP_STAT_AXI_ERROR_ID_1 0x0000F000134#define BF_PXP_STAT_AXI_ERROR_ID_1(v) \135 (((v) << 12) & BM_PXP_STAT_AXI_ERROR_ID_1)136#define BM_PXP_STAT_RSVD2 0x00000800137#define BF_PXP_STAT_RSVD2(v) \138 (((v) << 11) & BM_PXP_STAT_RSVD2)139#define BM_PXP_STAT_AXI_READ_ERROR_1 0x00000400140#define BF_PXP_STAT_AXI_READ_ERROR_1(v) \141 (((v) << 10) & BM_PXP_STAT_AXI_READ_ERROR_1)142#define BM_PXP_STAT_AXI_WRITE_ERROR_1 0x00000200143#define BF_PXP_STAT_AXI_WRITE_ERROR_1(v) \144 (((v) << 9) & BM_PXP_STAT_AXI_WRITE_ERROR_1)145#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100146#define BF_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(v) \147 (((v) << 8) & BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ)148#define BP_PXP_STAT_AXI_ERROR_ID_0 4149#define BM_PXP_STAT_AXI_ERROR_ID_0 0x000000F0150#define BF_PXP_STAT_AXI_ERROR_ID_0(v) \151 (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID_0)152#define BM_PXP_STAT_NEXT_IRQ 0x00000008153#define BF_PXP_STAT_NEXT_IRQ(v) \154 (((v) << 3) & BM_PXP_STAT_NEXT_IRQ)155#define BM_PXP_STAT_AXI_READ_ERROR_0 0x00000004156#define BF_PXP_STAT_AXI_READ_ERROR_0(v) \157 (((v) << 2) & BM_PXP_STAT_AXI_READ_ERROR_0)158#define BM_PXP_STAT_AXI_WRITE_ERROR_0 0x00000002159#define BF_PXP_STAT_AXI_WRITE_ERROR_0(v) \160 (((v) << 1) & BM_PXP_STAT_AXI_WRITE_ERROR_0)161#define BM_PXP_STAT_IRQ0 0x00000001162#define BF_PXP_STAT_IRQ0(v) \163 (((v) << 0) & BM_PXP_STAT_IRQ0)164 165#define HW_PXP_OUT_CTRL (0x00000020)166#define HW_PXP_OUT_CTRL_SET (0x00000024)167#define HW_PXP_OUT_CTRL_CLR (0x00000028)168#define HW_PXP_OUT_CTRL_TOG (0x0000002c)169 170#define BP_PXP_OUT_CTRL_ALPHA 24171#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000172#define BF_PXP_OUT_CTRL_ALPHA(v) \173 (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA)174#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000175#define BF_PXP_OUT_CTRL_ALPHA_OUTPUT(v) \176 (((v) << 23) & BM_PXP_OUT_CTRL_ALPHA_OUTPUT)177#define BP_PXP_OUT_CTRL_RSVD1 10178#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00179#define BF_PXP_OUT_CTRL_RSVD1(v) \180 (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1)181#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8182#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300183#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \184 (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT)185#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0186#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1187#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2188#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3189#define BP_PXP_OUT_CTRL_RSVD0 5190#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0191#define BF_PXP_OUT_CTRL_RSVD0(v) \192 (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0)193#define BP_PXP_OUT_CTRL_FORMAT 0194#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F195#define BF_PXP_OUT_CTRL_FORMAT(v) \196 (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)197#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0198#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4199#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5200#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8201#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9202#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC203#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD204#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE205#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10206#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12207#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13208#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14209#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15210#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18211#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19212#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A213#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B214 215#define HW_PXP_OUT_BUF (0x00000030)216 217#define BP_PXP_OUT_BUF_ADDR 0218#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF219#define BF_PXP_OUT_BUF_ADDR(v) (v)220 221#define HW_PXP_OUT_BUF2 (0x00000040)222 223#define BP_PXP_OUT_BUF2_ADDR 0224#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF225#define BF_PXP_OUT_BUF2_ADDR(v) (v)226 227#define HW_PXP_OUT_PITCH (0x00000050)228 229#define BP_PXP_OUT_PITCH_RSVD 16230#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000231#define BF_PXP_OUT_PITCH_RSVD(v) \232 (((v) << 16) & BM_PXP_OUT_PITCH_RSVD)233#define BP_PXP_OUT_PITCH_PITCH 0234#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF235#define BF_PXP_OUT_PITCH_PITCH(v) \236 (((v) << 0) & BM_PXP_OUT_PITCH_PITCH)237 238#define HW_PXP_OUT_LRC (0x00000060)239 240#define BP_PXP_OUT_LRC_RSVD1 30241#define BM_PXP_OUT_LRC_RSVD1 0xC0000000242#define BF_PXP_OUT_LRC_RSVD1(v) \243 (((v) << 30) & BM_PXP_OUT_LRC_RSVD1)244#define BP_PXP_OUT_LRC_X 16245#define BM_PXP_OUT_LRC_X 0x3FFF0000246#define BF_PXP_OUT_LRC_X(v) \247 (((v) << 16) & BM_PXP_OUT_LRC_X)248#define BP_PXP_OUT_LRC_RSVD0 14249#define BM_PXP_OUT_LRC_RSVD0 0x0000C000250#define BF_PXP_OUT_LRC_RSVD0(v) \251 (((v) << 14) & BM_PXP_OUT_LRC_RSVD0)252#define BP_PXP_OUT_LRC_Y 0253#define BM_PXP_OUT_LRC_Y 0x00003FFF254#define BF_PXP_OUT_LRC_Y(v) \255 (((v) << 0) & BM_PXP_OUT_LRC_Y)256 257#define HW_PXP_OUT_PS_ULC (0x00000070)258 259#define BP_PXP_OUT_PS_ULC_RSVD1 30260#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000261#define BF_PXP_OUT_PS_ULC_RSVD1(v) \262 (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1)263#define BP_PXP_OUT_PS_ULC_X 16264#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000265#define BF_PXP_OUT_PS_ULC_X(v) \266 (((v) << 16) & BM_PXP_OUT_PS_ULC_X)267#define BP_PXP_OUT_PS_ULC_RSVD0 14268#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000269#define BF_PXP_OUT_PS_ULC_RSVD0(v) \270 (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0)271#define BP_PXP_OUT_PS_ULC_Y 0272#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF273#define BF_PXP_OUT_PS_ULC_Y(v) \274 (((v) << 0) & BM_PXP_OUT_PS_ULC_Y)275 276#define HW_PXP_OUT_PS_LRC (0x00000080)277 278#define BP_PXP_OUT_PS_LRC_RSVD1 30279#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000280#define BF_PXP_OUT_PS_LRC_RSVD1(v) \281 (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1)282#define BP_PXP_OUT_PS_LRC_X 16283#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000284#define BF_PXP_OUT_PS_LRC_X(v) \285 (((v) << 16) & BM_PXP_OUT_PS_LRC_X)286#define BP_PXP_OUT_PS_LRC_RSVD0 14287#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000288#define BF_PXP_OUT_PS_LRC_RSVD0(v) \289 (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0)290#define BP_PXP_OUT_PS_LRC_Y 0291#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF292#define BF_PXP_OUT_PS_LRC_Y(v) \293 (((v) << 0) & BM_PXP_OUT_PS_LRC_Y)294 295#define HW_PXP_OUT_AS_ULC (0x00000090)296 297#define BP_PXP_OUT_AS_ULC_RSVD1 30298#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000299#define BF_PXP_OUT_AS_ULC_RSVD1(v) \300 (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1)301#define BP_PXP_OUT_AS_ULC_X 16302#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000303#define BF_PXP_OUT_AS_ULC_X(v) \304 (((v) << 16) & BM_PXP_OUT_AS_ULC_X)305#define BP_PXP_OUT_AS_ULC_RSVD0 14306#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000307#define BF_PXP_OUT_AS_ULC_RSVD0(v) \308 (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0)309#define BP_PXP_OUT_AS_ULC_Y 0310#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF311#define BF_PXP_OUT_AS_ULC_Y(v) \312 (((v) << 0) & BM_PXP_OUT_AS_ULC_Y)313 314#define HW_PXP_OUT_AS_LRC (0x000000a0)315 316#define BP_PXP_OUT_AS_LRC_RSVD1 30317#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000318#define BF_PXP_OUT_AS_LRC_RSVD1(v) \319 (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1)320#define BP_PXP_OUT_AS_LRC_X 16321#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000322#define BF_PXP_OUT_AS_LRC_X(v) \323 (((v) << 16) & BM_PXP_OUT_AS_LRC_X)324#define BP_PXP_OUT_AS_LRC_RSVD0 14325#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000326#define BF_PXP_OUT_AS_LRC_RSVD0(v) \327 (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0)328#define BP_PXP_OUT_AS_LRC_Y 0329#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF330#define BF_PXP_OUT_AS_LRC_Y(v) \331 (((v) << 0) & BM_PXP_OUT_AS_LRC_Y)332 333#define HW_PXP_PS_CTRL (0x000000b0)334#define HW_PXP_PS_CTRL_SET (0x000000b4)335#define HW_PXP_PS_CTRL_CLR (0x000000b8)336#define HW_PXP_PS_CTRL_TOG (0x000000bc)337 338#define BP_PXP_PS_CTRL_RSVD1 12339#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000340#define BF_PXP_PS_CTRL_RSVD1(v) \341 (((v) << 12) & BM_PXP_PS_CTRL_RSVD1)342#define BP_PXP_PS_CTRL_DECX 10343#define BM_PXP_PS_CTRL_DECX 0x00000C00344#define BF_PXP_PS_CTRL_DECX(v) \345 (((v) << 10) & BM_PXP_PS_CTRL_DECX)346#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0347#define BV_PXP_PS_CTRL_DECX__DECX2 0x1348#define BV_PXP_PS_CTRL_DECX__DECX4 0x2349#define BV_PXP_PS_CTRL_DECX__DECX8 0x3350#define BP_PXP_PS_CTRL_DECY 8351#define BM_PXP_PS_CTRL_DECY 0x00000300352#define BF_PXP_PS_CTRL_DECY(v) \353 (((v) << 8) & BM_PXP_PS_CTRL_DECY)354#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0355#define BV_PXP_PS_CTRL_DECY__DECY2 0x1356#define BV_PXP_PS_CTRL_DECY__DECY4 0x2357#define BV_PXP_PS_CTRL_DECY__DECY8 0x3358#define BM_PXP_PS_CTRL_RSVD0 0x00000080359#define BF_PXP_PS_CTRL_RSVD0(v) \360 (((v) << 7) & BM_PXP_PS_CTRL_RSVD0)361#define BM_PXP_PS_CTRL_WB_SWAP 0x00000040362#define BF_PXP_PS_CTRL_WB_SWAP(v) \363 (((v) << 6) & BM_PXP_PS_CTRL_WB_SWAP)364#define BP_PXP_PS_CTRL_FORMAT 0365#define BM_PXP_PS_CTRL_FORMAT 0x0000003F366#define BF_PXP_PS_CTRL_FORMAT(v) \367 (((v) << 0) & BM_PXP_PS_CTRL_FORMAT)368#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4369#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC370#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD371#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE372#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10373#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12374#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13375#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14376#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15377#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18378#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19379#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A380#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B381#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E382#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F383 384#define HW_PXP_PS_BUF (0x000000c0)385 386#define BP_PXP_PS_BUF_ADDR 0387#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF388#define BF_PXP_PS_BUF_ADDR(v) (v)389 390#define HW_PXP_PS_UBUF (0x000000d0)391 392#define BP_PXP_PS_UBUF_ADDR 0393#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF394#define BF_PXP_PS_UBUF_ADDR(v) (v)395 396#define HW_PXP_PS_VBUF (0x000000e0)397 398#define BP_PXP_PS_VBUF_ADDR 0399#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF400#define BF_PXP_PS_VBUF_ADDR(v) (v)401 402#define HW_PXP_PS_PITCH (0x000000f0)403 404#define BP_PXP_PS_PITCH_RSVD 16405#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000406#define BF_PXP_PS_PITCH_RSVD(v) \407 (((v) << 16) & BM_PXP_PS_PITCH_RSVD)408#define BP_PXP_PS_PITCH_PITCH 0409#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF410#define BF_PXP_PS_PITCH_PITCH(v) \411 (((v) << 0) & BM_PXP_PS_PITCH_PITCH)412 413#define HW_PXP_PS_BACKGROUND_0 (0x00000100)414 415#define BP_PXP_PS_BACKGROUND_0_RSVD 24416#define BM_PXP_PS_BACKGROUND_0_RSVD 0xFF000000417#define BF_PXP_PS_BACKGROUND_0_RSVD(v) \418 (((v) << 24) & BM_PXP_PS_BACKGROUND_0_RSVD)419#define BP_PXP_PS_BACKGROUND_0_COLOR 0420#define BM_PXP_PS_BACKGROUND_0_COLOR 0x00FFFFFF421#define BF_PXP_PS_BACKGROUND_0_COLOR(v) \422 (((v) << 0) & BM_PXP_PS_BACKGROUND_0_COLOR)423 424#define HW_PXP_PS_SCALE (0x00000110)425 426#define BM_PXP_PS_SCALE_RSVD2 0x80000000427#define BF_PXP_PS_SCALE_RSVD2(v) \428 (((v) << 31) & BM_PXP_PS_SCALE_RSVD2)429#define BP_PXP_PS_SCALE_YSCALE 16430#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000431#define BF_PXP_PS_SCALE_YSCALE(v) \432 (((v) << 16) & BM_PXP_PS_SCALE_YSCALE)433#define BM_PXP_PS_SCALE_RSVD1 0x00008000434#define BF_PXP_PS_SCALE_RSVD1(v) \435 (((v) << 15) & BM_PXP_PS_SCALE_RSVD1)436#define BP_PXP_PS_SCALE_XSCALE 0437#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF438#define BF_PXP_PS_SCALE_XSCALE(v) \439 (((v) << 0) & BM_PXP_PS_SCALE_XSCALE)440 441#define HW_PXP_PS_OFFSET (0x00000120)442 443#define BP_PXP_PS_OFFSET_RSVD2 28444#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000445#define BF_PXP_PS_OFFSET_RSVD2(v) \446 (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2)447#define BP_PXP_PS_OFFSET_YOFFSET 16448#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000449#define BF_PXP_PS_OFFSET_YOFFSET(v) \450 (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET)451#define BP_PXP_PS_OFFSET_RSVD1 12452#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000453#define BF_PXP_PS_OFFSET_RSVD1(v) \454 (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1)455#define BP_PXP_PS_OFFSET_XOFFSET 0456#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF457#define BF_PXP_PS_OFFSET_XOFFSET(v) \458 (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)459 460#define HW_PXP_PS_CLRKEYLOW_0 (0x00000130)461 462#define BP_PXP_PS_CLRKEYLOW_0_RSVD1 24463#define BM_PXP_PS_CLRKEYLOW_0_RSVD1 0xFF000000464#define BF_PXP_PS_CLRKEYLOW_0_RSVD1(v) \465 (((v) << 24) & BM_PXP_PS_CLRKEYLOW_0_RSVD1)466#define BP_PXP_PS_CLRKEYLOW_0_PIXEL 0467#define BM_PXP_PS_CLRKEYLOW_0_PIXEL 0x00FFFFFF468#define BF_PXP_PS_CLRKEYLOW_0_PIXEL(v) \469 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_0_PIXEL)470 471#define HW_PXP_PS_CLRKEYHIGH_0 (0x00000140)472 473#define BP_PXP_PS_CLRKEYHIGH_0_RSVD1 24474#define BM_PXP_PS_CLRKEYHIGH_0_RSVD1 0xFF000000475#define BF_PXP_PS_CLRKEYHIGH_0_RSVD1(v) \476 (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_0_RSVD1)477#define BP_PXP_PS_CLRKEYHIGH_0_PIXEL 0478#define BM_PXP_PS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF479#define BF_PXP_PS_CLRKEYHIGH_0_PIXEL(v) \480 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_0_PIXEL)481 482#define HW_PXP_AS_CTRL (0x00000150)483 484#define BP_PXP_AS_CTRL_RSVD1 22485#define BM_PXP_AS_CTRL_RSVD1 0xFFC00000486#define BF_PXP_AS_CTRL_RSVD1(v) \487 (((v) << 22) & BM_PXP_AS_CTRL_RSVD1)488#define BM_PXP_AS_CTRL_ALPHA1_INVERT 0x00200000489#define BF_PXP_AS_CTRL_ALPHA1_INVERT(v) \490 (((v) << 21) & BM_PXP_AS_CTRL_ALPHA1_INVERT)491#define BM_PXP_AS_CTRL_ALPHA0_INVERT 0x00100000492#define BF_PXP_AS_CTRL_ALPHA0_INVERT(v) \493 (((v) << 20) & BM_PXP_AS_CTRL_ALPHA0_INVERT)494#define BP_PXP_AS_CTRL_ROP 16495#define BM_PXP_AS_CTRL_ROP 0x000F0000496#define BF_PXP_AS_CTRL_ROP(v) \497 (((v) << 16) & BM_PXP_AS_CTRL_ROP)498#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0499#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1500#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2501#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3502#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4503#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5504#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6505#define BV_PXP_AS_CTRL_ROP__NOT 0x7506#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8507#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9508#define BV_PXP_AS_CTRL_ROP__XORAS 0xA509#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB510#define BP_PXP_AS_CTRL_ALPHA 8511#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00512#define BF_PXP_AS_CTRL_ALPHA(v) \513 (((v) << 8) & BM_PXP_AS_CTRL_ALPHA)514#define BP_PXP_AS_CTRL_FORMAT 4515#define BM_PXP_AS_CTRL_FORMAT 0x000000F0516#define BF_PXP_AS_CTRL_FORMAT(v) \517 (((v) << 4) & BM_PXP_AS_CTRL_FORMAT)518#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0519#define BV_PXP_AS_CTRL_FORMAT__RGBA8888 0x1520#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4521#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8522#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9523#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC524#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD525#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE526#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008527#define BF_PXP_AS_CTRL_ENABLE_COLORKEY(v) \528 (((v) << 3) & BM_PXP_AS_CTRL_ENABLE_COLORKEY)529#define BP_PXP_AS_CTRL_ALPHA_CTRL 1530#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006531#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \532 (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL)533#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0534#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1535#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2536#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3537#define BM_PXP_AS_CTRL_RSVD0 0x00000001538#define BF_PXP_AS_CTRL_RSVD0(v) \539 (((v) << 0) & BM_PXP_AS_CTRL_RSVD0)540 541#define HW_PXP_AS_BUF (0x00000160)542 543#define BP_PXP_AS_BUF_ADDR 0544#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF545#define BF_PXP_AS_BUF_ADDR(v) (v)546 547#define HW_PXP_AS_PITCH (0x00000170)548 549#define BP_PXP_AS_PITCH_RSVD 16550#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000551#define BF_PXP_AS_PITCH_RSVD(v) \552 (((v) << 16) & BM_PXP_AS_PITCH_RSVD)553#define BP_PXP_AS_PITCH_PITCH 0554#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF555#define BF_PXP_AS_PITCH_PITCH(v) \556 (((v) << 0) & BM_PXP_AS_PITCH_PITCH)557 558#define HW_PXP_AS_CLRKEYLOW_0 (0x00000180)559 560#define BP_PXP_AS_CLRKEYLOW_0_RSVD1 24561#define BM_PXP_AS_CLRKEYLOW_0_RSVD1 0xFF000000562#define BF_PXP_AS_CLRKEYLOW_0_RSVD1(v) \563 (((v) << 24) & BM_PXP_AS_CLRKEYLOW_0_RSVD1)564#define BP_PXP_AS_CLRKEYLOW_0_PIXEL 0565#define BM_PXP_AS_CLRKEYLOW_0_PIXEL 0x00FFFFFF566#define BF_PXP_AS_CLRKEYLOW_0_PIXEL(v) \567 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_0_PIXEL)568 569#define HW_PXP_AS_CLRKEYHIGH_0 (0x00000190)570 571#define BP_PXP_AS_CLRKEYHIGH_0_RSVD1 24572#define BM_PXP_AS_CLRKEYHIGH_0_RSVD1 0xFF000000573#define BF_PXP_AS_CLRKEYHIGH_0_RSVD1(v) \574 (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_0_RSVD1)575#define BP_PXP_AS_CLRKEYHIGH_0_PIXEL 0576#define BM_PXP_AS_CLRKEYHIGH_0_PIXEL 0x00FFFFFF577#define BF_PXP_AS_CLRKEYHIGH_0_PIXEL(v) \578 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_0_PIXEL)579 580#define HW_PXP_CSC1_COEF0 (0x000001a0)581 582#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000583#define BF_PXP_CSC1_COEF0_YCBCR_MODE(v) \584 (((v) << 31) & BM_PXP_CSC1_COEF0_YCBCR_MODE)585#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000586#define BF_PXP_CSC1_COEF0_BYPASS(v) \587 (((v) << 30) & BM_PXP_CSC1_COEF0_BYPASS)588#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000589#define BF_PXP_CSC1_COEF0_RSVD1(v) \590 (((v) << 29) & BM_PXP_CSC1_COEF0_RSVD1)591#define BP_PXP_CSC1_COEF0_C0 18592#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000593#define BF_PXP_CSC1_COEF0_C0(v) \594 (((v) << 18) & BM_PXP_CSC1_COEF0_C0)595#define BP_PXP_CSC1_COEF0_UV_OFFSET 9596#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00597 598/*599 * We use v * (1 << 9) instead of v << 9, to workaround a gcc5 bug.600 * The compiler cannot understand that the expression is constant.601 */602#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \603 (((v) * (1 << 9)) & BM_PXP_CSC1_COEF0_UV_OFFSET)604#define BP_PXP_CSC1_COEF0_Y_OFFSET 0605#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF606#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \607 ((v) & BM_PXP_CSC1_COEF0_Y_OFFSET)608 609#define HW_PXP_CSC1_COEF1 (0x000001b0)610 611#define BP_PXP_CSC1_COEF1_RSVD1 27612#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000613#define BF_PXP_CSC1_COEF1_RSVD1(v) \614 (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1)615#define BP_PXP_CSC1_COEF1_C1 16616#define BM_PXP_CSC1_COEF1_C1 0x07FF0000617#define BF_PXP_CSC1_COEF1_C1(v) \618 (((v) << 16) & BM_PXP_CSC1_COEF1_C1)619#define BP_PXP_CSC1_COEF1_RSVD0 11620#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800621#define BF_PXP_CSC1_COEF1_RSVD0(v) \622 (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0)623#define BP_PXP_CSC1_COEF1_C4 0624#define BM_PXP_CSC1_COEF1_C4 0x000007FF625#define BF_PXP_CSC1_COEF1_C4(v) \626 (((v) << 0) & BM_PXP_CSC1_COEF1_C4)627 628#define HW_PXP_CSC1_COEF2 (0x000001c0)629 630#define BP_PXP_CSC1_COEF2_RSVD1 27631#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000632#define BF_PXP_CSC1_COEF2_RSVD1(v) \633 (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1)634#define BP_PXP_CSC1_COEF2_C2 16635#define BM_PXP_CSC1_COEF2_C2 0x07FF0000636#define BF_PXP_CSC1_COEF2_C2(v) \637 (((v) << 16) & BM_PXP_CSC1_COEF2_C2)638#define BP_PXP_CSC1_COEF2_RSVD0 11639#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800640#define BF_PXP_CSC1_COEF2_RSVD0(v) \641 (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0)642#define BP_PXP_CSC1_COEF2_C3 0643#define BM_PXP_CSC1_COEF2_C3 0x000007FF644#define BF_PXP_CSC1_COEF2_C3(v) \645 (((v) << 0) & BM_PXP_CSC1_COEF2_C3)646 647#define HW_PXP_CSC2_CTRL (0x000001d0)648 649#define BP_PXP_CSC2_CTRL_RSVD 3650#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8651#define BF_PXP_CSC2_CTRL_RSVD(v) \652 (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD)653#define BP_PXP_CSC2_CTRL_CSC_MODE 1654#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006655#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \656 (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE)657#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0658#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1659#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2660#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3661#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001662#define BF_PXP_CSC2_CTRL_BYPASS(v) \663 (((v) << 0) & BM_PXP_CSC2_CTRL_BYPASS)664 665#define HW_PXP_CSC2_COEF0 (0x000001e0)666 667#define BP_PXP_CSC2_COEF0_RSVD1 27668#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000669#define BF_PXP_CSC2_COEF0_RSVD1(v) \670 (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1)671#define BP_PXP_CSC2_COEF0_A2 16672#define BM_PXP_CSC2_COEF0_A2 0x07FF0000673#define BF_PXP_CSC2_COEF0_A2(v) \674 (((v) << 16) & BM_PXP_CSC2_COEF0_A2)675#define BP_PXP_CSC2_COEF0_RSVD0 11676#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800677#define BF_PXP_CSC2_COEF0_RSVD0(v) \678 (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0)679#define BP_PXP_CSC2_COEF0_A1 0680#define BM_PXP_CSC2_COEF0_A1 0x000007FF681#define BF_PXP_CSC2_COEF0_A1(v) \682 (((v) << 0) & BM_PXP_CSC2_COEF0_A1)683 684#define HW_PXP_CSC2_COEF1 (0x000001f0)685 686#define BP_PXP_CSC2_COEF1_RSVD1 27687#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000688#define BF_PXP_CSC2_COEF1_RSVD1(v) \689 (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1)690#define BP_PXP_CSC2_COEF1_B1 16691#define BM_PXP_CSC2_COEF1_B1 0x07FF0000692#define BF_PXP_CSC2_COEF1_B1(v) \693 (((v) << 16) & BM_PXP_CSC2_COEF1_B1)694#define BP_PXP_CSC2_COEF1_RSVD0 11695#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800696#define BF_PXP_CSC2_COEF1_RSVD0(v) \697 (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0)698#define BP_PXP_CSC2_COEF1_A3 0699#define BM_PXP_CSC2_COEF1_A3 0x000007FF700#define BF_PXP_CSC2_COEF1_A3(v) \701 (((v) << 0) & BM_PXP_CSC2_COEF1_A3)702 703#define HW_PXP_CSC2_COEF2 (0x00000200)704 705#define BP_PXP_CSC2_COEF2_RSVD1 27706#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000707#define BF_PXP_CSC2_COEF2_RSVD1(v) \708 (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1)709#define BP_PXP_CSC2_COEF2_B3 16710#define BM_PXP_CSC2_COEF2_B3 0x07FF0000711#define BF_PXP_CSC2_COEF2_B3(v) \712 (((v) << 16) & BM_PXP_CSC2_COEF2_B3)713#define BP_PXP_CSC2_COEF2_RSVD0 11714#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800715#define BF_PXP_CSC2_COEF2_RSVD0(v) \716 (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0)717#define BP_PXP_CSC2_COEF2_B2 0718#define BM_PXP_CSC2_COEF2_B2 0x000007FF719#define BF_PXP_CSC2_COEF2_B2(v) \720 (((v) << 0) & BM_PXP_CSC2_COEF2_B2)721 722#define HW_PXP_CSC2_COEF3 (0x00000210)723 724#define BP_PXP_CSC2_COEF3_RSVD1 27725#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000726#define BF_PXP_CSC2_COEF3_RSVD1(v) \727 (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1)728#define BP_PXP_CSC2_COEF3_C2 16729#define BM_PXP_CSC2_COEF3_C2 0x07FF0000730#define BF_PXP_CSC2_COEF3_C2(v) \731 (((v) << 16) & BM_PXP_CSC2_COEF3_C2)732#define BP_PXP_CSC2_COEF3_RSVD0 11733#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800734#define BF_PXP_CSC2_COEF3_RSVD0(v) \735 (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0)736#define BP_PXP_CSC2_COEF3_C1 0737#define BM_PXP_CSC2_COEF3_C1 0x000007FF738#define BF_PXP_CSC2_COEF3_C1(v) \739 (((v) << 0) & BM_PXP_CSC2_COEF3_C1)740 741#define HW_PXP_CSC2_COEF4 (0x00000220)742 743#define BP_PXP_CSC2_COEF4_RSVD1 25744#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000745#define BF_PXP_CSC2_COEF4_RSVD1(v) \746 (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1)747#define BP_PXP_CSC2_COEF4_D1 16748#define BM_PXP_CSC2_COEF4_D1 0x01FF0000749#define BF_PXP_CSC2_COEF4_D1(v) \750 (((v) << 16) & BM_PXP_CSC2_COEF4_D1)751#define BP_PXP_CSC2_COEF4_RSVD0 11752#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800753#define BF_PXP_CSC2_COEF4_RSVD0(v) \754 (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0)755#define BP_PXP_CSC2_COEF4_C3 0756#define BM_PXP_CSC2_COEF4_C3 0x000007FF757#define BF_PXP_CSC2_COEF4_C3(v) \758 (((v) << 0) & BM_PXP_CSC2_COEF4_C3)759 760#define HW_PXP_CSC2_COEF5 (0x00000230)761 762#define BP_PXP_CSC2_COEF5_RSVD1 25763#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000764#define BF_PXP_CSC2_COEF5_RSVD1(v) \765 (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1)766#define BP_PXP_CSC2_COEF5_D3 16767#define BM_PXP_CSC2_COEF5_D3 0x01FF0000768#define BF_PXP_CSC2_COEF5_D3(v) \769 (((v) << 16) & BM_PXP_CSC2_COEF5_D3)770#define BP_PXP_CSC2_COEF5_RSVD0 9771#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00772#define BF_PXP_CSC2_COEF5_RSVD0(v) \773 (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0)774#define BP_PXP_CSC2_COEF5_D2 0775#define BM_PXP_CSC2_COEF5_D2 0x000001FF776#define BF_PXP_CSC2_COEF5_D2(v) \777 (((v) << 0) & BM_PXP_CSC2_COEF5_D2)778 779#define HW_PXP_LUT_CTRL (0x00000240)780 781#define BM_PXP_LUT_CTRL_BYPASS 0x80000000782#define BF_PXP_LUT_CTRL_BYPASS(v) \783 (((v) << 31) & BM_PXP_LUT_CTRL_BYPASS)784#define BP_PXP_LUT_CTRL_RSVD3 26785#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000786#define BF_PXP_LUT_CTRL_RSVD3(v) \787 (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3)788#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24789#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000790#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \791 (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE)792#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0793#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1794#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2795#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3796#define BP_PXP_LUT_CTRL_RSVD2 18797#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000798#define BF_PXP_LUT_CTRL_RSVD2(v) \799 (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2)800#define BP_PXP_LUT_CTRL_OUT_MODE 16801#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000802#define BF_PXP_LUT_CTRL_OUT_MODE(v) \803 (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE)804#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0805#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1806#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2807#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3808#define BP_PXP_LUT_CTRL_RSVD1 11809#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800810#define BF_PXP_LUT_CTRL_RSVD1(v) \811 (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1)812#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400813#define BF_PXP_LUT_CTRL_SEL_8KB(v) \814 (((v) << 10) & BM_PXP_LUT_CTRL_SEL_8KB)815#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200816#define BF_PXP_LUT_CTRL_LRU_UPD(v) \817 (((v) << 9) & BM_PXP_LUT_CTRL_LRU_UPD)818#define BM_PXP_LUT_CTRL_INVALID 0x00000100819#define BF_PXP_LUT_CTRL_INVALID(v) \820 (((v) << 8) & BM_PXP_LUT_CTRL_INVALID)821#define BP_PXP_LUT_CTRL_RSVD0 1822#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE823#define BF_PXP_LUT_CTRL_RSVD0(v) \824 (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0)825#define BM_PXP_LUT_CTRL_DMA_START 0x00000001826#define BF_PXP_LUT_CTRL_DMA_START(v) \827 (((v) << 0) & BM_PXP_LUT_CTRL_DMA_START)828 829#define HW_PXP_LUT_ADDR (0x00000250)830 831#define BM_PXP_LUT_ADDR_RSVD2 0x80000000832#define BF_PXP_LUT_ADDR_RSVD2(v) \833 (((v) << 31) & BM_PXP_LUT_ADDR_RSVD2)834#define BP_PXP_LUT_ADDR_NUM_BYTES 16835#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000836#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \837 (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES)838#define BP_PXP_LUT_ADDR_RSVD1 14839#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000840#define BF_PXP_LUT_ADDR_RSVD1(v) \841 (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1)842#define BP_PXP_LUT_ADDR_ADDR 0843#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF844#define BF_PXP_LUT_ADDR_ADDR(v) \845 (((v) << 0) & BM_PXP_LUT_ADDR_ADDR)846 847#define HW_PXP_LUT_DATA (0x00000260)848 849#define BP_PXP_LUT_DATA_DATA 0850#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF851#define BF_PXP_LUT_DATA_DATA(v) (v)852 853#define HW_PXP_LUT_EXTMEM (0x00000270)854 855#define BP_PXP_LUT_EXTMEM_ADDR 0856#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF857#define BF_PXP_LUT_EXTMEM_ADDR(v) (v)858 859#define HW_PXP_CFA (0x00000280)860 861#define BP_PXP_CFA_DATA 0862#define BM_PXP_CFA_DATA 0xFFFFFFFF863#define BF_PXP_CFA_DATA(v) (v)864 865#define HW_PXP_ALPHA_A_CTRL (0x00000290)866 867#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 24868#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA 0xFF000000869#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(v) \870 (((v) << 24) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA)871#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 16872#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA 0x00FF0000873#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(v) \874 (((v) << 16) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA)875#define BP_PXP_ALPHA_A_CTRL_RSVD0 14876#define BM_PXP_ALPHA_A_CTRL_RSVD0 0x0000C000877#define BF_PXP_ALPHA_A_CTRL_RSVD0(v) \878 (((v) << 14) & BM_PXP_ALPHA_A_CTRL_RSVD0)879#define BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE 0x00002000880#define BF_PXP_ALPHA_A_CTRL_S1_COLOR_MODE(v) \881 (((v) << 13) & BM_PXP_ALPHA_A_CTRL_S1_COLOR_MODE)882#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__0 0x0883#define BV_PXP_ALPHA_A_CTRL_S1_COLOR_MODE__1 0x1884#define BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE 0x00001000885#define BF_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(v) \886 (((v) << 12) & BM_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE)887#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__0 0x0888#define BV_PXP_ALPHA_A_CTRL_S1_ALPHA_MODE__1 0x1889#define BP_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 10890#define BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00891#define BF_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(v) \892 (((v) << 10) & BM_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE)893#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0894#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x0895#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x0896#define BV_PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x0897#define BP_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 8898#define BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE 0x00000300899#define BF_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(v) \900 (((v) << 8) & BM_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE)901#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__0 0x0902#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__1 0x1903#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__2 0x2904#define BV_PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE__3 0x3905#define BM_PXP_ALPHA_A_CTRL_RSVD1 0x00000080906#define BF_PXP_ALPHA_A_CTRL_RSVD1(v) \907 (((v) << 7) & BM_PXP_ALPHA_A_CTRL_RSVD1)908#define BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE 0x00000040909#define BF_PXP_ALPHA_A_CTRL_S0_COLOR_MODE(v) \910 (((v) << 6) & BM_PXP_ALPHA_A_CTRL_S0_COLOR_MODE)911#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__0 0x0912#define BV_PXP_ALPHA_A_CTRL_S0_COLOR_MODE__1 0x1913#define BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE 0x00000020914#define BF_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(v) \915 (((v) << 5) & BM_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE)916#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__0 0x0917#define BV_PXP_ALPHA_A_CTRL_S0_ALPHA_MODE__1 0x1918#define BP_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 3919#define BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018920#define BF_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(v) \921 (((v) << 3) & BM_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE)922#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0923#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1924#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x2925#define BV_PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x3926#define BP_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 1927#define BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE 0x00000006928#define BF_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(v) \929 (((v) << 1) & BM_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE)930#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__0 0x0931#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__1 0x1932#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__2 0x2933#define BV_PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE__3 0x3934#define BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE 0x00000001935#define BF_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(v) \936 (((v) << 0) & BM_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE)937#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__0 0x0938#define BV_PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE__1 0x1939 940#define HW_PXP_ALPHA_B_CTRL (0x000002a0)941 942#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 24943#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA 0xFF000000944#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA(v) \945 (((v) << 24) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA)946#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 16947#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA 0x00FF0000948#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA(v) \949 (((v) << 16) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA)950#define BP_PXP_ALPHA_B_CTRL_RSVD0 14951#define BM_PXP_ALPHA_B_CTRL_RSVD0 0x0000C000952#define BF_PXP_ALPHA_B_CTRL_RSVD0(v) \953 (((v) << 14) & BM_PXP_ALPHA_B_CTRL_RSVD0)954#define BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE 0x00002000955#define BF_PXP_ALPHA_B_CTRL_S1_COLOR_MODE(v) \956 (((v) << 13) & BM_PXP_ALPHA_B_CTRL_S1_COLOR_MODE)957#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__0 0x0958#define BV_PXP_ALPHA_B_CTRL_S1_COLOR_MODE__1 0x1959#define BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE 0x00001000960#define BF_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE(v) \961 (((v) << 12) & BM_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE)962#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__0 0x0963#define BV_PXP_ALPHA_B_CTRL_S1_ALPHA_MODE__1 0x1964#define BP_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 10965#define BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE 0x00000C00966#define BF_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE(v) \967 (((v) << 10) & BM_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE)968#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__0 0x0969#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__1 0x1970#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__2 0x2971#define BV_PXP_ALPHA_B_CTRL_S1_GLOBAL_ALPHA_MODE__3 0x3972#define BP_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 8973#define BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE 0x00000300974#define BF_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE(v) \975 (((v) << 8) & BM_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE)976#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__0 0x0977#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__1 0x1978#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__2 0x2979#define BV_PXP_ALPHA_B_CTRL_S1_S0_FACTOR_MODE__3 0x3980#define BM_PXP_ALPHA_B_CTRL_RSVD1 0x00000080981#define BF_PXP_ALPHA_B_CTRL_RSVD1(v) \982 (((v) << 7) & BM_PXP_ALPHA_B_CTRL_RSVD1)983#define BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE 0x00000040984#define BF_PXP_ALPHA_B_CTRL_S0_COLOR_MODE(v) \985 (((v) << 6) & BM_PXP_ALPHA_B_CTRL_S0_COLOR_MODE)986#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__0 0x0987#define BV_PXP_ALPHA_B_CTRL_S0_COLOR_MODE__1 0x1988#define BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE 0x00000020989#define BF_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE(v) \990 (((v) << 5) & BM_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE)991#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__0 0x0992#define BV_PXP_ALPHA_B_CTRL_S0_ALPHA_MODE__1 0x1993#define BP_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 3994#define BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE 0x00000018995#define BF_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE(v) \996 (((v) << 3) & BM_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE)997#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__0 0x0998#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__1 0x1999#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__2 0x21000#define BV_PXP_ALPHA_B_CTRL_S0_GLOBAL_ALPHA_MODE__3 0x31001#define BP_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 11002#define BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE 0x000000061003#define BF_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE(v) \1004 (((v) << 1) & BM_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE)1005#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__0 0x01006#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__1 0x11007#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__2 0x21008#define BV_PXP_ALPHA_B_CTRL_S0_S1_FACTOR_MODE__3 0x31009#define BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE 0x000000011010#define BF_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE(v) \1011 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE)1012#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__0 0x01013#define BV_PXP_ALPHA_B_CTRL_POTER_DUFF_ENABLE__1 0x11014 1015#define HW_PXP_ALPHA_B_CTRL_1 (0x000002b0)1016 1017#define BP_PXP_ALPHA_B_CTRL_1_RSVD0 81018#define BM_PXP_ALPHA_B_CTRL_1_RSVD0 0xFFFFFF001019#define BF_PXP_ALPHA_B_CTRL_1_RSVD0(v) \1020 (((v) << 8) & BM_PXP_ALPHA_B_CTRL_1_RSVD0)1021#define BP_PXP_ALPHA_B_CTRL_1_ROP 41022#define BM_PXP_ALPHA_B_CTRL_1_ROP 0x000000F01023#define BF_PXP_ALPHA_B_CTRL_1_ROP(v) \1024 (((v) << 4) & BM_PXP_ALPHA_B_CTRL_1_ROP)1025#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKAS 0x01026#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKNOTAS 0x11027#define BV_PXP_ALPHA_B_CTRL_1_ROP__MASKASNOT 0x21028#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEAS 0x31029#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGENOTAS 0x41030#define BV_PXP_ALPHA_B_CTRL_1_ROP__MERGEASNOT 0x51031#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTCOPYAS 0x61032#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOT 0x71033#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMASKAS 0x81034#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTMERGEAS 0x91035#define BV_PXP_ALPHA_B_CTRL_1_ROP__XORAS 0xA1036#define BV_PXP_ALPHA_B_CTRL_1_ROP__NOTXORAS 0xB1037#define BP_PXP_ALPHA_B_CTRL_1_RSVD1 21038#define BM_PXP_ALPHA_B_CTRL_1_RSVD1 0x0000000C1039#define BF_PXP_ALPHA_B_CTRL_1_RSVD1(v) \1040 (((v) << 2) & BM_PXP_ALPHA_B_CTRL_1_RSVD1)1041#define BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE 0x000000021042#define BF_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE(v) \1043 (((v) << 1) & BM_PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE)1044#define BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE 0x000000011045#define BF_PXP_ALPHA_B_CTRL_1_ROP_ENABLE(v) \1046 (((v) << 0) & BM_PXP_ALPHA_B_CTRL_1_ROP_ENABLE)1047 1048#define HW_PXP_PS_BACKGROUND_1 (0x000002c0)1049 1050#define BP_PXP_PS_BACKGROUND_1_RSVD 241051#define BM_PXP_PS_BACKGROUND_1_RSVD 0xFF0000001052#define BF_PXP_PS_BACKGROUND_1_RSVD(v) \1053 (((v) << 24) & BM_PXP_PS_BACKGROUND_1_RSVD)1054#define BP_PXP_PS_BACKGROUND_1_COLOR 01055#define BM_PXP_PS_BACKGROUND_1_COLOR 0x00FFFFFF1056#define BF_PXP_PS_BACKGROUND_1_COLOR(v) \1057 (((v) << 0) & BM_PXP_PS_BACKGROUND_1_COLOR)1058 1059#define HW_PXP_PS_CLRKEYLOW_1 (0x000002d0)1060 1061#define BP_PXP_PS_CLRKEYLOW_1_RSVD1 241062#define BM_PXP_PS_CLRKEYLOW_1_RSVD1 0xFF0000001063#define BF_PXP_PS_CLRKEYLOW_1_RSVD1(v) \1064 (((v) << 24) & BM_PXP_PS_CLRKEYLOW_1_RSVD1)1065#define BP_PXP_PS_CLRKEYLOW_1_PIXEL 01066#define BM_PXP_PS_CLRKEYLOW_1_PIXEL 0x00FFFFFF1067#define BF_PXP_PS_CLRKEYLOW_1_PIXEL(v) \1068 (((v) << 0) & BM_PXP_PS_CLRKEYLOW_1_PIXEL)1069 1070#define HW_PXP_PS_CLRKEYHIGH_1 (0x000002e0)1071 1072#define BP_PXP_PS_CLRKEYHIGH_1_RSVD1 241073#define BM_PXP_PS_CLRKEYHIGH_1_RSVD1 0xFF0000001074#define BF_PXP_PS_CLRKEYHIGH_1_RSVD1(v) \1075 (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_1_RSVD1)1076#define BP_PXP_PS_CLRKEYHIGH_1_PIXEL 01077#define BM_PXP_PS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF1078#define BF_PXP_PS_CLRKEYHIGH_1_PIXEL(v) \1079 (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_1_PIXEL)1080 1081#define HW_PXP_AS_CLRKEYLOW_1 (0x000002f0)1082 1083#define BP_PXP_AS_CLRKEYLOW_1_RSVD1 241084#define BM_PXP_AS_CLRKEYLOW_1_RSVD1 0xFF0000001085#define BF_PXP_AS_CLRKEYLOW_1_RSVD1(v) \1086 (((v) << 24) & BM_PXP_AS_CLRKEYLOW_1_RSVD1)1087#define BP_PXP_AS_CLRKEYLOW_1_PIXEL 01088#define BM_PXP_AS_CLRKEYLOW_1_PIXEL 0x00FFFFFF1089#define BF_PXP_AS_CLRKEYLOW_1_PIXEL(v) \1090 (((v) << 0) & BM_PXP_AS_CLRKEYLOW_1_PIXEL)1091 1092#define HW_PXP_AS_CLRKEYHIGH_1 (0x00000300)1093 1094#define BP_PXP_AS_CLRKEYHIGH_1_RSVD1 241095#define BM_PXP_AS_CLRKEYHIGH_1_RSVD1 0xFF0000001096#define BF_PXP_AS_CLRKEYHIGH_1_RSVD1(v) \1097 (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_1_RSVD1)1098#define BP_PXP_AS_CLRKEYHIGH_1_PIXEL 01099#define BM_PXP_AS_CLRKEYHIGH_1_PIXEL 0x00FFFFFF1100#define BF_PXP_AS_CLRKEYHIGH_1_PIXEL(v) \1101 (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_1_PIXEL)1102 1103#define HW_PXP_CTRL2 (0x00000310)1104#define HW_PXP_CTRL2_SET (0x00000314)1105#define HW_PXP_CTRL2_CLR (0x00000318)1106#define HW_PXP_CTRL2_TOG (0x0000031c)1107 1108#define BP_PXP_CTRL2_RSVD3 281109#define BM_PXP_CTRL2_RSVD3 0xF00000001110#define BF_PXP_CTRL2_RSVD3(v) \1111 (((v) << 28) & BM_PXP_CTRL2_RSVD3)1112#define BM_PXP_CTRL2_ENABLE_ROTATE1 0x080000001113#define BF_PXP_CTRL2_ENABLE_ROTATE1(v) \1114 (((v) << 27) & BM_PXP_CTRL2_ENABLE_ROTATE1)1115#define BM_PXP_CTRL2_ENABLE_ROTATE0 0x040000001116#define BF_PXP_CTRL2_ENABLE_ROTATE0(v) \1117 (((v) << 26) & BM_PXP_CTRL2_ENABLE_ROTATE0)1118#define BM_PXP_CTRL2_ENABLE_LUT 0x020000001119#define BF_PXP_CTRL2_ENABLE_LUT(v) \1120 (((v) << 25) & BM_PXP_CTRL2_ENABLE_LUT)1121#define BM_PXP_CTRL2_ENABLE_CSC2 0x010000001122#define BF_PXP_CTRL2_ENABLE_CSC2(v) \1123 (((v) << 24) & BM_PXP_CTRL2_ENABLE_CSC2)1124#define BM_PXP_CTRL2_BLOCK_SIZE 0x008000001125#define BF_PXP_CTRL2_BLOCK_SIZE(v) \1126 (((v) << 23) & BM_PXP_CTRL2_BLOCK_SIZE)1127#define BV_PXP_CTRL2_BLOCK_SIZE__8X8 0x01128#define BV_PXP_CTRL2_BLOCK_SIZE__16X16 0x11129#define BM_PXP_CTRL2_RSVD2 0x004000001130#define BF_PXP_CTRL2_RSVD2(v) \1131 (((v) << 22) & BM_PXP_CTRL2_RSVD2)1132#define BM_PXP_CTRL2_ENABLE_ALPHA_B 0x002000001133#define BF_PXP_CTRL2_ENABLE_ALPHA_B(v) \1134 (((v) << 21) & BM_PXP_CTRL2_ENABLE_ALPHA_B)1135#define BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE 0x001000001136#define BF_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE(v) \1137 (((v) << 20) & BM_PXP_CTRL2_ENABLE_INPUT_FETCH_STORE)1138#define BM_PXP_CTRL2_ENABLE_WFE_B 0x000800001139#define BF_PXP_CTRL2_ENABLE_WFE_B(v) \1140 (((v) << 19) & BM_PXP_CTRL2_ENABLE_WFE_B)1141#define BM_PXP_CTRL2_ENABLE_WFE_A 0x000400001142#define BF_PXP_CTRL2_ENABLE_WFE_A(v) \1143 (((v) << 18) & BM_PXP_CTRL2_ENABLE_WFE_A)1144#define BM_PXP_CTRL2_ENABLE_DITHER 0x000200001145#define BF_PXP_CTRL2_ENABLE_DITHER(v) \1146 (((v) << 17) & BM_PXP_CTRL2_ENABLE_DITHER)1147#define BM_PXP_CTRL2_RSVD1 0x000100001148#define BF_PXP_CTRL2_RSVD1(v) \1149 (((v) << 16) & BM_PXP_CTRL2_RSVD1)1150#define BM_PXP_CTRL2_VFLIP1 0x000080001151#define BF_PXP_CTRL2_VFLIP1(v) \1152 (((v) << 15) & BM_PXP_CTRL2_VFLIP1)1153#define BM_PXP_CTRL2_HFLIP1 0x000040001154#define BF_PXP_CTRL2_HFLIP1(v) \1155 (((v) << 14) & BM_PXP_CTRL2_HFLIP1)1156#define BP_PXP_CTRL2_ROTATE1 121157#define BM_PXP_CTRL2_ROTATE1 0x000030001158#define BF_PXP_CTRL2_ROTATE1(v) \1159 (((v) << 12) & BM_PXP_CTRL2_ROTATE1)1160#define BV_PXP_CTRL2_ROTATE1__ROT_0 0x01161#define BV_PXP_CTRL2_ROTATE1__ROT_90 0x11162#define BV_PXP_CTRL2_ROTATE1__ROT_180 0x21163#define BV_PXP_CTRL2_ROTATE1__ROT_270 0x31164#define BM_PXP_CTRL2_VFLIP0 0x000008001165#define BF_PXP_CTRL2_VFLIP0(v) \1166 (((v) << 11) & BM_PXP_CTRL2_VFLIP0)1167#define BM_PXP_CTRL2_HFLIP0 0x000004001168#define BF_PXP_CTRL2_HFLIP0(v) \1169 (((v) << 10) & BM_PXP_CTRL2_HFLIP0)1170#define BP_PXP_CTRL2_ROTATE0 81171#define BM_PXP_CTRL2_ROTATE0 0x000003001172#define BF_PXP_CTRL2_ROTATE0(v) \1173 (((v) << 8) & BM_PXP_CTRL2_ROTATE0)1174#define BV_PXP_CTRL2_ROTATE0__ROT_0 0x01175#define BV_PXP_CTRL2_ROTATE0__ROT_90 0x11176#define BV_PXP_CTRL2_ROTATE0__ROT_180 0x21177#define BV_PXP_CTRL2_ROTATE0__ROT_270 0x31178#define BP_PXP_CTRL2_RSVD0 11179#define BM_PXP_CTRL2_RSVD0 0x000000FE1180#define BF_PXP_CTRL2_RSVD0(v) \1181 (((v) << 1) & BM_PXP_CTRL2_RSVD0)1182#define BM_PXP_CTRL2_ENABLE 0x000000011183#define BF_PXP_CTRL2_ENABLE(v) \1184 (((v) << 0) & BM_PXP_CTRL2_ENABLE)1185 1186#define HW_PXP_POWER_REG0 (0x00000320)1187 1188#define BP_PXP_POWER_REG0_CTRL 121189#define BM_PXP_POWER_REG0_CTRL 0xFFFFF0001190#define BF_PXP_POWER_REG0_CTRL(v) \1191 (((v) << 12) & BM_PXP_POWER_REG0_CTRL)1192#define BP_PXP_POWER_REG0_ROT0_MEM_LP_STATE 91193#define BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE 0x00000E001194#define BF_PXP_POWER_REG0_ROT0_MEM_LP_STATE(v) \1195 (((v) << 9) & BM_PXP_POWER_REG0_ROT0_MEM_LP_STATE)1196#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__NONE 0x01197#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__LS 0x11198#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__DS 0x21199#define BV_PXP_POWER_REG0_ROT0_MEM_LP_STATE__SD 0x41200#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 61201#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN 0x000001C01202#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(v) \1203 (((v) << 6) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN)1204#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__NONE 0x01205#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__LS 0x11206#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__DS 0x21207#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN__SD 0x41208#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 31209#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN 0x000000381210#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(v) \1211 (((v) << 3) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN)1212#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__NONE 0x01213#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__LS 0x11214#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__DS 0x21215#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN__SD 0x41216#define BP_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 01217#define BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0 0x000000071218#define BF_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(v) \1219 (((v) << 0) & BM_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0)1220#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__NONE 0x01221#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__LS 0x11222#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__DS 0x21223#define BV_PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0__SD 0x41224 1225#define HW_PXP_POWER_REG1 (0x00000330)1226 1227#define BP_PXP_POWER_REG1_RSVD0 241228#define BM_PXP_POWER_REG1_RSVD0 0xFF0000001229#define BF_PXP_POWER_REG1_RSVD0(v) \1230 (((v) << 24) & BM_PXP_POWER_REG1_RSVD0)1231#define BP_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 211232#define BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE 0x00E000001233#define BF_PXP_POWER_REG1_ALU_B_MEM_LP_STATE(v) \1234 (((v) << 21) & BM_PXP_POWER_REG1_ALU_B_MEM_LP_STATE)1235#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__NONE 0x01236#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__LS 0x11237#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__DS 0x21238#define BV_PXP_POWER_REG1_ALU_B_MEM_LP_STATE__SD 0x41239#define BP_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 181240#define BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE 0x001C00001241#define BF_PXP_POWER_REG1_ALU_A_MEM_LP_STATE(v) \1242 (((v) << 18) & BM_PXP_POWER_REG1_ALU_A_MEM_LP_STATE)1243#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__NONE 0x01244#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__LS 0x11245#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__DS 0x21246#define BV_PXP_POWER_REG1_ALU_A_MEM_LP_STATE__SD 0x41247#define BP_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 151248#define BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE 0x000380001249#define BF_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(v) \1250 (((v) << 15) & BM_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE)1251#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__NONE 0x01252#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__LS 0x11253#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__DS 0x21254#define BV_PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE__SD 0x41255#define BP_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 121256#define BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE 0x000070001257#define BF_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(v) \1258 (((v) << 12) & BM_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE)1259#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__NONE 0x01260#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__LS 0x11261#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__DS 0x21262#define BV_PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE__SD 0x41263#define BP_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 91264#define BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE 0x00000E001265#define BF_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(v) \1266 (((v) << 9) & BM_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE)1267#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__NONE 0x01268#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__LS 0x11269#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__DS 0x21270#define BV_PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE__SD 0x41271#define BP_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 61272#define BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE 0x000001C01273#define BF_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(v) \1274 (((v) << 6) & BM_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE)1275#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__NONE 0x01276#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__LS 0x11277#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__DS 0x21278#define BV_PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE__SD 0x41279#define BP_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 31280#define BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE 0x000000381281#define BF_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(v) \1282 (((v) << 3) & BM_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE)1283#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__NONE 0x01284#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__LS 0x11285#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__DS 0x21286#define BV_PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE__SD 0x41287#define BP_PXP_POWER_REG1_ROT1_MEM_LP_STATE 01288#define BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE 0x000000071289#define BF_PXP_POWER_REG1_ROT1_MEM_LP_STATE(v) \1290 (((v) << 0) & BM_PXP_POWER_REG1_ROT1_MEM_LP_STATE)1291#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__NONE 0x01292#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__LS 0x11293#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__DS 0x21294#define BV_PXP_POWER_REG1_ROT1_MEM_LP_STATE__SD 0x41295 1296#define HW_PXP_DATA_PATH_CTRL0 (0x00000340)1297#define HW_PXP_DATA_PATH_CTRL0_SET (0x00000344)1298#define HW_PXP_DATA_PATH_CTRL0_CLR (0x00000348)1299#define HW_PXP_DATA_PATH_CTRL0_TOG (0x0000034c)1300 1301#define BP_PXP_DATA_PATH_CTRL0_MUX15_SEL 301302#define BM_PXP_DATA_PATH_CTRL0_MUX15_SEL 0xC00000001303#define BF_PXP_DATA_PATH_CTRL0_MUX15_SEL(v) \1304 (((v) << 30) & BM_PXP_DATA_PATH_CTRL0_MUX15_SEL)1305#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__0 0x01306#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__1 0x11307#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__2 0x21308#define BV_PXP_DATA_PATH_CTRL0_MUX15_SEL__3 0x31309#define BP_PXP_DATA_PATH_CTRL0_MUX14_SEL 281310#define BM_PXP_DATA_PATH_CTRL0_MUX14_SEL 0x300000001311#define BF_PXP_DATA_PATH_CTRL0_MUX14_SEL(v) \1312 (((v) << 28) & BM_PXP_DATA_PATH_CTRL0_MUX14_SEL)1313#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__0 0x01314#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__1 0x11315#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__2 0x21316#define BV_PXP_DATA_PATH_CTRL0_MUX14_SEL__3 0x31317#define BP_PXP_DATA_PATH_CTRL0_MUX13_SEL 261318#define BM_PXP_DATA_PATH_CTRL0_MUX13_SEL 0x0C0000001319#define BF_PXP_DATA_PATH_CTRL0_MUX13_SEL(v) \1320 (((v) << 26) & BM_PXP_DATA_PATH_CTRL0_MUX13_SEL)1321#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__0 0x01322#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__1 0x11323#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__2 0x21324#define BV_PXP_DATA_PATH_CTRL0_MUX13_SEL__3 0x31325#define BP_PXP_DATA_PATH_CTRL0_MUX12_SEL 241326#define BM_PXP_DATA_PATH_CTRL0_MUX12_SEL 0x030000001327#define BF_PXP_DATA_PATH_CTRL0_MUX12_SEL(v) \1328 (((v) << 24) & BM_PXP_DATA_PATH_CTRL0_MUX12_SEL)1329#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__0 0x01330#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__1 0x11331#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__2 0x21332#define BV_PXP_DATA_PATH_CTRL0_MUX12_SEL__3 0x31333#define BP_PXP_DATA_PATH_CTRL0_MUX11_SEL 221334#define BM_PXP_DATA_PATH_CTRL0_MUX11_SEL 0x00C000001335#define BF_PXP_DATA_PATH_CTRL0_MUX11_SEL(v) \1336 (((v) << 22) & BM_PXP_DATA_PATH_CTRL0_MUX11_SEL)1337#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__0 0x01338#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__1 0x11339#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__2 0x21340#define BV_PXP_DATA_PATH_CTRL0_MUX11_SEL__3 0x31341#define BP_PXP_DATA_PATH_CTRL0_MUX10_SEL 201342#define BM_PXP_DATA_PATH_CTRL0_MUX10_SEL 0x003000001343#define BF_PXP_DATA_PATH_CTRL0_MUX10_SEL(v) \1344 (((v) << 20) & BM_PXP_DATA_PATH_CTRL0_MUX10_SEL)1345#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__0 0x01346#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__1 0x11347#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__2 0x21348#define BV_PXP_DATA_PATH_CTRL0_MUX10_SEL__3 0x31349#define BP_PXP_DATA_PATH_CTRL0_MUX9_SEL 181350#define BM_PXP_DATA_PATH_CTRL0_MUX9_SEL 0x000C00001351#define BF_PXP_DATA_PATH_CTRL0_MUX9_SEL(v) \1352 (((v) << 18) & BM_PXP_DATA_PATH_CTRL0_MUX9_SEL)1353#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__0 0x01354#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__1 0x11355#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__2 0x21356#define BV_PXP_DATA_PATH_CTRL0_MUX9_SEL__3 0x31357#define BP_PXP_DATA_PATH_CTRL0_MUX8_SEL 161358#define BM_PXP_DATA_PATH_CTRL0_MUX8_SEL 0x000300001359#define BF_PXP_DATA_PATH_CTRL0_MUX8_SEL(v) \1360 (((v) << 16) & BM_PXP_DATA_PATH_CTRL0_MUX8_SEL)1361#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__0 0x01362#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__1 0x11363#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__2 0x21364#define BV_PXP_DATA_PATH_CTRL0_MUX8_SEL__3 0x31365#define BP_PXP_DATA_PATH_CTRL0_MUX7_SEL 141366#define BM_PXP_DATA_PATH_CTRL0_MUX7_SEL 0x0000C0001367#define BF_PXP_DATA_PATH_CTRL0_MUX7_SEL(v) \1368 (((v) << 14) & BM_PXP_DATA_PATH_CTRL0_MUX7_SEL)1369#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__0 0x01370#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__1 0x11371#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__2 0x21372#define BV_PXP_DATA_PATH_CTRL0_MUX7_SEL__3 0x31373#define BP_PXP_DATA_PATH_CTRL0_MUX6_SEL 121374#define BM_PXP_DATA_PATH_CTRL0_MUX6_SEL 0x000030001375#define BF_PXP_DATA_PATH_CTRL0_MUX6_SEL(v) \1376 (((v) << 12) & BM_PXP_DATA_PATH_CTRL0_MUX6_SEL)1377#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__0 0x01378#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__1 0x11379#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__2 0x21380#define BV_PXP_DATA_PATH_CTRL0_MUX6_SEL__3 0x31381#define BP_PXP_DATA_PATH_CTRL0_MUX5_SEL 101382#define BM_PXP_DATA_PATH_CTRL0_MUX5_SEL 0x00000C001383#define BF_PXP_DATA_PATH_CTRL0_MUX5_SEL(v) \1384 (((v) << 10) & BM_PXP_DATA_PATH_CTRL0_MUX5_SEL)1385#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__0 0x01386#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__1 0x11387#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__2 0x21388#define BV_PXP_DATA_PATH_CTRL0_MUX5_SEL__3 0x31389#define BP_PXP_DATA_PATH_CTRL0_MUX4_SEL 81390#define BM_PXP_DATA_PATH_CTRL0_MUX4_SEL 0x000003001391#define BF_PXP_DATA_PATH_CTRL0_MUX4_SEL(v) \1392 (((v) << 8) & BM_PXP_DATA_PATH_CTRL0_MUX4_SEL)1393#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__0 0x01394#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__1 0x11395#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__2 0x21396#define BV_PXP_DATA_PATH_CTRL0_MUX4_SEL__3 0x31397#define BP_PXP_DATA_PATH_CTRL0_MUX3_SEL 61398#define BM_PXP_DATA_PATH_CTRL0_MUX3_SEL 0x000000C01399#define BF_PXP_DATA_PATH_CTRL0_MUX3_SEL(v) \1400 (((v) << 6) & BM_PXP_DATA_PATH_CTRL0_MUX3_SEL)1401#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__0 0x01402#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__1 0x11403#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__2 0x21404#define BV_PXP_DATA_PATH_CTRL0_MUX3_SEL__3 0x31405#define BP_PXP_DATA_PATH_CTRL0_MUX2_SEL 41406#define BM_PXP_DATA_PATH_CTRL0_MUX2_SEL 0x000000301407#define BF_PXP_DATA_PATH_CTRL0_MUX2_SEL(v) \1408 (((v) << 4) & BM_PXP_DATA_PATH_CTRL0_MUX2_SEL)1409#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__0 0x01410#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__1 0x11411#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__2 0x21412#define BV_PXP_DATA_PATH_CTRL0_MUX2_SEL__3 0x31413#define BP_PXP_DATA_PATH_CTRL0_MUX1_SEL 21414#define BM_PXP_DATA_PATH_CTRL0_MUX1_SEL 0x0000000C1415#define BF_PXP_DATA_PATH_CTRL0_MUX1_SEL(v) \1416 (((v) << 2) & BM_PXP_DATA_PATH_CTRL0_MUX1_SEL)1417#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__0 0x01418#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__1 0x11419#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__2 0x21420#define BV_PXP_DATA_PATH_CTRL0_MUX1_SEL__3 0x31421#define BP_PXP_DATA_PATH_CTRL0_MUX0_SEL 01422#define BM_PXP_DATA_PATH_CTRL0_MUX0_SEL 0x000000031423#define BF_PXP_DATA_PATH_CTRL0_MUX0_SEL(v) \1424 (((v) << 0) & BM_PXP_DATA_PATH_CTRL0_MUX0_SEL)1425#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__0 0x01426#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__1 0x11427#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__2 0x21428#define BV_PXP_DATA_PATH_CTRL0_MUX0_SEL__3 0x31429 1430#define HW_PXP_DATA_PATH_CTRL1 (0x00000350)1431#define HW_PXP_DATA_PATH_CTRL1_SET (0x00000354)1432#define HW_PXP_DATA_PATH_CTRL1_CLR (0x00000358)1433#define HW_PXP_DATA_PATH_CTRL1_TOG (0x0000035c)1434 1435#define BP_PXP_DATA_PATH_CTRL1_RSVD0 41436#define BM_PXP_DATA_PATH_CTRL1_RSVD0 0xFFFFFFF01437#define BF_PXP_DATA_PATH_CTRL1_RSVD0(v) \1438 (((v) << 4) & BM_PXP_DATA_PATH_CTRL1_RSVD0)1439#define BP_PXP_DATA_PATH_CTRL1_MUX17_SEL 21440#define BM_PXP_DATA_PATH_CTRL1_MUX17_SEL 0x0000000C1441#define BF_PXP_DATA_PATH_CTRL1_MUX17_SEL(v) \1442 (((v) << 2) & BM_PXP_DATA_PATH_CTRL1_MUX17_SEL)1443#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__0 0x01444#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__1 0x11445#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__2 0x21446#define BV_PXP_DATA_PATH_CTRL1_MUX17_SEL__3 0x31447#define BP_PXP_DATA_PATH_CTRL1_MUX16_SEL 01448#define BM_PXP_DATA_PATH_CTRL1_MUX16_SEL 0x000000031449#define BF_PXP_DATA_PATH_CTRL1_MUX16_SEL(v) \1450 (((v) << 0) & BM_PXP_DATA_PATH_CTRL1_MUX16_SEL)1451#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__0 0x01452#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__1 0x11453#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__2 0x21454#define BV_PXP_DATA_PATH_CTRL1_MUX16_SEL__3 0x31455 1456#define HW_PXP_INIT_MEM_CTRL (0x00000360)1457#define HW_PXP_INIT_MEM_CTRL_SET (0x00000364)1458#define HW_PXP_INIT_MEM_CTRL_CLR (0x00000368)1459#define HW_PXP_INIT_MEM_CTRL_TOG (0x0000036c)1460 1461#define BM_PXP_INIT_MEM_CTRL_START 0x800000001462#define BF_PXP_INIT_MEM_CTRL_START(v) \1463 (((v) << 31) & BM_PXP_INIT_MEM_CTRL_START)1464#define BP_PXP_INIT_MEM_CTRL_SELECT 271465#define BM_PXP_INIT_MEM_CTRL_SELECT 0x780000001466#define BF_PXP_INIT_MEM_CTRL_SELECT(v) \1467 (((v) << 27) & BM_PXP_INIT_MEM_CTRL_SELECT)1468#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_LUT 0x01469#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR0 0x11470#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER0_ERR1 0x21471#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER1_LUT 0x31472#define BV_PXP_INIT_MEM_CTRL_SELECT__DITHER2_LUT 0x41473#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_A 0x51474#define BV_PXP_INIT_MEM_CTRL_SELECT__ALU_B 0x61475#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_A_FETCH 0x71476#define BV_PXP_INIT_MEM_CTRL_SELECT__WFE_B_FETCH 0x81477#define BV_PXP_INIT_MEM_CTRL_SELECT__RESERVED 0x151478#define BP_PXP_INIT_MEM_CTRL_RSVD0 161479#define BM_PXP_INIT_MEM_CTRL_RSVD0 0x07FF00001480#define BF_PXP_INIT_MEM_CTRL_RSVD0(v) \1481 (((v) << 16) & BM_PXP_INIT_MEM_CTRL_RSVD0)1482#define BP_PXP_INIT_MEM_CTRL_ADDR 01483#define BM_PXP_INIT_MEM_CTRL_ADDR 0x0000FFFF1484#define BF_PXP_INIT_MEM_CTRL_ADDR(v) \1485 (((v) << 0) & BM_PXP_INIT_MEM_CTRL_ADDR)1486 1487#define HW_PXP_INIT_MEM_DATA (0x00000370)1488 1489#define BP_PXP_INIT_MEM_DATA_DATA 01490#define BM_PXP_INIT_MEM_DATA_DATA 0xFFFFFFFF1491#define BF_PXP_INIT_MEM_DATA_DATA(v) (v)1492 1493#define HW_PXP_INIT_MEM_DATA_HIGH (0x00000380)1494 1495#define BP_PXP_INIT_MEM_DATA_HIGH_DATA 01496#define BM_PXP_INIT_MEM_DATA_HIGH_DATA 0xFFFFFFFF1497#define BF_PXP_INIT_MEM_DATA_HIGH_DATA(v) (v)1498 1499#define HW_PXP_IRQ_MASK (0x00000390)1500#define HW_PXP_IRQ_MASK_SET (0x00000394)1501#define HW_PXP_IRQ_MASK_CLR (0x00000398)1502#define HW_PXP_IRQ_MASK_TOG (0x0000039c)1503 1504#define BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN 0x800000001505#define BF_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN(v) \1506 (((v) << 31) & BM_PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN)1507#define BP_PXP_IRQ_MASK_RSVD1 161508#define BM_PXP_IRQ_MASK_RSVD1 0x7FFF00001509#define BF_PXP_IRQ_MASK_RSVD1(v) \1510 (((v) << 16) & BM_PXP_IRQ_MASK_RSVD1)1511#define BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN 0x000080001512#define BF_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(v) \1513 (((v) << 15) & BM_PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN)1514#define BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN 0x000040001515#define BF_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN(v) \1516 (((v) << 14) & BM_PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN)1517#define BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN 0x000020001518#define BF_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN(v) \1519 (((v) << 13) & BM_PXP_IRQ_MASK_DITHER_STORE_IRQ_EN)1520#define BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN 0x000010001521#define BF_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN(v) \1522 (((v) << 12) & BM_PXP_IRQ_MASK_FIRST_STORE_IRQ_EN)1523#define BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN 0x000008001524#define BF_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(v) \1525 (((v) << 11) & BM_PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN)1526#define BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN 0x000004001527#define BF_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(v) \1528 (((v) << 10) & BM_PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN)1529#define BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN 0x000002001530#define BF_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN(v) \1531 (((v) << 9) & BM_PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN)1532#define BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN 0x000001001533#define BF_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN(v) \1534 (((v) << 8) & BM_PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN)1535#define BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN 0x000000801536#define BF_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN(v) \1537 (((v) << 7) & BM_PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN)1538#define BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN 0x000000401539#define BF_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN(v) \1540 (((v) << 6) & BM_PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN)1541#define BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN 0x000000201542#define BF_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN(v) \1543 (((v) << 5) & BM_PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN)1544#define BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN 0x000000101545#define BF_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN(v) \1546 (((v) << 4) & BM_PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN)1547#define BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN 0x000000081548#define BF_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN(v) \1549 (((v) << 3) & BM_PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN)1550#define BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN 0x000000041551#define BF_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN(v) \1552 (((v) << 2) & BM_PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN)1553#define BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN 0x000000021554#define BF_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN(v) \1555 (((v) << 1) & BM_PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN)1556#define BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN 0x000000011557#define BF_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN(v) \1558 (((v) << 0) & BM_PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN)1559 1560#define HW_PXP_IRQ (0x000003a0)1561#define HW_PXP_IRQ_SET (0x000003a4)1562#define HW_PXP_IRQ_CLR (0x000003a8)1563#define HW_PXP_IRQ_TOG (0x000003ac)1564 1565#define BM_PXP_IRQ_COMPRESS_DONE_IRQ 0x800000001566#define BF_PXP_IRQ_COMPRESS_DONE_IRQ(v) \1567 (((v) << 31) & BM_PXP_IRQ_COMPRESS_DONE_IRQ)1568#define BP_PXP_IRQ_RSVD1 161569#define BM_PXP_IRQ_RSVD1 0x7FFF00001570#define BF_PXP_IRQ_RSVD1(v) \1571 (((v) << 16) & BM_PXP_IRQ_RSVD1)1572#define BM_PXP_IRQ_WFE_B_STORE_IRQ 0x000080001573#define BF_PXP_IRQ_WFE_B_STORE_IRQ(v) \1574 (((v) << 15) & BM_PXP_IRQ_WFE_B_STORE_IRQ)1575#define BM_PXP_IRQ_WFE_A_STORE_IRQ 0x000040001576#define BF_PXP_IRQ_WFE_A_STORE_IRQ(v) \1577 (((v) << 14) & BM_PXP_IRQ_WFE_A_STORE_IRQ)1578#define BM_PXP_IRQ_DITHER_STORE_IRQ 0x000020001579#define BF_PXP_IRQ_DITHER_STORE_IRQ(v) \1580 (((v) << 13) & BM_PXP_IRQ_DITHER_STORE_IRQ)1581#define BM_PXP_IRQ_FIRST_STORE_IRQ 0x000010001582#define BF_PXP_IRQ_FIRST_STORE_IRQ(v) \1583 (((v) << 12) & BM_PXP_IRQ_FIRST_STORE_IRQ)1584#define BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ 0x000008001585#define BF_PXP_IRQ_WFE_B_CH1_STORE_IRQ(v) \1586 (((v) << 11) & BM_PXP_IRQ_WFE_B_CH1_STORE_IRQ)1587#define BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ 0x000004001588#define BF_PXP_IRQ_WFE_B_CH0_STORE_IRQ(v) \1589 (((v) << 10) & BM_PXP_IRQ_WFE_B_CH0_STORE_IRQ)1590#define BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ 0x000002001591#define BF_PXP_IRQ_WFE_A_CH1_STORE_IRQ(v) \1592 (((v) << 9) & BM_PXP_IRQ_WFE_A_CH1_STORE_IRQ)1593#define BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ 0x000001001594#define BF_PXP_IRQ_WFE_A_CH0_STORE_IRQ(v) \1595 (((v) << 8) & BM_PXP_IRQ_WFE_A_CH0_STORE_IRQ)1596#define BM_PXP_IRQ_DITHER_CH1_STORE_IRQ 0x000000801597#define BF_PXP_IRQ_DITHER_CH1_STORE_IRQ(v) \1598 (((v) << 7) & BM_PXP_IRQ_DITHER_CH1_STORE_IRQ)1599#define BM_PXP_IRQ_DITHER_CH0_STORE_IRQ 0x000000401600#define BF_PXP_IRQ_DITHER_CH0_STORE_IRQ(v) \1601 (((v) << 6) & BM_PXP_IRQ_DITHER_CH0_STORE_IRQ)1602#define BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ 0x000000201603#define BF_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ(v) \1604 (((v) << 5) & BM_PXP_IRQ_DITHER_CH1_PREFETCH_IRQ)1605#define BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ 0x000000101606#define BF_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ(v) \1607 (((v) << 4) & BM_PXP_IRQ_DITHER_CH0_PREFETCH_IRQ)1608#define BM_PXP_IRQ_FIRST_CH1_STORE_IRQ 0x000000081609#define BF_PXP_IRQ_FIRST_CH1_STORE_IRQ(v) \1610 (((v) << 3) & BM_PXP_IRQ_FIRST_CH1_STORE_IRQ)1611#define BM_PXP_IRQ_FIRST_CH0_STORE_IRQ 0x000000041612#define BF_PXP_IRQ_FIRST_CH0_STORE_IRQ(v) \1613 (((v) << 2) & BM_PXP_IRQ_FIRST_CH0_STORE_IRQ)1614#define BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ 0x000000021615#define BF_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ(v) \1616 (((v) << 1) & BM_PXP_IRQ_FIRST_CH1_PREFETCH_IRQ)1617#define BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ 0x000000011618#define BF_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ(v) \1619 (((v) << 0) & BM_PXP_IRQ_FIRST_CH0_PREFETCH_IRQ)1620 1621#define HW_PXP_NEXT (0x00000400)1622 1623#define BP_PXP_NEXT_POINTER 21624#define BM_PXP_NEXT_POINTER 0xFFFFFFFC1625#define BF_PXP_NEXT_POINTER(v) \1626 (((v) << 2) & BM_PXP_NEXT_POINTER)1627#define BM_PXP_NEXT_RSVD 0x000000021628#define BF_PXP_NEXT_RSVD(v) \1629 (((v) << 1) & BM_PXP_NEXT_RSVD)1630#define BM_PXP_NEXT_ENABLED 0x000000011631#define BF_PXP_NEXT_ENABLED(v) \1632 (((v) << 0) & BM_PXP_NEXT_ENABLED)1633 1634#define HW_PXP_DEBUGCTRL (0x00000410)1635 1636#define BP_PXP_DEBUGCTRL_RSVD 121637#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF0001638#define BF_PXP_DEBUGCTRL_RSVD(v) \1639 (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD)1640#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 81641#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F001642#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \1643 (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT)1644#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x01645#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x11646#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x21647#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x41648#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x81649#define BP_PXP_DEBUGCTRL_SELECT 01650#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF1651#define BF_PXP_DEBUGCTRL_SELECT(v) \1652 (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)1653#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x01654#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x11655#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x21656#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x31657#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x41658#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x51659#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x61660#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x71661#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x81662#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x91663#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x101664#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x111665#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x121666#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x131667#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x141668 1669#define HW_PXP_DEBUG (0x00000420)1670 1671#define BP_PXP_DEBUG_DATA 01672#define BM_PXP_DEBUG_DATA 0xFFFFFFFF1673#define BF_PXP_DEBUG_DATA(v) (v)1674 1675#define HW_PXP_VERSION (0x00000430)1676 1677#define BP_PXP_VERSION_MAJOR 241678#define BM_PXP_VERSION_MAJOR 0xFF0000001679#define BF_PXP_VERSION_MAJOR(v) \1680 (((v) << 24) & BM_PXP_VERSION_MAJOR)1681#define BP_PXP_VERSION_MINOR 161682#define BM_PXP_VERSION_MINOR 0x00FF00001683#define BF_PXP_VERSION_MINOR(v) \1684 (((v) << 16) & BM_PXP_VERSION_MINOR)1685#define BP_PXP_VERSION_STEP 01686#define BM_PXP_VERSION_STEP 0x0000FFFF1687#define BF_PXP_VERSION_STEP(v) \1688 (((v) << 0) & BM_PXP_VERSION_STEP)1689 1690#endif /* __IMX_PXP_H__ */1691