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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright 2019-2020 NXP4 */5 6#ifndef __IMX8_ISI_REGS_H__7#define __IMX8_ISI_REGS_H__8 9#include <linux/bits.h>10 11/* ISI Registers Define */12/* Channel Control Register */13#define CHNL_CTRL 0x000014#define CHNL_CTRL_CHNL_EN BIT(31)15#define CHNL_CTRL_CLK_EN BIT(30)16#define CHNL_CTRL_CHNL_BYPASS BIT(29)17#define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25)18#define CHNL_CTRL_CHAIN_BUF_MASK GENMASK(26, 25)19#define CHNL_CTRL_CHAIN_BUF_NO_CHAIN 020#define CHNL_CTRL_CHAIN_BUF_2_CHAIN 121#define CHNL_CTRL_SW_RST BIT(24)22#define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)23#define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)24#define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6)25#define CHNL_CTRL_MIPI_VC_ID_MASK GENMASK(7, 6)26#define CHNL_CTRL_SRC_TYPE(n) ((n) << 4)27#define CHNL_CTRL_SRC_TYPE_MASK BIT(4)28#define CHNL_CTRL_SRC_TYPE_DEVICE 029#define CHNL_CTRL_SRC_TYPE_MEMORY 130#define CHNL_CTRL_SRC_INPUT(n) ((n) << 0)31#define CHNL_CTRL_SRC_INPUT_MASK GENMASK(2, 0)32 33/* Channel Image Control Register */34#define CHNL_IMG_CTRL 0x000435#define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24)36#define CHNL_IMG_CTRL_FORMAT_MASK GENMASK(29, 24)37#define CHNL_IMG_CTRL_FORMAT_RGBA8888 0x0038#define CHNL_IMG_CTRL_FORMAT_ABGR8888 0x0139#define CHNL_IMG_CTRL_FORMAT_ARGB8888 0x0240#define CHNL_IMG_CTRL_FORMAT_RGBX888 0x0341#define CHNL_IMG_CTRL_FORMAT_XBGR888 0x0442#define CHNL_IMG_CTRL_FORMAT_XRGB888 0x0543#define CHNL_IMG_CTRL_FORMAT_RGB888P 0x0644#define CHNL_IMG_CTRL_FORMAT_BGR888P 0x0745#define CHNL_IMG_CTRL_FORMAT_A2BGR10 0x0846#define CHNL_IMG_CTRL_FORMAT_A2RGB10 0x0947#define CHNL_IMG_CTRL_FORMAT_RGB565 0x0a48#define CHNL_IMG_CTRL_FORMAT_RAW8 0x0b49#define CHNL_IMG_CTRL_FORMAT_RAW10 0x0c50#define CHNL_IMG_CTRL_FORMAT_RAW10P 0x0d51#define CHNL_IMG_CTRL_FORMAT_RAW12 0x0e52#define CHNL_IMG_CTRL_FORMAT_RAW16 0x0f53#define CHNL_IMG_CTRL_FORMAT_YUV444_1P8P 0x1054#define CHNL_IMG_CTRL_FORMAT_YUV444_2P8P 0x1155#define CHNL_IMG_CTRL_FORMAT_YUV444_3P8P 0x1256#define CHNL_IMG_CTRL_FORMAT_YUV444_1P8 0x1357#define CHNL_IMG_CTRL_FORMAT_YUV444_1P10 0x1458#define CHNL_IMG_CTRL_FORMAT_YUV444_2P10 0x1559#define CHNL_IMG_CTRL_FORMAT_YUV444_3P10 0x1660#define CHNL_IMG_CTRL_FORMAT_YUV444_1P10P 0x1861#define CHNL_IMG_CTRL_FORMAT_YUV444_2P10P 0x1962#define CHNL_IMG_CTRL_FORMAT_YUV444_3P10P 0x1a63#define CHNL_IMG_CTRL_FORMAT_YUV444_1P12 0x1c64#define CHNL_IMG_CTRL_FORMAT_YUV444_2P12 0x1d65#define CHNL_IMG_CTRL_FORMAT_YUV444_3P12 0x1e66#define CHNL_IMG_CTRL_FORMAT_YUV422_1P8P 0x2067#define CHNL_IMG_CTRL_FORMAT_YUV422_2P8P 0x2168#define CHNL_IMG_CTRL_FORMAT_YUV422_3P8P 0x2269#define CHNL_IMG_CTRL_FORMAT_YUV422_1P10 0x2470#define CHNL_IMG_CTRL_FORMAT_YUV422_2P10 0x2571#define CHNL_IMG_CTRL_FORMAT_YUV422_3P10 0x2672#define CHNL_IMG_CTRL_FORMAT_YUV422_1P10P 0x2873#define CHNL_IMG_CTRL_FORMAT_YUV422_2P10P 0x2974#define CHNL_IMG_CTRL_FORMAT_YUV422_3P10P 0x2a75#define CHNL_IMG_CTRL_FORMAT_YUV422_1P12 0x2c76#define CHNL_IMG_CTRL_FORMAT_YUV422_2P12 0x2d77#define CHNL_IMG_CTRL_FORMAT_YUV422_3P12 0x2e78#define CHNL_IMG_CTRL_FORMAT_YUV420_2P8P 0x3179#define CHNL_IMG_CTRL_FORMAT_YUV420_3P8P 0x3280#define CHNL_IMG_CTRL_FORMAT_YUV420_2P10 0x3581#define CHNL_IMG_CTRL_FORMAT_YUV420_3P10 0x3682#define CHNL_IMG_CTRL_FORMAT_YUV420_2P10P 0x3983#define CHNL_IMG_CTRL_FORMAT_YUV420_3P10P 0x3a84#define CHNL_IMG_CTRL_FORMAT_YUV420_2P12 0x3d85#define CHNL_IMG_CTRL_FORMAT_YUV420_3P12 0x3e86#define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16)87#define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK GENMASK(23, 16)88#define CHNL_IMG_CTRL_GBL_ALPHA_EN BIT(15)89#define CHNL_IMG_CTRL_DEINT(n) ((n) << 12)90#define CHNL_IMG_CTRL_DEINT_MASK GENMASK(14, 12)91#define CHNL_IMG_CTRL_DEINT_WEAVE_ODD_EVEN 292#define CHNL_IMG_CTRL_DEINT_WEAVE_EVEN_ODD 393#define CHNL_IMG_CTRL_DEINT_BLEND_ODD_EVEN 494#define CHNL_IMG_CTRL_DEINT_BLEND_EVEN_ODD 595#define CHNL_IMG_CTRL_DEINT_LDOUBLE_ODD_EVEN 696#define CHNL_IMG_CTRL_DEINT_LDOUBLE_EVEN_ODD 797#define CHNL_IMG_CTRL_DEC_X(n) ((n) << 10)98#define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10)99#define CHNL_IMG_CTRL_DEC_Y(n) ((n) << 8)100#define CHNL_IMG_CTRL_DEC_Y_MASK GENMASK(9, 8)101#define CHNL_IMG_CTRL_CROP_EN BIT(7)102#define CHNL_IMG_CTRL_VFLIP_EN BIT(6)103#define CHNL_IMG_CTRL_HFLIP_EN BIT(5)104#define CHNL_IMG_CTRL_YCBCR_MODE BIT(3)105#define CHNL_IMG_CTRL_CSC_MODE(n) ((n) << 1)106#define CHNL_IMG_CTRL_CSC_MODE_MASK GENMASK(2, 1)107#define CHNL_IMG_CTRL_CSC_MODE_YUV2RGB 0108#define CHNL_IMG_CTRL_CSC_MODE_YCBCR2RGB 1109#define CHNL_IMG_CTRL_CSC_MODE_RGB2YUV 2110#define CHNL_IMG_CTRL_CSC_MODE_RGB2YCBCR 3111#define CHNL_IMG_CTRL_CSC_BYPASS BIT(0)112 113/* Channel Output Buffer Control Register */114#define CHNL_OUT_BUF_CTRL 0x0008115#define CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR BIT(15)116#define CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR BIT(14)117#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(n) ((n) << 6)118#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK GENMASK(7, 6)119#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_NO_PANIC 0120#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_25 1121#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_50 2122#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_75 3123#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(n) ((n) << 3)124#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK GENMASK(4, 3)125#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_NO_PANIC 0126#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_25 1127#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_50 2128#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_75 3129#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(n) ((n) << 0)130#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK GENMASK(1, 0)131#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_NO_PANIC 0132#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_25 1133#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_50 2134#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_75 3135 136/* Channel Image Configuration */137#define CHNL_IMG_CFG 0x000c138#define CHNL_IMG_CFG_HEIGHT(n) ((n) << 16)139#define CHNL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)140#define CHNL_IMG_CFG_WIDTH(n) ((n) << 0)141#define CHNL_IMG_CFG_WIDTH_MASK GENMASK(12, 0)142 143/* Channel Interrupt Enable Register */144#define CHNL_IER 0x0010145#define CHNL_IER_MEM_RD_DONE_EN BIT(31)146#define CHNL_IER_LINE_RCVD_EN BIT(30)147#define CHNL_IER_FRM_RCVD_EN BIT(29)148#define CHNL_IER_AXI_WR_ERR_V_EN BIT(28)149#define CHNL_IER_AXI_WR_ERR_U_EN BIT(27)150#define CHNL_IER_AXI_WR_ERR_Y_EN BIT(26)151#define CHNL_IER_AXI_RD_ERR_EN BIT(25)152 153/* Channel Status Register */154#define CHNL_STS 0x0014155#define CHNL_STS_MEM_RD_DONE BIT(31)156#define CHNL_STS_LINE_STRD BIT(30)157#define CHNL_STS_FRM_STRD BIT(29)158#define CHNL_STS_AXI_WR_ERR_V BIT(28)159#define CHNL_STS_AXI_WR_ERR_U BIT(27)160#define CHNL_STS_AXI_WR_ERR_Y BIT(26)161#define CHNL_STS_AXI_RD_ERR BIT(25)162#define CHNL_STS_OFLW_PANIC_V_BUF BIT(24)163#define CHNL_STS_EXCS_OFLW_V_BUF BIT(23)164#define CHNL_STS_OFLW_V_BUF BIT(22)165#define CHNL_STS_OFLW_PANIC_U_BUF BIT(21)166#define CHNL_STS_EXCS_OFLW_U_BUF BIT(20)167#define CHNL_STS_OFLW_U_BUF BIT(19)168#define CHNL_STS_OFLW_PANIC_Y_BUF BIT(18)169#define CHNL_STS_EXCS_OFLW_Y_BUF BIT(17)170#define CHNL_STS_OFLW_Y_BUF BIT(16)171#define CHNL_STS_EARLY_VSYNC_ERR BIT(15)172#define CHNL_STS_LATE_VSYNC_ERR BIT(14)173#define CHNL_STS_MEM_RD_OFLOW BIT(10)174#define CHNL_STS_BUF2_ACTIVE BIT(9)175#define CHNL_STS_BUF1_ACTIVE BIT(8)176#define CHNL_STS_OFLW_BYTES(n) ((n) << 0)177#define CHNL_STS_OFLW_BYTES_MASK GENMASK(7, 0)178 179/* Channel Scale Factor Register */180#define CHNL_SCALE_FACTOR 0x0018181#define CHNL_SCALE_FACTOR_Y_SCALE(n) ((n) << 16)182#define CHNL_SCALE_FACTOR_Y_SCALE_MASK GENMASK(29, 16)183#define CHNL_SCALE_FACTOR_X_SCALE(n) ((n) << 0)184#define CHNL_SCALE_FACTOR_X_SCALE_MASK GENMASK(13, 0)185 186/* Channel Scale Offset Register */187#define CHNL_SCALE_OFFSET 0x001c188#define CHNL_SCALE_OFFSET_Y_SCALE(n) ((n) << 16)189#define CHNL_SCALE_OFFSET_Y_SCALE_MASK GENMASK(27, 16)190#define CHNL_SCALE_OFFSET_X_SCALE(n) ((n) << 0)191#define CHNL_SCALE_OFFSET_X_SCALE_MASK GENMASK(11, 0)192 193/* Channel Crop Upper Left Corner Coordinate Register */194#define CHNL_CROP_ULC 0x0020195#define CHNL_CROP_ULC_X(n) ((n) << 16)196#define CHNL_CROP_ULC_X_MASK GENMASK(27, 16)197#define CHNL_CROP_ULC_Y(n) ((n) << 0)198#define CHNL_CROP_ULC_Y_MASK GENMASK(11, 0)199 200/* Channel Crop Lower Right Corner Coordinate Register */201#define CHNL_CROP_LRC 0x0024202#define CHNL_CROP_LRC_X(n) ((n) << 16)203#define CHNL_CROP_LRC_X_MASK GENMASK(27, 16)204#define CHNL_CROP_LRC_Y(n) ((n) << 0)205#define CHNL_CROP_LRC_Y_MASK GENMASK(11, 0)206 207/* Channel Color Space Conversion Coefficient Register 0 */208#define CHNL_CSC_COEFF0 0x0028209#define CHNL_CSC_COEFF0_A2(n) ((n) << 16)210#define CHNL_CSC_COEFF0_A2_MASK GENMASK(26, 16)211#define CHNL_CSC_COEFF0_A1(n) ((n) << 0)212#define CHNL_CSC_COEFF0_A1_MASK GENMASK(10, 0)213 214/* Channel Color Space Conversion Coefficient Register 1 */215#define CHNL_CSC_COEFF1 0x002c216#define CHNL_CSC_COEFF1_B1(n) ((n) << 16)217#define CHNL_CSC_COEFF1_B1_MASK GENMASK(26, 16)218#define CHNL_CSC_COEFF1_A3(n) ((n) << 0)219#define CHNL_CSC_COEFF1_A3_MASK GENMASK(10, 0)220 221/* Channel Color Space Conversion Coefficient Register 2 */222#define CHNL_CSC_COEFF2 0x0030223#define CHNL_CSC_COEFF2_B3(n) ((n) << 16)224#define CHNL_CSC_COEFF2_B3_MASK GENMASK(26, 16)225#define CHNL_CSC_COEFF2_B2(n) ((n) << 0)226#define CHNL_CSC_COEFF2_B2_MASK GENMASK(10, 0)227 228/* Channel Color Space Conversion Coefficient Register 3 */229#define CHNL_CSC_COEFF3 0x0034230#define CHNL_CSC_COEFF3_C2(n) ((n) << 16)231#define CHNL_CSC_COEFF3_C2_MASK GENMASK(26, 16)232#define CHNL_CSC_COEFF3_C1(n) ((n) << 0)233#define CHNL_CSC_COEFF3_C1_MASK GENMASK(10, 0)234 235/* Channel Color Space Conversion Coefficient Register 4 */236#define CHNL_CSC_COEFF4 0x0038237#define CHNL_CSC_COEFF4_D1(n) ((n) << 16)238#define CHNL_CSC_COEFF4_D1_MASK GENMASK(24, 16)239#define CHNL_CSC_COEFF4_C3(n) ((n) << 0)240#define CHNL_CSC_COEFF4_C3_MASK GENMASK(10, 0)241 242/* Channel Color Space Conversion Coefficient Register 5 */243#define CHNL_CSC_COEFF5 0x003c244#define CHNL_CSC_COEFF5_D3(n) ((n) << 16)245#define CHNL_CSC_COEFF5_D3_MASK GENMASK(24, 16)246#define CHNL_CSC_COEFF5_D2(n) ((n) << 0)247#define CHNL_CSC_COEFF5_D2_MASK GENMASK(8, 0)248 249/* Channel Alpha Value Register for ROI 0 */250#define CHNL_ROI_0_ALPHA 0x0040251#define CHNL_ROI_0_ALPHA_VAL(n) ((n) << 24)252#define CHNL_ROI_0_ALPHA_MASK GENMASK(31, 24)253#define CHNL_ROI_0_ALPHA_EN BIT(16)254 255/* Channel Upper Left Coordinate Register for ROI 0 */256#define CHNL_ROI_0_ULC 0x0044257#define CHNL_ROI_0_ULC_X(n) ((n) << 16)258#define CHNL_ROI_0_ULC_X_MASK GENMASK(27, 16)259#define CHNL_ROI_0_ULC_Y(n) ((n) << 0)260#define CHNL_ROI_0_ULC_Y_MASK GENMASK(11, 0)261 262/* Channel Lower Right Coordinate Register for ROI 0 */263#define CHNL_ROI_0_LRC 0x0048264#define CHNL_ROI_0_LRC_X(n) ((n) << 16)265#define CHNL_ROI_0_LRC_X_MASK GENMASK(27, 16)266#define CHNL_ROI_0_LRC_Y(n) ((n) << 0)267#define CHNL_ROI_0_LRC_Y_MASK GENMASK(11, 0)268 269/* Channel Alpha Value Register for ROI 1 */270#define CHNL_ROI_1_ALPHA 0x004c271#define CHNL_ROI_1_ALPHA_VAL(n) ((n) << 24)272#define CHNL_ROI_1_ALPHA_MASK GENMASK(31, 24)273#define CHNL_ROI_1_ALPHA_EN BIT(16)274 275/* Channel Upper Left Coordinate Register for ROI 1 */276#define CHNL_ROI_1_ULC 0x0050277#define CHNL_ROI_1_ULC_X(n) ((n) << 16)278#define CHNL_ROI_1_ULC_X_MASK GENMASK(27, 16)279#define CHNL_ROI_1_ULC_Y(n) ((n) << 0)280#define CHNL_ROI_1_ULC_Y_MASK GENMASK(11, 0)281 282/* Channel Lower Right Coordinate Register for ROI 1 */283#define CHNL_ROI_1_LRC 0x0054284#define CHNL_ROI_1_LRC_X(n) ((n) << 16)285#define CHNL_ROI_1_LRC_X_MASK GENMASK(27, 16)286#define CHNL_ROI_1_LRC_Y(n) ((n) << 0)287#define CHNL_ROI_1_LRC_Y_MASK GENMASK(11, 0)288 289/* Channel Alpha Value Register for ROI 2 */290#define CHNL_ROI_2_ALPHA 0x0058291#define CHNL_ROI_2_ALPHA_VAL(n) ((n) << 24)292#define CHNL_ROI_2_ALPHA_MASK GENMASK(31, 24)293#define CHNL_ROI_2_ALPHA_EN BIT(16)294 295/* Channel Upper Left Coordinate Register for ROI 2 */296#define CHNL_ROI_2_ULC 0x005c297#define CHNL_ROI_2_ULC_X(n) ((n) << 16)298#define CHNL_ROI_2_ULC_X_MASK GENMASK(27, 16)299#define CHNL_ROI_2_ULC_Y(n) ((n) << 0)300#define CHNL_ROI_2_ULC_Y_MASK GENMASK(11, 0)301 302/* Channel Lower Right Coordinate Register for ROI 2 */303#define CHNL_ROI_2_LRC 0x0060304#define CHNL_ROI_2_LRC_X(n) ((n) << 16)305#define CHNL_ROI_2_LRC_X_MASK GENMASK(27, 16)306#define CHNL_ROI_2_LRC_Y(n) ((n) << 0)307#define CHNL_ROI_2_LRC_Y_MASK GENMASK(11, 0)308 309/* Channel Alpha Value Register for ROI 3 */310#define CHNL_ROI_3_ALPHA 0x0064311#define CHNL_ROI_3_ALPHA_VAL(n) ((n) << 24)312#define CHNL_ROI_3_ALPHA_MASK GENMASK(31, 24)313#define CHNL_ROI_3_ALPHA_EN BIT(16)314 315/* Channel Upper Left Coordinate Register for ROI 3 */316#define CHNL_ROI_3_ULC 0x0068317#define CHNL_ROI_3_ULC_X(n) ((n) << 16)318#define CHNL_ROI_3_ULC_X_MASK GENMASK(27, 16)319#define CHNL_ROI_3_ULC_Y(n) ((n) << 0)320#define CHNL_ROI_3_ULC_Y_MASK GENMASK(11, 0)321 322/* Channel Lower Right Coordinate Register for ROI 3 */323#define CHNL_ROI_3_LRC 0x006c324#define CHNL_ROI_3_LRC_X(n) ((n) << 16)325#define CHNL_ROI_3_LRC_X_MASK GENMASK(27, 16)326#define CHNL_ROI_3_LRC_Y(n) ((n) << 0)327#define CHNL_ROI_3_LRC_Y_MASK GENMASK(11, 0)328/* Channel RGB or Luma (Y) Output Buffer 1 Address */329#define CHNL_OUT_BUF1_ADDR_Y 0x0070330 331/* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */332#define CHNL_OUT_BUF1_ADDR_U 0x0074333 334/* Channel Chroma (V/Cr) Output Buffer 1 Address */335#define CHNL_OUT_BUF1_ADDR_V 0x0078336 337/* Channel Output Buffer Pitch */338#define CHNL_OUT_BUF_PITCH 0x007c339#define CHNL_OUT_BUF_PITCH_LINE_PITCH(n) ((n) << 0)340#define CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0)341 342/* Channel Input Buffer Address */343#define CHNL_IN_BUF_ADDR 0x0080344 345/* Channel Input Buffer Pitch */346#define CHNL_IN_BUF_PITCH 0x0084347#define CHNL_IN_BUF_PITCH_FRM_PITCH(n) ((n) << 16)348#define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK GENMASK(31, 16)349#define CHNL_IN_BUF_PITCH_LINE_PITCH(n) ((n) << 0)350#define CHNL_IN_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0)351 352/* Channel Memory Read Control */353#define CHNL_MEM_RD_CTRL 0x0088354#define CHNL_MEM_RD_CTRL_IMG_TYPE(n) ((n) << 28)355#define CHNL_MEM_RD_CTRL_IMG_TYPE_MASK GENMASK(31, 28)356#define CHNL_MEM_RD_CTRL_IMG_TYPE_BGR8P 0x00357#define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB8P 0x01358#define CHNL_MEM_RD_CTRL_IMG_TYPE_XRGB8 0x02359#define CHNL_MEM_RD_CTRL_IMG_TYPE_RGBX8 0x03360#define CHNL_MEM_RD_CTRL_IMG_TYPE_XBGR8 0x04361#define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB565 0x05362#define CHNL_MEM_RD_CTRL_IMG_TYPE_A2BGR10 0x06363#define CHNL_MEM_RD_CTRL_IMG_TYPE_A2RGB10 0x07364#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8P 0x08365#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10 0x09366#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10P 0x0a367#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P12 0x0b368#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8 0x0c369#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P8P 0x0d370#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P10 0x0e371#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P12 0x0f372#define CHNL_MEM_RD_CTRL_READ_MEM BIT(0)373 374/* Channel RGB or Luma (Y) Output Buffer 2 Address */375#define CHNL_OUT_BUF2_ADDR_Y 0x008c376 377/* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */378#define CHNL_OUT_BUF2_ADDR_U 0x0090379 380/* Channel Chroma (V/Cr) Output Buffer 2 Address */381#define CHNL_OUT_BUF2_ADDR_V 0x0094382 383/* Channel scale image config */384#define CHNL_SCL_IMG_CFG 0x0098385#define CHNL_SCL_IMG_CFG_HEIGHT(n) ((n) << 16)386#define CHNL_SCL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)387#define CHNL_SCL_IMG_CFG_WIDTH(n) ((n) << 0)388#define CHNL_SCL_IMG_CFG_WIDTH_MASK GENMASK(12, 0)389 390/* Channel Flow Control Register */391#define CHNL_FLOW_CTRL 0x009c392#define CHNL_FLOW_CTRL_FC_DENOM_MASK GENMASK(7, 0)393#define CHNL_FLOW_CTRL_FC_DENOM(n) ((n) << 0)394#define CHNL_FLOW_CTRL_FC_NUMER_MASK GENMASK(23, 16)395#define CHNL_FLOW_CTRL_FC_NUMER(n) ((n) << 0)396 397/* Channel Output Y-Buffer 1 Extended Address Bits */398#define CHNL_Y_BUF1_XTND_ADDR 0x00a0399 400/* Channel Output U-Buffer 1 Extended Address Bits */401#define CHNL_U_BUF1_XTND_ADDR 0x00a4402 403/* Channel Output V-Buffer 1 Extended Address Bits */404#define CHNL_V_BUF1_XTND_ADDR 0x00a8405 406/* Channel Output Y-Buffer 2 Extended Address Bits */407#define CHNL_Y_BUF2_XTND_ADDR 0x00ac408 409/* Channel Output U-Buffer 2 Extended Address Bits */410#define CHNL_U_BUF2_XTND_ADDR 0x00b0411 412/* Channel Output V-Buffer 2 Extended Address Bits */413#define CHNL_V_BUF2_XTND_ADDR 0x00b4414 415/* Channel Input Buffer Extended Address Bits */416#define CHNL_IN_BUF_XTND_ADDR 0x00b8417 418#endif /* __IMX8_ISI_REGS_H__ */419