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1// SPDX-License-Identifier: GPL-2.02/*3 * camss-csiphy-2ph-1-0.c4 *5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 2phase v1.06 *7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.8 * Copyright (C) 2016-2018 Linaro Ltd.9 */10 11#include "camss-csiphy.h"12 13#include <linux/delay.h>14#include <linux/interrupt.h>15#include <linux/io.h>16 17#define CAMSS_CSI_PHY_LNn_CFG2(n) (0x004 + 0x40 * (n))18#define CAMSS_CSI_PHY_LNn_CFG3(n) (0x008 + 0x40 * (n))19#define CAMSS_CSI_PHY_LN_CLK 120#define CAMSS_CSI_PHY_GLBL_RESET 0x14021#define CAMSS_CSI_PHY_GLBL_PWR_CFG 0x14422#define CAMSS_CSI_PHY_GLBL_IRQ_CMD 0x16423#define CAMSS_CSI_PHY_HW_VERSION 0x18824#define CAMSS_CSI_PHY_INTERRUPT_STATUSn(n) (0x18c + 0x4 * (n))25#define CAMSS_CSI_PHY_INTERRUPT_MASKn(n) (0x1ac + 0x4 * (n))26#define CAMSS_CSI_PHY_INTERRUPT_CLEARn(n) (0x1cc + 0x4 * (n))27#define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0 0x1ec28#define CAMSS_CSI_PHY_T_WAKEUP_CFG0 0x1f429 30static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg)31{32 u8 lane_mask;33 int i;34 35 lane_mask = 1 << CAMSS_CSI_PHY_LN_CLK;36 37 for (i = 0; i < lane_cfg->num_data; i++)38 lane_mask |= 1 << lane_cfg->data[i].pos;39 40 return lane_mask;41}42 43static void csiphy_hw_version_read(struct csiphy_device *csiphy,44 struct device *dev)45{46 u8 hw_version = readl_relaxed(csiphy->base +47 CAMSS_CSI_PHY_HW_VERSION);48 49 dev_dbg(dev, "CSIPHY HW Version = 0x%02x\n", hw_version);50}51 52/*53 * csiphy_reset - Perform software reset on CSIPHY module54 * @csiphy: CSIPHY device55 */56static void csiphy_reset(struct csiphy_device *csiphy)57{58 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);59 usleep_range(5000, 8000);60 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);61}62 63/*64 * csiphy_settle_cnt_calc - Calculate settle count value65 *66 * Helper function to calculate settle count value. This is67 * based on the CSI2 T_hs_settle parameter which in turn68 * is calculated based on the CSI2 transmitter link frequency.69 *70 * Return settle count value or 0 if the CSI2 link frequency71 * is not available72 */73static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate)74{75 u32 ui; /* ps */76 u32 timer_period; /* ps */77 u32 t_hs_prepare_max; /* ps */78 u32 t_hs_prepare_zero_min; /* ps */79 u32 t_hs_settle; /* ps */80 u8 settle_cnt;81 82 if (link_freq <= 0)83 return 0;84 85 ui = div_u64(1000000000000LL, link_freq);86 ui /= 2;87 t_hs_prepare_max = 85000 + 6 * ui;88 t_hs_prepare_zero_min = 145000 + 10 * ui;89 t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2;90 91 timer_period = div_u64(1000000000000LL, timer_clk_rate);92 settle_cnt = t_hs_settle / timer_period - 1;93 94 return settle_cnt;95}96 97static void csiphy_lanes_enable(struct csiphy_device *csiphy,98 struct csiphy_config *cfg,99 s64 link_freq, u8 lane_mask)100{101 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;102 u8 settle_cnt;103 u8 val, l = 0;104 int i = 0;105 106 settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);107 108 writel_relaxed(0x1, csiphy->base +109 CAMSS_CSI_PHY_GLBL_T_INIT_CFG0);110 writel_relaxed(0x1, csiphy->base +111 CAMSS_CSI_PHY_T_WAKEUP_CFG0);112 113 val = 0x1;114 val |= lane_mask << 1;115 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);116 117 val = cfg->combo_mode << 4;118 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);119 120 for (i = 0; i <= c->num_data; i++) {121 if (i == c->num_data)122 l = CAMSS_CSI_PHY_LN_CLK;123 else124 l = c->data[i].pos;125 126 writel_relaxed(0x10, csiphy->base +127 CAMSS_CSI_PHY_LNn_CFG2(l));128 writel_relaxed(settle_cnt, csiphy->base +129 CAMSS_CSI_PHY_LNn_CFG3(l));130 writel_relaxed(0x3f, csiphy->base +131 CAMSS_CSI_PHY_INTERRUPT_MASKn(l));132 writel_relaxed(0x3f, csiphy->base +133 CAMSS_CSI_PHY_INTERRUPT_CLEARn(l));134 }135}136 137static void csiphy_lanes_disable(struct csiphy_device *csiphy,138 struct csiphy_config *cfg)139{140 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;141 u8 l = 0;142 int i = 0;143 144 for (i = 0; i <= c->num_data; i++) {145 if (i == c->num_data)146 l = CAMSS_CSI_PHY_LN_CLK;147 else148 l = c->data[i].pos;149 150 writel_relaxed(0x0, csiphy->base +151 CAMSS_CSI_PHY_LNn_CFG2(l));152 }153 154 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);155}156 157/*158 * csiphy_isr - CSIPHY module interrupt handler159 * @irq: Interrupt line160 * @dev: CSIPHY device161 *162 * Return IRQ_HANDLED on success163 */164static irqreturn_t csiphy_isr(int irq, void *dev)165{166 struct csiphy_device *csiphy = dev;167 u8 i;168 169 for (i = 0; i < 8; i++) {170 u8 val = readl_relaxed(csiphy->base +171 CAMSS_CSI_PHY_INTERRUPT_STATUSn(i));172 writel_relaxed(val, csiphy->base +173 CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));174 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);175 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);176 writel_relaxed(0x0, csiphy->base +177 CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));178 }179 180 return IRQ_HANDLED;181}182 183const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = {184 .get_lane_mask = csiphy_get_lane_mask,185 .hw_version_read = csiphy_hw_version_read,186 .reset = csiphy_reset,187 .lanes_enable = csiphy_lanes_enable,188 .lanes_disable = csiphy_lanes_disable,189 .isr = csiphy_isr,190};191