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1// SPDX-License-Identifier: GPL-2.02/*3 * camss-ispif.c4 *5 * Qualcomm MSM Camera Subsystem - ISPIF (ISP Interface) Module6 *7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.8 * Copyright (C) 2015-2018 Linaro Ltd.9 */10#include <linux/clk.h>11#include <linux/completion.h>12#include <linux/interrupt.h>13#include <linux/io.h>14#include <linux/iopoll.h>15#include <linux/kernel.h>16#include <linux/mutex.h>17#include <linux/platform_device.h>18#include <linux/pm_runtime.h>19#include <media/media-entity.h>20#include <media/v4l2-device.h>21#include <media/v4l2-subdev.h>22 23#include "camss-ispif.h"24#include "camss.h"25 26#define MSM_ISPIF_NAME "msm_ispif"27 28#define ISPIF_RST_CMD_0 0x00829#define ISPIF_RST_CMD_1 0x00c30#define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)31#define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)32#define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)33#define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)34#define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)35#define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)36#define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)37#define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)38#define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)39#define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)40#define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)41#define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)42#define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)43#define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)44#define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)45#define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)46#define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)47#define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c48#define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))49#define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)50#define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))51#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x0000124952#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff53#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x0249200054#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe00055#define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))56#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x0000124957#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff58#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x0249200059#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe00060#define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))61#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x0000124962#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff63#define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))64#define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)65#define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)66#define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))67#define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)68#define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)69#define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))70#define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)71#define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))72#define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))73#define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))74#define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))75#define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))76#define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))77#define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \78 (0x254 + 0x200 * (m) + 0x4 * (n))79#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \80 (0x264 + 0x200 * (m) + 0x4 * (n))81/* PACK_CFG registers are 8x96 only */82#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \83 (0x270 + 0x200 * (m) + 0x4 * (n))84#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \85 (0x27c + 0x200 * (m) + 0x4 * (n))86#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \87 (1 << ((cid % 8) * 4))88#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \89 (0x2c0 + 0x200 * (m) + 0x4 * (n))90#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \91 (0x2d0 + 0x200 * (m) + 0x4 * (n))92 93#define CSI_PIX_CLK_MUX_SEL 0x00094#define CSI_RDI_CLK_MUX_SEL 0x00895 96#define ISPIF_TIMEOUT_SLEEP_US 100097#define ISPIF_TIMEOUT_ALL_US 100000098#define ISPIF_RESET_TIMEOUT_MS 50099 100enum ispif_intf_cmd {101 CMD_DISABLE_FRAME_BOUNDARY = 0x0,102 CMD_ENABLE_FRAME_BOUNDARY = 0x1,103 CMD_DISABLE_IMMEDIATELY = 0x2,104 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,105 CMD_ALL_NO_CHANGE = 0xffffffff,106};107 108static const u32 ispif_formats_8x16[] = {109 MEDIA_BUS_FMT_UYVY8_1X16,110 MEDIA_BUS_FMT_VYUY8_1X16,111 MEDIA_BUS_FMT_YUYV8_1X16,112 MEDIA_BUS_FMT_YVYU8_1X16,113 MEDIA_BUS_FMT_SBGGR8_1X8,114 MEDIA_BUS_FMT_SGBRG8_1X8,115 MEDIA_BUS_FMT_SGRBG8_1X8,116 MEDIA_BUS_FMT_SRGGB8_1X8,117 MEDIA_BUS_FMT_SBGGR10_1X10,118 MEDIA_BUS_FMT_SGBRG10_1X10,119 MEDIA_BUS_FMT_SGRBG10_1X10,120 MEDIA_BUS_FMT_SRGGB10_1X10,121 MEDIA_BUS_FMT_SBGGR12_1X12,122 MEDIA_BUS_FMT_SGBRG12_1X12,123 MEDIA_BUS_FMT_SGRBG12_1X12,124 MEDIA_BUS_FMT_SRGGB12_1X12,125 MEDIA_BUS_FMT_Y10_1X10,126};127 128static const u32 ispif_formats_8x96[] = {129 MEDIA_BUS_FMT_UYVY8_1X16,130 MEDIA_BUS_FMT_VYUY8_1X16,131 MEDIA_BUS_FMT_YUYV8_1X16,132 MEDIA_BUS_FMT_YVYU8_1X16,133 MEDIA_BUS_FMT_SBGGR8_1X8,134 MEDIA_BUS_FMT_SGBRG8_1X8,135 MEDIA_BUS_FMT_SGRBG8_1X8,136 MEDIA_BUS_FMT_SRGGB8_1X8,137 MEDIA_BUS_FMT_SBGGR10_1X10,138 MEDIA_BUS_FMT_SGBRG10_1X10,139 MEDIA_BUS_FMT_SGRBG10_1X10,140 MEDIA_BUS_FMT_SRGGB10_1X10,141 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,142 MEDIA_BUS_FMT_SBGGR12_1X12,143 MEDIA_BUS_FMT_SGBRG12_1X12,144 MEDIA_BUS_FMT_SGRBG12_1X12,145 MEDIA_BUS_FMT_SRGGB12_1X12,146 MEDIA_BUS_FMT_SBGGR14_1X14,147 MEDIA_BUS_FMT_SGBRG14_1X14,148 MEDIA_BUS_FMT_SGRBG14_1X14,149 MEDIA_BUS_FMT_SRGGB14_1X14,150 MEDIA_BUS_FMT_Y10_1X10,151 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,152};153 154/*155 * ispif_isr_8x96 - ISPIF module interrupt handler for 8x96156 * @irq: Interrupt line157 * @dev: ISPIF device158 *159 * Return IRQ_HANDLED on success160 */161static irqreturn_t ispif_isr_8x96(int irq, void *dev)162{163 struct ispif_device *ispif = dev;164 struct camss *camss = ispif->camss;165 u32 value0, value1, value2, value3, value4, value5;166 167 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));168 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));169 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));170 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));171 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));172 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));173 174 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));175 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));176 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));177 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));178 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));179 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));180 181 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);182 183 if ((value0 >> 27) & 0x1)184 complete(&ispif->reset_complete[0]);185 186 if ((value3 >> 27) & 0x1)187 complete(&ispif->reset_complete[1]);188 189 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))190 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");191 192 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))193 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");194 195 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))196 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");197 198 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))199 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");200 201 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))202 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");203 204 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))205 dev_err_ratelimited(camss->dev, "VFE1 pix0 overflow\n");206 207 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))208 dev_err_ratelimited(camss->dev, "VFE1 rdi0 overflow\n");209 210 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))211 dev_err_ratelimited(camss->dev, "VFE1 pix1 overflow\n");212 213 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))214 dev_err_ratelimited(camss->dev, "VFE1 rdi1 overflow\n");215 216 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))217 dev_err_ratelimited(camss->dev, "VFE1 rdi2 overflow\n");218 219 return IRQ_HANDLED;220}221 222/*223 * ispif_isr_8x16 - ISPIF module interrupt handler for 8x16224 * @irq: Interrupt line225 * @dev: ISPIF device226 *227 * Return IRQ_HANDLED on success228 */229static irqreturn_t ispif_isr_8x16(int irq, void *dev)230{231 struct ispif_device *ispif = dev;232 struct camss *camss = ispif->camss;233 u32 value0, value1, value2;234 235 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));236 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));237 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));238 239 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));240 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));241 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));242 243 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);244 245 if ((value0 >> 27) & 0x1)246 complete(&ispif->reset_complete[0]);247 248 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))249 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");250 251 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))252 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");253 254 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))255 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");256 257 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))258 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");259 260 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))261 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");262 263 return IRQ_HANDLED;264}265 266static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)267{268 struct camss *camss = ispif->camss;269 270 unsigned long time;271 u32 val;272 273 if (vfe_id >= camss->res->vfe_num) {274 dev_err(camss->dev,275 "Error: asked reset for invalid VFE%d\n", vfe_id);276 return -ENOENT;277 }278 279 reinit_completion(&ispif->reset_complete[vfe_id]);280 281 val = ISPIF_RST_CMD_0_STROBED_RST_EN |282 ISPIF_RST_CMD_0_MISC_LOGIC_RST |283 ISPIF_RST_CMD_0_SW_REG_RST |284 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |285 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |286 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |287 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |288 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |289 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |290 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |291 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |292 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |293 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |294 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |295 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |296 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |297 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;298 299 if (vfe_id == 1)300 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);301 else302 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);303 304 time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id],305 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));306 if (!time) {307 dev_err(camss->dev,308 "ISPIF for VFE%d reset timeout\n", vfe_id);309 return -EIO;310 }311 312 return 0;313}314 315/*316 * ispif_reset - Trigger reset on ISPIF module and wait to complete317 * @ispif: ISPIF device318 *319 * Return 0 on success or a negative error code otherwise320 */321static int ispif_reset(struct ispif_device *ispif, u8 vfe_id)322{323 struct camss *camss = ispif->camss;324 int ret;325 326 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE0);327 if (ret < 0)328 return ret;329 330 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE1);331 if (ret < 0)332 return ret;333 334 ret = camss_enable_clocks(ispif->nclocks_for_reset,335 ispif->clock_for_reset,336 camss->dev);337 if (ret < 0)338 return ret;339 340 ret = ispif_vfe_reset(ispif, vfe_id);341 if (ret)342 dev_dbg(camss->dev, "ISPIF Reset failed\n");343 344 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);345 346 camss_pm_domain_off(camss, PM_DOMAIN_VFE0);347 camss_pm_domain_off(camss, PM_DOMAIN_VFE1);348 349 return ret;350}351 352/*353 * ispif_set_power - Power on/off ISPIF module354 * @sd: ISPIF V4L2 subdevice355 * @on: Requested power state356 *357 * Return 0 on success or a negative error code otherwise358 */359static int ispif_set_power(struct v4l2_subdev *sd, int on)360{361 struct ispif_line *line = v4l2_get_subdevdata(sd);362 struct ispif_device *ispif = line->ispif;363 struct device *dev = ispif->camss->dev;364 int ret = 0;365 366 mutex_lock(&ispif->power_lock);367 368 if (on) {369 if (ispif->power_count) {370 /* Power is already on */371 ispif->power_count++;372 goto exit;373 }374 375 ret = pm_runtime_resume_and_get(dev);376 if (ret < 0)377 goto exit;378 379 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);380 if (ret < 0) {381 pm_runtime_put_sync(dev);382 goto exit;383 }384 385 ret = ispif_reset(ispif, line->vfe_id);386 if (ret < 0) {387 pm_runtime_put_sync(dev);388 camss_disable_clocks(ispif->nclocks, ispif->clock);389 goto exit;390 }391 392 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;393 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;394 395 ispif->power_count++;396 } else {397 if (ispif->power_count == 0) {398 dev_err(dev, "ispif power off on power_count == 0\n");399 goto exit;400 } else if (ispif->power_count == 1) {401 camss_disable_clocks(ispif->nclocks, ispif->clock);402 pm_runtime_put_sync(dev);403 }404 405 ispif->power_count--;406 }407 408exit:409 mutex_unlock(&ispif->power_lock);410 411 return ret;412}413 414/*415 * ispif_select_clk_mux - Select clock for PIX/RDI interface416 * @ispif: ISPIF device417 * @intf: VFE interface418 * @csid: CSID HW module id419 * @vfe: VFE HW module id420 * @enable: enable or disable the selected clock421 */422static void ispif_select_clk_mux(struct ispif_device *ispif,423 enum ispif_intf intf, u8 csid,424 u8 vfe, u8 enable)425{426 u32 val;427 428 switch (intf) {429 case PIX0:430 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);431 val &= ~(0xf << (vfe * 8));432 if (enable)433 val |= (csid << (vfe * 8));434 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);435 break;436 437 case RDI0:438 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);439 val &= ~(0xf << (vfe * 12));440 if (enable)441 val |= (csid << (vfe * 12));442 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);443 break;444 445 case PIX1:446 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);447 val &= ~(0xf << (4 + (vfe * 8)));448 if (enable)449 val |= (csid << (4 + (vfe * 8)));450 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);451 break;452 453 case RDI1:454 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);455 val &= ~(0xf << (4 + (vfe * 12)));456 if (enable)457 val |= (csid << (4 + (vfe * 12)));458 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);459 break;460 461 case RDI2:462 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);463 val &= ~(0xf << (8 + (vfe * 12)));464 if (enable)465 val |= (csid << (8 + (vfe * 12)));466 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);467 break;468 }469 470 mb();471}472 473/*474 * ispif_validate_intf_status - Validate current status of PIX/RDI interface475 * @ispif: ISPIF device476 * @intf: VFE interface477 * @vfe: VFE HW module id478 *479 * Return 0 when interface is idle or -EBUSY otherwise480 */481static int ispif_validate_intf_status(struct ispif_device *ispif,482 enum ispif_intf intf, u8 vfe)483{484 int ret = 0;485 u32 val = 0;486 487 switch (intf) {488 case PIX0:489 val = readl_relaxed(ispif->base +490 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));491 break;492 case RDI0:493 val = readl_relaxed(ispif->base +494 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));495 break;496 case PIX1:497 val = readl_relaxed(ispif->base +498 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));499 break;500 case RDI1:501 val = readl_relaxed(ispif->base +502 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));503 break;504 case RDI2:505 val = readl_relaxed(ispif->base +506 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));507 break;508 }509 510 if ((val & 0xf) != 0xf) {511 dev_err(ispif->camss->dev, "%s: ispif is busy: 0x%x\n",512 __func__, val);513 ret = -EBUSY;514 }515 516 return ret;517}518 519/*520 * ispif_wait_for_stop - Wait for PIX/RDI interface to stop521 * @ispif: ISPIF device522 * @intf: VFE interface523 * @vfe: VFE HW module id524 *525 * Return 0 on success or a negative error code otherwise526 */527static int ispif_wait_for_stop(struct ispif_device *ispif,528 enum ispif_intf intf, u8 vfe)529{530 u32 addr = 0;531 u32 stop_flag = 0;532 int ret;533 534 switch (intf) {535 case PIX0:536 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);537 break;538 case RDI0:539 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);540 break;541 case PIX1:542 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);543 break;544 case RDI1:545 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);546 break;547 case RDI2:548 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);549 break;550 }551 552 ret = readl_poll_timeout(ispif->base + addr,553 stop_flag,554 (stop_flag & 0xf) == 0xf,555 ISPIF_TIMEOUT_SLEEP_US,556 ISPIF_TIMEOUT_ALL_US);557 if (ret < 0)558 dev_err(ispif->camss->dev, "%s: ispif stop timeout\n",559 __func__);560 561 return ret;562}563 564/*565 * ispif_select_csid - Select CSID HW module for input from566 * @ispif: ISPIF device567 * @intf: VFE interface568 * @csid: CSID HW module id569 * @vfe: VFE HW module id570 * @enable: enable or disable the selected input571 */572static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,573 u8 csid, u8 vfe, u8 enable)574{575 u32 val;576 577 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));578 switch (intf) {579 case PIX0:580 val &= ~(BIT(1) | BIT(0));581 if (enable)582 val |= csid;583 break;584 case RDI0:585 val &= ~(BIT(5) | BIT(4));586 if (enable)587 val |= (csid << 4);588 break;589 case PIX1:590 val &= ~(BIT(9) | BIT(8));591 if (enable)592 val |= (csid << 8);593 break;594 case RDI1:595 val &= ~(BIT(13) | BIT(12));596 if (enable)597 val |= (csid << 12);598 break;599 case RDI2:600 val &= ~(BIT(21) | BIT(20));601 if (enable)602 val |= (csid << 20);603 break;604 }605 606 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));607}608 609/*610 * ispif_select_cid - Enable/disable desired CID611 * @ispif: ISPIF device612 * @intf: VFE interface613 * @cid: desired CID to enable/disable614 * @vfe: VFE HW module id615 * @enable: enable or disable the desired CID616 */617static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,618 u8 cid, u8 vfe, u8 enable)619{620 u32 cid_mask = 1 << cid;621 u32 addr = 0;622 u32 val;623 624 switch (intf) {625 case PIX0:626 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);627 break;628 case RDI0:629 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);630 break;631 case PIX1:632 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);633 break;634 case RDI1:635 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);636 break;637 case RDI2:638 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);639 break;640 }641 642 val = readl_relaxed(ispif->base + addr);643 if (enable)644 val |= cid_mask;645 else646 val &= ~cid_mask;647 648 writel(val, ispif->base + addr);649}650 651/*652 * ispif_config_irq - Enable/disable interrupts for PIX/RDI interface653 * @ispif: ISPIF device654 * @intf: VFE interface655 * @vfe: VFE HW module id656 * @enable: enable or disable657 */658static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,659 u8 vfe, u8 enable)660{661 u32 val;662 663 switch (intf) {664 case PIX0:665 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));666 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;667 if (enable)668 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;669 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));670 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,671 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));672 break;673 case RDI0:674 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));675 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;676 if (enable)677 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;678 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));679 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,680 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));681 break;682 case PIX1:683 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));684 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;685 if (enable)686 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;687 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));688 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,689 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));690 break;691 case RDI1:692 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));693 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;694 if (enable)695 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;696 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));697 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,698 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));699 break;700 case RDI2:701 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));702 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;703 if (enable)704 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;705 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));706 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,707 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));708 break;709 }710 711 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);712}713 714/*715 * ispif_config_pack - Config packing for PRDI mode716 * @ispif: ISPIF device717 * @code: media bus format code718 * @intf: VFE interface719 * @cid: desired CID to handle720 * @vfe: VFE HW module id721 * @enable: enable or disable722 */723static void ispif_config_pack(struct ispif_device *ispif, u32 code,724 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)725{726 u32 addr, val;727 728 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&729 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)730 return;731 732 switch (intf) {733 case RDI0:734 if (cid < 8)735 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);736 else737 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);738 break;739 case RDI1:740 if (cid < 8)741 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);742 else743 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);744 break;745 case RDI2:746 if (cid < 8)747 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);748 else749 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);750 break;751 default:752 return;753 }754 755 if (enable)756 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);757 else758 val = 0;759 760 writel_relaxed(val, ispif->base + addr);761}762 763/*764 * ispif_set_intf_cmd - Set command to enable/disable interface765 * @ispif: ISPIF device766 * @cmd: interface command767 * @intf: VFE interface768 * @vfe: VFE HW module id769 * @vc: virtual channel770 */771static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,772 enum ispif_intf intf, u8 vfe, u8 vc)773{774 u32 *val;775 776 if (intf == RDI2) {777 val = &ispif->intf_cmd[vfe].cmd_1;778 *val &= ~(0x3 << (vc * 2 + 8));779 *val |= (cmd << (vc * 2 + 8));780 wmb();781 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));782 wmb();783 } else {784 val = &ispif->intf_cmd[vfe].cmd_0;785 *val &= ~(0x3 << (vc * 2 + intf * 8));786 *val |= (cmd << (vc * 2 + intf * 8));787 wmb();788 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));789 wmb();790 }791}792 793/*794 * ispif_set_stream - Enable/disable streaming on ISPIF module795 * @sd: ISPIF V4L2 subdevice796 * @enable: Requested streaming state797 *798 * Main configuration of ISPIF module is also done here.799 *800 * Return 0 on success or a negative error code otherwise801 */802static int ispif_set_stream(struct v4l2_subdev *sd, int enable)803{804 struct ispif_line *line = v4l2_get_subdevdata(sd);805 struct ispif_device *ispif = line->ispif;806 struct camss *camss = ispif->camss;807 enum ispif_intf intf = line->interface;808 u8 csid = line->csid_id;809 u8 vfe = line->vfe_id;810 u8 vc = 0; /* Virtual Channel 0 */811 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */812 int ret;813 814 if (enable) {815 if (!media_pad_remote_pad_first(&line->pads[MSM_ISPIF_PAD_SINK]))816 return -ENOLINK;817 818 /* Config */819 820 mutex_lock(&ispif->config_lock);821 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);822 823 ret = ispif_validate_intf_status(ispif, intf, vfe);824 if (ret < 0) {825 mutex_unlock(&ispif->config_lock);826 return ret;827 }828 829 ispif_select_csid(ispif, intf, csid, vfe, 1);830 ispif_select_cid(ispif, intf, cid, vfe, 1);831 ispif_config_irq(ispif, intf, vfe, 1);832 if (camss->res->version == CAMSS_8x96 ||833 camss->res->version == CAMSS_660)834 ispif_config_pack(ispif,835 line->fmt[MSM_ISPIF_PAD_SINK].code,836 intf, cid, vfe, 1);837 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,838 intf, vfe, vc);839 } else {840 mutex_lock(&ispif->config_lock);841 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,842 intf, vfe, vc);843 mutex_unlock(&ispif->config_lock);844 845 ret = ispif_wait_for_stop(ispif, intf, vfe);846 if (ret < 0)847 return ret;848 849 mutex_lock(&ispif->config_lock);850 if (camss->res->version == CAMSS_8x96 ||851 camss->res->version == CAMSS_660)852 ispif_config_pack(ispif,853 line->fmt[MSM_ISPIF_PAD_SINK].code,854 intf, cid, vfe, 0);855 ispif_config_irq(ispif, intf, vfe, 0);856 ispif_select_cid(ispif, intf, cid, vfe, 0);857 ispif_select_csid(ispif, intf, csid, vfe, 0);858 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);859 }860 861 mutex_unlock(&ispif->config_lock);862 863 return 0;864}865 866/*867 * __ispif_get_format - Get pointer to format structure868 * @ispif: ISPIF line869 * @sd_state: V4L2 subdev state870 * @pad: pad from which format is requested871 * @which: TRY or ACTIVE format872 *873 * Return pointer to TRY or ACTIVE format structure874 */875static struct v4l2_mbus_framefmt *876__ispif_get_format(struct ispif_line *line,877 struct v4l2_subdev_state *sd_state,878 unsigned int pad,879 enum v4l2_subdev_format_whence which)880{881 if (which == V4L2_SUBDEV_FORMAT_TRY)882 return v4l2_subdev_state_get_format(sd_state, pad);883 884 return &line->fmt[pad];885}886 887/*888 * ispif_try_format - Handle try format by pad subdev method889 * @ispif: ISPIF line890 * @sd_state: V4L2 subdev state891 * @pad: pad on which format is requested892 * @fmt: pointer to v4l2 format structure893 * @which: wanted subdev format894 */895static void ispif_try_format(struct ispif_line *line,896 struct v4l2_subdev_state *sd_state,897 unsigned int pad,898 struct v4l2_mbus_framefmt *fmt,899 enum v4l2_subdev_format_whence which)900{901 unsigned int i;902 903 switch (pad) {904 case MSM_ISPIF_PAD_SINK:905 /* Set format on sink pad */906 907 for (i = 0; i < line->nformats; i++)908 if (fmt->code == line->formats[i])909 break;910 911 /* If not found, use UYVY as default */912 if (i >= line->nformats)913 fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;914 915 fmt->width = clamp_t(u32, fmt->width, 1, 8191);916 fmt->height = clamp_t(u32, fmt->height, 1, 8191);917 918 fmt->field = V4L2_FIELD_NONE;919 fmt->colorspace = V4L2_COLORSPACE_SRGB;920 921 break;922 923 case MSM_ISPIF_PAD_SRC:924 /* Set and return a format same as sink pad */925 926 *fmt = *__ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SINK,927 which);928 929 break;930 }931 932 fmt->colorspace = V4L2_COLORSPACE_SRGB;933}934 935/*936 * ispif_enum_mbus_code - Handle pixel format enumeration937 * @sd: ISPIF V4L2 subdevice938 * @sd_state: V4L2 subdev state939 * @code: pointer to v4l2_subdev_mbus_code_enum structure940 * return -EINVAL or zero on success941 */942static int ispif_enum_mbus_code(struct v4l2_subdev *sd,943 struct v4l2_subdev_state *sd_state,944 struct v4l2_subdev_mbus_code_enum *code)945{946 struct ispif_line *line = v4l2_get_subdevdata(sd);947 struct v4l2_mbus_framefmt *format;948 949 if (code->pad == MSM_ISPIF_PAD_SINK) {950 if (code->index >= line->nformats)951 return -EINVAL;952 953 code->code = line->formats[code->index];954 } else {955 if (code->index > 0)956 return -EINVAL;957 958 format = __ispif_get_format(line, sd_state,959 MSM_ISPIF_PAD_SINK,960 code->which);961 962 code->code = format->code;963 }964 965 return 0;966}967 968/*969 * ispif_enum_frame_size - Handle frame size enumeration970 * @sd: ISPIF V4L2 subdevice971 * @sd_state: V4L2 subdev state972 * @fse: pointer to v4l2_subdev_frame_size_enum structure973 * return -EINVAL or zero on success974 */975static int ispif_enum_frame_size(struct v4l2_subdev *sd,976 struct v4l2_subdev_state *sd_state,977 struct v4l2_subdev_frame_size_enum *fse)978{979 struct ispif_line *line = v4l2_get_subdevdata(sd);980 struct v4l2_mbus_framefmt format;981 982 if (fse->index != 0)983 return -EINVAL;984 985 format.code = fse->code;986 format.width = 1;987 format.height = 1;988 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);989 fse->min_width = format.width;990 fse->min_height = format.height;991 992 if (format.code != fse->code)993 return -EINVAL;994 995 format.code = fse->code;996 format.width = -1;997 format.height = -1;998 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);999 fse->max_width = format.width;1000 fse->max_height = format.height;1001 1002 return 0;1003}1004 1005/*1006 * ispif_get_format - Handle get format by pads subdev method1007 * @sd: ISPIF V4L2 subdevice1008 * @sd_state: V4L2 subdev state1009 * @fmt: pointer to v4l2 subdev format structure1010 *1011 * Return -EINVAL or zero on success1012 */1013static int ispif_get_format(struct v4l2_subdev *sd,1014 struct v4l2_subdev_state *sd_state,1015 struct v4l2_subdev_format *fmt)1016{1017 struct ispif_line *line = v4l2_get_subdevdata(sd);1018 struct v4l2_mbus_framefmt *format;1019 1020 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);1021 if (format == NULL)1022 return -EINVAL;1023 1024 fmt->format = *format;1025 1026 return 0;1027}1028 1029/*1030 * ispif_set_format - Handle set format by pads subdev method1031 * @sd: ISPIF V4L2 subdevice1032 * @sd_state: V4L2 subdev state1033 * @fmt: pointer to v4l2 subdev format structure1034 *1035 * Return -EINVAL or zero on success1036 */1037static int ispif_set_format(struct v4l2_subdev *sd,1038 struct v4l2_subdev_state *sd_state,1039 struct v4l2_subdev_format *fmt)1040{1041 struct ispif_line *line = v4l2_get_subdevdata(sd);1042 struct v4l2_mbus_framefmt *format;1043 1044 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);1045 if (format == NULL)1046 return -EINVAL;1047 1048 ispif_try_format(line, sd_state, fmt->pad, &fmt->format, fmt->which);1049 *format = fmt->format;1050 1051 /* Propagate the format from sink to source */1052 if (fmt->pad == MSM_ISPIF_PAD_SINK) {1053 format = __ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SRC,1054 fmt->which);1055 1056 *format = fmt->format;1057 ispif_try_format(line, sd_state, MSM_ISPIF_PAD_SRC, format,1058 fmt->which);1059 }1060 1061 return 0;1062}1063 1064/*1065 * ispif_init_formats - Initialize formats on all pads1066 * @sd: ISPIF V4L2 subdevice1067 * @fh: V4L2 subdev file handle1068 *1069 * Initialize all pad formats with default values.1070 *1071 * Return 0 on success or a negative error code otherwise1072 */1073static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)1074{1075 struct v4l2_subdev_format format = {1076 .pad = MSM_ISPIF_PAD_SINK,1077 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :1078 V4L2_SUBDEV_FORMAT_ACTIVE,1079 .format = {1080 .code = MEDIA_BUS_FMT_UYVY8_1X16,1081 .width = 1920,1082 .height = 10801083 }1084 };1085 1086 return ispif_set_format(sd, fh ? fh->state : NULL, &format);1087}1088 1089/*1090 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources1091 * @ispif: ISPIF device1092 * @res: ISPIF module resources table1093 *1094 * Return 0 on success or a negative error code otherwise1095 */1096int msm_ispif_subdev_init(struct camss *camss,1097 const struct camss_subdev_resources *res)1098{1099 struct device *dev = camss->dev;1100 struct ispif_device *ispif = camss->ispif;1101 struct platform_device *pdev = to_platform_device(dev);1102 int i;1103 int ret;1104 1105 if (!camss->ispif)1106 return 0;1107 1108 ispif->camss = camss;1109 1110 /* Number of ISPIF lines - same as number of CSID hardware modules */1111 if (camss->res->version == CAMSS_8x16)1112 ispif->line_num = 2;1113 else if (camss->res->version == CAMSS_8x96 ||1114 camss->res->version == CAMSS_660)1115 ispif->line_num = 4;1116 else1117 return -EINVAL;1118 1119 ispif->line = devm_kcalloc(dev, ispif->line_num,1120 sizeof(*ispif->line), GFP_KERNEL);1121 if (!ispif->line)1122 return -ENOMEM;1123 1124 for (i = 0; i < ispif->line_num; i++) {1125 ispif->line[i].ispif = ispif;1126 ispif->line[i].id = i;1127 1128 if (camss->res->version == CAMSS_8x16) {1129 ispif->line[i].formats = ispif_formats_8x16;1130 ispif->line[i].nformats =1131 ARRAY_SIZE(ispif_formats_8x16);1132 } else if (camss->res->version == CAMSS_8x96 ||1133 camss->res->version == CAMSS_660) {1134 ispif->line[i].formats = ispif_formats_8x96;1135 ispif->line[i].nformats =1136 ARRAY_SIZE(ispif_formats_8x96);1137 } else {1138 return -EINVAL;1139 }1140 }1141 1142 /* Memory */1143 1144 ispif->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]);1145 if (IS_ERR(ispif->base))1146 return PTR_ERR(ispif->base);1147 1148 ispif->base_clk_mux = devm_platform_ioremap_resource_byname(pdev, res->reg[1]);1149 if (IS_ERR(ispif->base_clk_mux))1150 return PTR_ERR(ispif->base_clk_mux);1151 1152 /* Interrupt */1153 1154 ret = platform_get_irq_byname(pdev, res->interrupt[0]);1155 if (ret < 0)1156 return ret;1157 1158 ispif->irq = ret;1159 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",1160 dev_name(dev), MSM_ISPIF_NAME);1161 if (camss->res->version == CAMSS_8x16)1162 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,1163 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);1164 else if (camss->res->version == CAMSS_8x96 ||1165 camss->res->version == CAMSS_660)1166 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,1167 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);1168 else1169 ret = -EINVAL;1170 1171 if (ret < 0) {1172 dev_err(dev, "request_irq failed: %d\n", ret);1173 return ret;1174 }1175 1176 /* Clocks */1177 1178 ispif->nclocks = 0;1179 while (res->clock[ispif->nclocks])1180 ispif->nclocks++;1181 1182 ispif->clock = devm_kcalloc(dev,1183 ispif->nclocks, sizeof(*ispif->clock),1184 GFP_KERNEL);1185 if (!ispif->clock)1186 return -ENOMEM;1187 1188 for (i = 0; i < ispif->nclocks; i++) {1189 struct camss_clock *clock = &ispif->clock[i];1190 1191 clock->clk = devm_clk_get(dev, res->clock[i]);1192 if (IS_ERR(clock->clk))1193 return PTR_ERR(clock->clk);1194 1195 clock->freq = NULL;1196 clock->nfreqs = 0;1197 }1198 1199 ispif->nclocks_for_reset = 0;1200 while (res->clock_for_reset[ispif->nclocks_for_reset])1201 ispif->nclocks_for_reset++;1202 1203 ispif->clock_for_reset = devm_kcalloc(dev,1204 ispif->nclocks_for_reset,1205 sizeof(*ispif->clock_for_reset),1206 GFP_KERNEL);1207 if (!ispif->clock_for_reset)1208 return -ENOMEM;1209 1210 for (i = 0; i < ispif->nclocks_for_reset; i++) {1211 struct camss_clock *clock = &ispif->clock_for_reset[i];1212 1213 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);1214 if (IS_ERR(clock->clk))1215 return PTR_ERR(clock->clk);1216 1217 clock->freq = NULL;1218 clock->nfreqs = 0;1219 }1220 1221 mutex_init(&ispif->power_lock);1222 ispif->power_count = 0;1223 1224 mutex_init(&ispif->config_lock);1225 1226 for (i = 0; i < MSM_ISPIF_VFE_NUM; i++)1227 init_completion(&ispif->reset_complete[i]);1228 1229 return 0;1230}1231 1232/*1233 * ispif_get_intf - Get ISPIF interface to use by VFE line id1234 * @line_id: VFE line id that the ISPIF line is connected to1235 *1236 * Return ISPIF interface to use1237 */1238static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)1239{1240 switch (line_id) {1241 case (VFE_LINE_RDI0):1242 return RDI0;1243 case (VFE_LINE_RDI1):1244 return RDI1;1245 case (VFE_LINE_RDI2):1246 return RDI2;1247 case (VFE_LINE_PIX):1248 return PIX0;1249 default:1250 return RDI0;1251 }1252}1253 1254/*1255 * ispif_get_vfe_id - Get VFE HW module id1256 * @entity: Pointer to VFE media entity structure1257 * @id: Return CSID HW module id here1258 */1259static void ispif_get_vfe_id(struct media_entity *entity, u8 *id)1260{1261 struct v4l2_subdev *sd;1262 struct vfe_line *line;1263 struct vfe_device *vfe;1264 1265 sd = media_entity_to_v4l2_subdev(entity);1266 line = v4l2_get_subdevdata(sd);1267 vfe = to_vfe(line);1268 1269 *id = vfe->id;1270}1271 1272/*1273 * ispif_get_vfe_line_id - Get VFE line id by media entity1274 * @entity: Pointer to VFE media entity structure1275 * @id: Return VFE line id here1276 */1277static void ispif_get_vfe_line_id(struct media_entity *entity,1278 enum vfe_line_id *id)1279{1280 struct v4l2_subdev *sd;1281 struct vfe_line *line;1282 1283 sd = media_entity_to_v4l2_subdev(entity);1284 line = v4l2_get_subdevdata(sd);1285 1286 *id = line->id;1287}1288 1289/*1290 * ispif_link_setup - Setup ISPIF connections1291 * @entity: Pointer to media entity structure1292 * @local: Pointer to local pad1293 * @remote: Pointer to remote pad1294 * @flags: Link flags1295 *1296 * Return 0 on success1297 */1298static int ispif_link_setup(struct media_entity *entity,1299 const struct media_pad *local,1300 const struct media_pad *remote, u32 flags)1301{1302 if (flags & MEDIA_LNK_FL_ENABLED) {1303 if (media_pad_remote_pad_first(local))1304 return -EBUSY;1305 1306 if (local->flags & MEDIA_PAD_FL_SINK) {1307 struct v4l2_subdev *sd;1308 struct ispif_line *line;1309 1310 sd = media_entity_to_v4l2_subdev(entity);1311 line = v4l2_get_subdevdata(sd);1312 1313 msm_csid_get_csid_id(remote->entity, &line->csid_id);1314 } else { /* MEDIA_PAD_FL_SOURCE */1315 struct v4l2_subdev *sd;1316 struct ispif_line *line;1317 enum vfe_line_id id;1318 1319 sd = media_entity_to_v4l2_subdev(entity);1320 line = v4l2_get_subdevdata(sd);1321 1322 ispif_get_vfe_id(remote->entity, &line->vfe_id);1323 ispif_get_vfe_line_id(remote->entity, &id);1324 line->interface = ispif_get_intf(id);1325 }1326 }1327 1328 return 0;1329}1330 1331static const struct v4l2_subdev_core_ops ispif_core_ops = {1332 .s_power = ispif_set_power,1333};1334 1335static const struct v4l2_subdev_video_ops ispif_video_ops = {1336 .s_stream = ispif_set_stream,1337};1338 1339static const struct v4l2_subdev_pad_ops ispif_pad_ops = {1340 .enum_mbus_code = ispif_enum_mbus_code,1341 .enum_frame_size = ispif_enum_frame_size,1342 .get_fmt = ispif_get_format,1343 .set_fmt = ispif_set_format,1344};1345 1346static const struct v4l2_subdev_ops ispif_v4l2_ops = {1347 .core = &ispif_core_ops,1348 .video = &ispif_video_ops,1349 .pad = &ispif_pad_ops,1350};1351 1352static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {1353 .open = ispif_init_formats,1354};1355 1356static const struct media_entity_operations ispif_media_ops = {1357 .link_setup = ispif_link_setup,1358 .link_validate = v4l2_subdev_link_validate,1359};1360 1361/*1362 * msm_ispif_register_entities - Register subdev node for ISPIF module1363 * @ispif: ISPIF device1364 * @v4l2_dev: V4L2 device1365 *1366 * Return 0 on success or a negative error code otherwise1367 */1368int msm_ispif_register_entities(struct ispif_device *ispif,1369 struct v4l2_device *v4l2_dev)1370{1371 struct camss *camss;1372 int ret;1373 int i;1374 1375 if (!ispif)1376 return 0;1377 1378 camss = ispif->camss;1379 1380 for (i = 0; i < ispif->line_num; i++) {1381 struct v4l2_subdev *sd = &ispif->line[i].subdev;1382 struct media_pad *pads = ispif->line[i].pads;1383 1384 v4l2_subdev_init(sd, &ispif_v4l2_ops);1385 sd->internal_ops = &ispif_v4l2_internal_ops;1386 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;1387 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",1388 MSM_ISPIF_NAME, i);1389 v4l2_set_subdevdata(sd, &ispif->line[i]);1390 1391 ret = ispif_init_formats(sd, NULL);1392 if (ret < 0) {1393 dev_err(camss->dev, "Failed to init format: %d\n", ret);1394 goto error;1395 }1396 1397 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;1398 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;1399 1400 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;1401 sd->entity.ops = &ispif_media_ops;1402 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,1403 pads);1404 if (ret < 0) {1405 dev_err(camss->dev, "Failed to init media entity: %d\n",1406 ret);1407 goto error;1408 }1409 1410 ret = v4l2_device_register_subdev(v4l2_dev, sd);1411 if (ret < 0) {1412 dev_err(camss->dev, "Failed to register subdev: %d\n",1413 ret);1414 media_entity_cleanup(&sd->entity);1415 goto error;1416 }1417 }1418 1419 return 0;1420 1421error:1422 for (i--; i >= 0; i--) {1423 struct v4l2_subdev *sd = &ispif->line[i].subdev;1424 1425 v4l2_device_unregister_subdev(sd);1426 media_entity_cleanup(&sd->entity);1427 }1428 1429 return ret;1430}1431 1432/*1433 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node1434 * @ispif: ISPIF device1435 */1436void msm_ispif_unregister_entities(struct ispif_device *ispif)1437{1438 int i;1439 1440 if (!ispif)1441 return;1442 1443 mutex_destroy(&ispif->power_lock);1444 mutex_destroy(&ispif->config_lock);1445 1446 for (i = 0; i < ispif->line_num; i++) {1447 struct v4l2_subdev *sd = &ispif->line[i].subdev;1448 1449 v4l2_device_unregister_subdev(sd);1450 media_entity_cleanup(&sd->entity);1451 }1452}1453