161 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.4 * Copyright (C) 2017 Linaro Ltd.5 */6#ifndef __VENUS_HFI_VENUS_IO_H__7#define __VENUS_HFI_VENUS_IO_H__8 9#define VBIF_BASE 0x8000010 11#define VBIF_AXI_HALT_CTRL0 0x20812#define VBIF_AXI_HALT_CTRL1 0x20c13 14#define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)15#define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)16#define VBIF_AXI_HALT_ACK_TIMEOUT_US 50000017 18#define CPU_BASE 0xc000019 20#define CPU_CS_BASE (CPU_BASE + 0x12000)21#define CPU_IC_BASE (CPU_BASE + 0x1f000)22#define CPU_BASE_V6 0xa000023#define CPU_CS_BASE_V6 CPU_BASE_V624#define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)25 26#define CPU_CS_A2HSOFTINTCLR 0x1c27 28#define VIDC_CTRL_INIT 0x4829#define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK 0xfffffffe30#define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 131#define VIDC_CTRL_INIT_CTRL_MASK 0x132#define VIDC_CTRL_INIT_CTRL_SHIFT 033 34/* HFI control status */35#define CPU_CS_SCIACMDARG0 0x4c36#define CPU_CS_SCIACMDARG0_MASK 0xff37#define CPU_CS_SCIACMDARG0_SHIFT 0x038#define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK 0xfe39#define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT 0x140#define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK 0x141#define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT 0x042#define CPU_CS_SCIACMDARG0_PC_READY BIT(8)43#define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30)44 45/* HFI queue table info */46#define CPU_CS_SCIACMDARG1 0x5047 48/* HFI queue table address */49#define CPU_CS_SCIACMDARG2 0x5450 51/* Venus cpu */52#define CPU_CS_SCIACMDARG3 0x5853 54#define SFR_ADDR 0x5c55#define MMAP_ADDR 0x6056#define UC_REGION_ADDR 0x6457#define UC_REGION_SIZE 0x6858 59#define CPU_CS_H2XSOFTINTEN_V6 0x14860 61#define CPU_CS_X2RPMH_V6 0x16862#define CPU_CS_X2RPMH_MASK0_BMSK_V6 0x163#define CPU_CS_X2RPMH_MASK0_SHFT_V6 0x064#define CPU_CS_X2RPMH_MASK1_BMSK_V6 0x265#define CPU_CS_X2RPMH_MASK1_SHFT_V6 0x166#define CPU_CS_X2RPMH_SWOVERRIDE_BMSK_V6 0x467#define CPU_CS_X2RPMH_SWOVERRIDE_SHFT_V6 0x368 69/* Relative to CPU_IC_BASE */70#define CPU_IC_SOFTINT 0x1871#define CPU_IC_SOFTINT_V6 0x15072#define CPU_IC_SOFTINT_H2A_MASK 0x800073#define CPU_IC_SOFTINT_H2A_SHIFT 0xf74#define CPU_IC_SOFTINT_H2A_SHIFT_V6 0x075 76/* Venus wrapper */77#define WRAPPER_BASE_V6 0x000b000078#define WRAPPER_BASE 0x000e000079 80#define WRAPPER_HW_VERSION 0x0081#define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x7800000082#define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 2883#define WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xfff000084#define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 1685#define WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xffff86 87#define WRAPPER_CLOCK_CONFIG 0x0488 89#define WRAPPER_INTR_STATUS 0x0c90#define WRAPPER_INTR_STATUS_A2HWD_MASK 0x1091#define WRAPPER_INTR_STATUS_A2HWD_SHIFT 0x492#define WRAPPER_INTR_STATUS_A2H_MASK 0x493#define WRAPPER_INTR_STATUS_A2H_SHIFT 0x294 95#define WRAPPER_INTR_MASK 0x1096#define WRAPPER_INTR_MASK_A2HWD_BASK 0x1097#define WRAPPER_INTR_MASK_A2HWD_SHIFT 0x498#define WRAPPER_INTR_MASK_A2HVCODEC_MASK 0x899#define WRAPPER_INTR_MASK_A2HVCODEC_SHIFT 0x3100#define WRAPPER_INTR_MASK_A2HCPU_MASK 0x4101#define WRAPPER_INTR_MASK_A2HCPU_SHIFT 0x2102 103#define WRAPPER_INTR_STATUS_A2HWD_MASK_V6 0x8104#define WRAPPER_INTR_MASK_A2HWD_BASK_V6 0x8105 106#define WRAPPER_INTR_CLEAR 0x14107#define WRAPPER_INTR_CLEAR_A2HWD_MASK 0x10108#define WRAPPER_INTR_CLEAR_A2HWD_SHIFT 0x4109#define WRAPPER_INTR_CLEAR_A2H_MASK 0x4110#define WRAPPER_INTR_CLEAR_A2H_SHIFT 0x2111 112#define WRAPPER_POWER_STATUS 0x44113#define WRAPPER_VDEC_VCODEC_POWER_CONTROL 0x48114#define WRAPPER_VENC_VCODEC_POWER_CONTROL 0x4c115#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6 0x54116#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_V6 0x58117#define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET 0x64118 119#define WRAPPER_CPU_CLOCK_CONFIG 0x2000120#define WRAPPER_CPU_AXI_HALT 0x2008121#define WRAPPER_CPU_AXI_HALT_HALT BIT(16)122#define WRAPPER_CPU_AXI_HALT_STATUS 0x200c123#define WRAPPER_CPU_AXI_HALT_STATUS_IDLE BIT(24)124 125#define WRAPPER_CPU_CGC_DIS 0x2010126#define WRAPPER_CPU_STATUS 0x2014127#define WRAPPER_CPU_STATUS_WFI BIT(0)128#define WRAPPER_SW_RESET 0x3000129#define WRAPPER_CPA_START_ADDR 0x1020130#define WRAPPER_CPA_END_ADDR 0x1024131#define WRAPPER_FW_START_ADDR 0x1028132#define WRAPPER_FW_END_ADDR 0x102C133#define WRAPPER_NONPIX_START_ADDR 0x1030134#define WRAPPER_NONPIX_END_ADDR 0x1034135#define WRAPPER_A9SS_SW_RESET 0x3000136#define WRAPPER_A9SS_SW_RESET_BIT BIT(4)137 138/* Venus 4xx */139#define WRAPPER_VCODEC0_MMCC_POWER_STATUS 0x90140#define WRAPPER_VCODEC0_MMCC_POWER_CONTROL 0x94141 142#define WRAPPER_VCODEC1_MMCC_POWER_STATUS 0x110143#define WRAPPER_VCODEC1_MMCC_POWER_CONTROL 0x114144 145/* Venus 6xx */146#define WRAPPER_CORE_POWER_STATUS_V6 0x80147#define WRAPPER_CORE_POWER_CONTROL_V6 0x84148 149/* Wrapper TZ 6xx */150#define WRAPPER_TZ_BASE_V6 0x000c0000151#define WRAPPER_TZ_CPU_STATUS_V6 0x10152#define WRAPPER_TZ_XTSS_SW_RESET 0x1000153#define WRAPPER_XTSS_SW_RESET_BIT BIT(0)154 155/* Venus AON */156#define AON_BASE_V6 0x000e0000157#define AON_WRAPPER_MVP_NOC_LPI_CONTROL 0x00158#define AON_WRAPPER_MVP_NOC_LPI_STATUS 0x04159 160#endif161