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1// SPDX-License-Identifier: GPL-2.02/*3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver4 *5 * Copyright (C) 2022 Renesas Electronics Corp.6 */7 8#include <linux/clk.h>9#include <linux/delay.h>10#include <linux/interrupt.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/of_graph.h>15#include <linux/platform_device.h>16#include <linux/pm_runtime.h>17#include <linux/reset.h>18#include <linux/sys_soc.h>19#include <linux/units.h>20 21#include <media/v4l2-ctrls.h>22#include <media/v4l2-device.h>23#include <media/v4l2-fwnode.h>24#include <media/v4l2-mc.h>25#include <media/v4l2-subdev.h>26 27/* LINK registers */28/* Module Configuration Register */29#define CSI2nMCG 0x030#define CSI2nMCG_SDLN GENMASK(11, 8)31 32/* Module Control Register 0 */33#define CSI2nMCT0 0x1034#define CSI2nMCT0_VDLN(x) ((x) << 0)35 36/* Module Control Register 2 */37#define CSI2nMCT2 0x1838#define CSI2nMCT2_FRRSKW(x) ((x) << 16)39#define CSI2nMCT2_FRRCLK(x) ((x) << 0)40 41/* Module Control Register 3 */42#define CSI2nMCT3 0x1c43#define CSI2nMCT3_RXEN BIT(0)44 45/* Reset Control Register */46#define CSI2nRTCT 0x2847#define CSI2nRTCT_VSRST BIT(0)48 49/* Reset Status Register */50#define CSI2nRTST 0x2c51#define CSI2nRTST_VSRSTS BIT(0)52 53/* Receive Data Type Enable Low Register */54#define CSI2nDTEL 0x6055 56/* Receive Data Type Enable High Register */57#define CSI2nDTEH 0x6458 59/* DPHY registers */60/* D-PHY Control Register 0 */61#define CSIDPHYCTRL0 0x40062#define CSIDPHYCTRL0_EN_LDO1200 BIT(1)63#define CSIDPHYCTRL0_EN_BGR BIT(0)64 65/* D-PHY Timing Register 0 */66#define CSIDPHYTIM0 0x40467#define CSIDPHYTIM0_TCLK_MISS(x) ((x) << 24)68#define CSIDPHYTIM0_T_INIT(x) ((x) << 0)69 70/* D-PHY Timing Register 1 */71#define CSIDPHYTIM1 0x40872#define CSIDPHYTIM1_THS_PREPARE(x) ((x) << 24)73#define CSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16)74#define CSIDPHYTIM1_THS_SETTLE(x) ((x) << 8)75#define CSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0)76 77/* D-PHY Skew Adjustment Function */78#define CSIDPHYSKW0 0x46079#define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x) ((x) & 0x3)80#define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x) (((x) & 0x3) << 4)81#define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x) (((x) & 0x3) << 8)82#define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x) (((x) & 0x3) << 12)83#define CSIDPHYSKW0_DEFAULT_SKW (CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \84 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \85 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \86 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1))87 88#define VSRSTS_RETRIES 2089 90#define RZG2L_CSI2_MIN_WIDTH 32091#define RZG2L_CSI2_MIN_HEIGHT 24092#define RZG2L_CSI2_MAX_WIDTH 280093#define RZG2L_CSI2_MAX_HEIGHT 409594 95#define RZG2L_CSI2_DEFAULT_WIDTH RZG2L_CSI2_MIN_WIDTH96#define RZG2L_CSI2_DEFAULT_HEIGHT RZG2L_CSI2_MIN_HEIGHT97#define RZG2L_CSI2_DEFAULT_FMT MEDIA_BUS_FMT_UYVY8_1X1698 99enum rzg2l_csi2_pads {100 RZG2L_CSI2_SINK = 0,101 RZG2L_CSI2_SOURCE,102 NR_OF_RZG2L_CSI2_PAD,103};104 105struct rzg2l_csi2 {106 struct device *dev;107 void __iomem *base;108 struct reset_control *presetn;109 struct reset_control *cmn_rstb;110 struct clk *sysclk;111 struct clk *vclk;112 unsigned long vclk_rate;113 114 struct v4l2_subdev subdev;115 struct media_pad pads[NR_OF_RZG2L_CSI2_PAD];116 117 struct v4l2_async_notifier notifier;118 struct v4l2_subdev *remote_source;119 120 unsigned short lanes;121 unsigned long hsfreq;122 123 bool dphy_enabled;124};125 126struct rzg2l_csi2_timings {127 u32 t_init;128 u32 tclk_miss;129 u32 tclk_settle;130 u32 ths_settle;131 u32 tclk_prepare;132 u32 ths_prepare;133 u32 max_hsfreq;134};135 136static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = {137 {138 .max_hsfreq = 80,139 .t_init = 79801,140 .tclk_miss = 4,141 .tclk_settle = 23,142 .ths_settle = 31,143 .tclk_prepare = 10,144 .ths_prepare = 19,145 },146 {147 .max_hsfreq = 125,148 .t_init = 79801,149 .tclk_miss = 4,150 .tclk_settle = 23,151 .ths_settle = 28,152 .tclk_prepare = 10,153 .ths_prepare = 19,154 },155 {156 .max_hsfreq = 250,157 .t_init = 79801,158 .tclk_miss = 4,159 .tclk_settle = 23,160 .ths_settle = 22,161 .tclk_prepare = 10,162 .ths_prepare = 16,163 },164 {165 .max_hsfreq = 360,166 .t_init = 79801,167 .tclk_miss = 4,168 .tclk_settle = 18,169 .ths_settle = 19,170 .tclk_prepare = 10,171 .ths_prepare = 10,172 },173 {174 .max_hsfreq = 1500,175 .t_init = 79801,176 .tclk_miss = 4,177 .tclk_settle = 18,178 .ths_settle = 18,179 .tclk_prepare = 10,180 .ths_prepare = 10,181 },182};183 184struct rzg2l_csi2_format {185 u32 code;186 unsigned int datatype;187 unsigned int bpp;188};189 190static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = {191 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 },192};193 194static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd)195{196 return container_of(sd, struct rzg2l_csi2, subdev);197}198 199static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code)200{201 unsigned int i;202 203 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_formats); i++)204 if (rzg2l_csi2_formats[i].code == code)205 return &rzg2l_csi2_formats[i];206 207 return NULL;208}209 210static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)211{212 return container_of(n, struct rzg2l_csi2, notifier);213}214 215static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg)216{217 return ioread32(csi2->base + reg);218}219 220static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg,221 u32 data)222{223 iowrite32(data, csi2->base + reg);224}225 226static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set)227{228 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) | set);229}230 231static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr)232{233 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) & ~clr);234}235 236static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2)237{238 struct v4l2_subdev *source = csi2->remote_source;239 const struct rzg2l_csi2_format *format;240 const struct v4l2_mbus_framefmt *fmt;241 struct v4l2_subdev_state *state;242 struct v4l2_ctrl *ctrl;243 u64 mbps;244 245 /* Read the pixel rate control from remote. */246 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);247 if (!ctrl) {248 dev_err(csi2->dev, "no pixel rate control in subdev %s\n",249 source->name);250 return -EINVAL;251 }252 253 state = v4l2_subdev_lock_and_get_active_state(&csi2->subdev);254 fmt = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);255 format = rzg2l_csi2_code_to_fmt(fmt->code);256 v4l2_subdev_unlock_state(state);257 258 /*259 * Calculate hsfreq in Mbps260 * hsfreq = (pixel_rate * bits_per_sample) / number_of_lanes261 */262 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * format->bpp;263 do_div(mbps, csi2->lanes * 1000000);264 265 return mbps;266}267 268/* -----------------------------------------------------------------------------269 * DPHY setting270 */271 272static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2)273{274 int ret;275 276 /* Reset the CRU (D-PHY) */277 ret = reset_control_assert(csi2->cmn_rstb);278 if (ret)279 return ret;280 281 /* Stop the D-PHY clock */282 clk_disable_unprepare(csi2->sysclk);283 284 /* Cancel the EN_LDO1200 register setting */285 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);286 287 /* Cancel the EN_BGR register setting */288 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);289 290 csi2->dphy_enabled = false;291 292 return 0;293}294 295static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2)296{297 const struct rzg2l_csi2_timings *dphy_timing;298 u32 dphytim0, dphytim1;299 unsigned int i;300 int mbps;301 int ret;302 303 mbps = rzg2l_csi2_calc_mbps(csi2);304 if (mbps < 0)305 return mbps;306 307 csi2->hsfreq = mbps;308 309 /* Set DPHY timing parameters */310 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_global_timings); ++i) {311 dphy_timing = &rzg2l_csi2_global_timings[i];312 313 if (csi2->hsfreq <= dphy_timing->max_hsfreq)314 break;315 }316 317 if (i >= ARRAY_SIZE(rzg2l_csi2_global_timings))318 return -EINVAL;319 320 /* Set D-PHY timing parameters */321 dphytim0 = CSIDPHYTIM0_TCLK_MISS(dphy_timing->tclk_miss) |322 CSIDPHYTIM0_T_INIT(dphy_timing->t_init);323 dphytim1 = CSIDPHYTIM1_THS_PREPARE(dphy_timing->ths_prepare) |324 CSIDPHYTIM1_TCLK_PREPARE(dphy_timing->tclk_prepare) |325 CSIDPHYTIM1_THS_SETTLE(dphy_timing->ths_settle) |326 CSIDPHYTIM1_TCLK_SETTLE(dphy_timing->tclk_settle);327 rzg2l_csi2_write(csi2, CSIDPHYTIM0, dphytim0);328 rzg2l_csi2_write(csi2, CSIDPHYTIM1, dphytim1);329 330 /* Enable D-PHY power control 0 */331 rzg2l_csi2_write(csi2, CSIDPHYSKW0, CSIDPHYSKW0_DEFAULT_SKW);332 333 /* Set the EN_BGR bit */334 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);335 336 /* Delay 20us to be stable */337 usleep_range(20, 40);338 339 /* Enable D-PHY power control 1 */340 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);341 342 /* Delay 10us to be stable */343 usleep_range(10, 20);344 345 /* Start supplying the internal clock for the D-PHY block */346 ret = clk_prepare_enable(csi2->sysclk);347 if (ret)348 rzg2l_csi2_dphy_disable(csi2);349 350 csi2->dphy_enabled = true;351 352 return ret;353}354 355static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on)356{357 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);358 359 if (on)360 return rzg2l_csi2_dphy_enable(csi2);361 362 return rzg2l_csi2_dphy_disable(csi2);363}364 365static int rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2)366{367 unsigned long vclk_rate = csi2->vclk_rate / HZ_PER_MHZ;368 u32 frrskw, frrclk, frrskw_coeff, frrclk_coeff;369 370 /* Select data lanes */371 rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes));372 373 frrskw_coeff = 3 * vclk_rate * 8;374 frrclk_coeff = frrskw_coeff / 2;375 frrskw = DIV_ROUND_UP(frrskw_coeff, csi2->hsfreq);376 frrclk = DIV_ROUND_UP(frrclk_coeff, csi2->hsfreq);377 rzg2l_csi2_write(csi2, CSI2nMCT2, CSI2nMCT2_FRRSKW(frrskw) |378 CSI2nMCT2_FRRCLK(frrclk));379 380 /*381 * Select data type.382 * FS, FE, LS, LE, Generic Short Packet Codes 1 to 8,383 * Generic Long Packet Data Types 1 to 4 YUV422 8-bit,384 * RGB565, RGB888, RAW8 to RAW20, User-defined 8-bit385 * data types 1 to 8386 */387 rzg2l_csi2_write(csi2, CSI2nDTEL, 0xf778ff0f);388 rzg2l_csi2_write(csi2, CSI2nDTEH, 0x00ffff1f);389 390 clk_disable_unprepare(csi2->vclk);391 392 /* Enable LINK reception */393 rzg2l_csi2_write(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);394 395 return clk_prepare_enable(csi2->vclk);396}397 398static int rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2)399{400 unsigned int timeout = VSRSTS_RETRIES;401 402 /* Stop LINK reception */403 rzg2l_csi2_clr(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);404 405 /* Request a software reset of the LINK Video Pixel Interface */406 rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST);407 408 /* Make sure CSI2nRTST.VSRSTS bit is cleared */409 while (--timeout) {410 if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS))411 break;412 usleep_range(100, 200);413 }414 415 if (!timeout)416 dev_err(csi2->dev, "Clearing CSI2nRTST.VSRSTS timed out\n");417 418 return 0;419}420 421static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on)422{423 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);424 int ret;425 426 if (on)427 ret = rzg2l_csi2_mipi_link_enable(csi2);428 else429 ret = rzg2l_csi2_mipi_link_disable(csi2);430 431 return ret;432}433 434static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable)435{436 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);437 int s_stream_ret = 0;438 int ret;439 440 if (enable) {441 ret = pm_runtime_resume_and_get(csi2->dev);442 if (ret)443 return ret;444 445 ret = rzg2l_csi2_mipi_link_setting(sd, 1);446 if (ret)447 goto err_pm_put;448 449 ret = reset_control_deassert(csi2->cmn_rstb);450 if (ret)451 goto err_mipi_link_disable;452 }453 454 ret = v4l2_subdev_call(csi2->remote_source, video, s_stream, enable);455 if (ret)456 s_stream_ret = ret;457 458 if (enable && ret)459 goto err_assert_rstb;460 461 if (!enable) {462 ret = rzg2l_csi2_dphy_setting(sd, 0);463 if (ret && !s_stream_ret)464 s_stream_ret = ret;465 ret = rzg2l_csi2_mipi_link_setting(sd, 0);466 if (ret && !s_stream_ret)467 s_stream_ret = ret;468 469 pm_runtime_put_sync(csi2->dev);470 }471 472 return s_stream_ret;473 474err_assert_rstb:475 reset_control_assert(csi2->cmn_rstb);476err_mipi_link_disable:477 rzg2l_csi2_mipi_link_setting(sd, 0);478err_pm_put:479 pm_runtime_put_sync(csi2->dev);480 return ret;481}482 483static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags)484{485 return rzg2l_csi2_dphy_setting(sd, 1);486}487 488static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd)489{490 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);491 492 /*493 * In ideal case D-PHY will be disabled in s_stream(0) callback494 * as mentioned in the HW manual. The below will only happen when495 * pre_streamon succeeds and further down the line s_stream(1)496 * fails so we need to undo things in post_streamoff.497 */498 if (csi2->dphy_enabled)499 return rzg2l_csi2_dphy_setting(sd, 0);500 501 return 0;502}503 504static int rzg2l_csi2_set_format(struct v4l2_subdev *sd,505 struct v4l2_subdev_state *state,506 struct v4l2_subdev_format *fmt)507{508 struct v4l2_mbus_framefmt *src_format;509 struct v4l2_mbus_framefmt *sink_format;510 511 src_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SOURCE);512 if (fmt->pad == RZG2L_CSI2_SOURCE) {513 fmt->format = *src_format;514 return 0;515 }516 517 sink_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK);518 519 if (!rzg2l_csi2_code_to_fmt(fmt->format.code))520 sink_format->code = rzg2l_csi2_formats[0].code;521 else522 sink_format->code = fmt->format.code;523 524 sink_format->field = V4L2_FIELD_NONE;525 sink_format->colorspace = fmt->format.colorspace;526 sink_format->xfer_func = fmt->format.xfer_func;527 sink_format->ycbcr_enc = fmt->format.ycbcr_enc;528 sink_format->quantization = fmt->format.quantization;529 sink_format->width = clamp_t(u32, fmt->format.width,530 RZG2L_CSI2_MIN_WIDTH, RZG2L_CSI2_MAX_WIDTH);531 sink_format->height = clamp_t(u32, fmt->format.height,532 RZG2L_CSI2_MIN_HEIGHT, RZG2L_CSI2_MAX_HEIGHT);533 fmt->format = *sink_format;534 535 /* propagate format to source pad */536 *src_format = *sink_format;537 538 return 0;539}540 541static int rzg2l_csi2_init_state(struct v4l2_subdev *sd,542 struct v4l2_subdev_state *sd_state)543{544 struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, };545 546 fmt.format.width = RZG2L_CSI2_DEFAULT_WIDTH;547 fmt.format.height = RZG2L_CSI2_DEFAULT_HEIGHT;548 fmt.format.field = V4L2_FIELD_NONE;549 fmt.format.code = RZG2L_CSI2_DEFAULT_FMT;550 fmt.format.colorspace = V4L2_COLORSPACE_SRGB;551 fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;552 fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT;553 fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT;554 555 return rzg2l_csi2_set_format(sd, sd_state, &fmt);556}557 558static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd,559 struct v4l2_subdev_state *sd_state,560 struct v4l2_subdev_mbus_code_enum *code)561{562 if (code->index >= ARRAY_SIZE(rzg2l_csi2_formats))563 return -EINVAL;564 565 code->code = rzg2l_csi2_formats[code->index].code;566 567 return 0;568}569 570static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd,571 struct v4l2_subdev_state *sd_state,572 struct v4l2_subdev_frame_size_enum *fse)573{574 if (fse->index != 0)575 return -EINVAL;576 577 fse->min_width = RZG2L_CSI2_MIN_WIDTH;578 fse->min_height = RZG2L_CSI2_MIN_HEIGHT;579 fse->max_width = RZG2L_CSI2_MAX_WIDTH;580 fse->max_height = RZG2L_CSI2_MAX_HEIGHT;581 582 return 0;583}584 585static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = {586 .s_stream = rzg2l_csi2_s_stream,587 .pre_streamon = rzg2l_csi2_pre_streamon,588 .post_streamoff = rzg2l_csi2_post_streamoff,589};590 591static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = {592 .enum_mbus_code = rzg2l_csi2_enum_mbus_code,593 .enum_frame_size = rzg2l_csi2_enum_frame_size,594 .set_fmt = rzg2l_csi2_set_format,595 .get_fmt = v4l2_subdev_get_fmt,596};597 598static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = {599 .video = &rzg2l_csi2_video_ops,600 .pad = &rzg2l_csi2_pad_ops,601};602 603static const struct v4l2_subdev_internal_ops rzg2l_csi2_internal_ops = {604 .init_state = rzg2l_csi2_init_state,605};606 607/* -----------------------------------------------------------------------------608 * Async handling and registration of subdevices and links.609 */610 611static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier,612 struct v4l2_subdev *subdev,613 struct v4l2_async_connection *asd)614{615 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);616 617 csi2->remote_source = subdev;618 619 dev_dbg(csi2->dev, "Bound subdev: %s pad\n", subdev->name);620 621 return media_create_pad_link(&subdev->entity, RZG2L_CSI2_SINK,622 &csi2->subdev.entity, 0,623 MEDIA_LNK_FL_ENABLED |624 MEDIA_LNK_FL_IMMUTABLE);625}626 627static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier,628 struct v4l2_subdev *subdev,629 struct v4l2_async_connection *asd)630{631 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);632 633 csi2->remote_source = NULL;634 635 dev_dbg(csi2->dev, "Unbind subdev %s\n", subdev->name);636}637 638static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = {639 .bound = rzg2l_csi2_notify_bound,640 .unbind = rzg2l_csi2_notify_unbind,641};642 643static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2,644 struct v4l2_fwnode_endpoint *vep)645{646 /* Only port 0 endpoint 0 is valid. */647 if (vep->base.port || vep->base.id)648 return -ENOTCONN;649 650 csi2->lanes = vep->bus.mipi_csi2.num_data_lanes;651 652 return 0;653}654 655static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2)656{657 struct v4l2_fwnode_endpoint v4l2_ep = {658 .bus_type = V4L2_MBUS_CSI2_DPHY659 };660 struct v4l2_async_connection *asd;661 struct fwnode_handle *fwnode;662 struct fwnode_handle *ep;663 int ret;664 665 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0, 0);666 if (!ep) {667 dev_err(csi2->dev, "Not connected to subdevice\n");668 return -EINVAL;669 }670 671 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);672 if (ret) {673 dev_err(csi2->dev, "Could not parse v4l2 endpoint\n");674 fwnode_handle_put(ep);675 return -EINVAL;676 }677 678 ret = rzg2l_csi2_parse_v4l2(csi2, &v4l2_ep);679 if (ret) {680 fwnode_handle_put(ep);681 return ret;682 }683 684 fwnode = fwnode_graph_get_remote_endpoint(ep);685 fwnode_handle_put(ep);686 687 v4l2_async_subdev_nf_init(&csi2->notifier, &csi2->subdev);688 csi2->notifier.ops = &rzg2l_csi2_notify_ops;689 690 asd = v4l2_async_nf_add_fwnode(&csi2->notifier, fwnode,691 struct v4l2_async_connection);692 fwnode_handle_put(fwnode);693 if (IS_ERR(asd))694 return PTR_ERR(asd);695 696 ret = v4l2_async_nf_register(&csi2->notifier);697 if (ret)698 v4l2_async_nf_cleanup(&csi2->notifier);699 700 return ret;701}702 703static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2)704{705 int lanes;706 int ret;707 708 if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) {709 dev_err(csi2->dev, "Unsupported number of data-lanes: %u\n",710 csi2->lanes);711 return -EINVAL;712 }713 714 ret = pm_runtime_resume_and_get(csi2->dev);715 if (ret)716 return ret;717 718 /* Checking the maximum lanes support for CSI-2 module */719 lanes = (rzg2l_csi2_read(csi2, CSI2nMCG) & CSI2nMCG_SDLN) >> 8;720 if (lanes < csi2->lanes) {721 dev_err(csi2->dev,722 "Failed to support %d data lanes\n", csi2->lanes);723 ret = -EINVAL;724 }725 726 pm_runtime_put_sync(csi2->dev);727 728 return ret;729}730 731/* -----------------------------------------------------------------------------732 * Platform Device Driver.733 */734 735static const struct media_entity_operations rzg2l_csi2_entity_ops = {736 .link_validate = v4l2_subdev_link_validate,737};738 739static int rzg2l_csi2_probe(struct platform_device *pdev)740{741 struct rzg2l_csi2 *csi2;742 int ret;743 744 csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL);745 if (!csi2)746 return -ENOMEM;747 748 csi2->base = devm_platform_ioremap_resource(pdev, 0);749 if (IS_ERR(csi2->base))750 return PTR_ERR(csi2->base);751 752 csi2->cmn_rstb = devm_reset_control_get_exclusive(&pdev->dev, "cmn-rstb");753 if (IS_ERR(csi2->cmn_rstb))754 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->cmn_rstb),755 "Failed to get cpg cmn-rstb\n");756 757 csi2->presetn = devm_reset_control_get_shared(&pdev->dev, "presetn");758 if (IS_ERR(csi2->presetn))759 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->presetn),760 "Failed to get cpg presetn\n");761 762 csi2->sysclk = devm_clk_get(&pdev->dev, "system");763 if (IS_ERR(csi2->sysclk))764 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->sysclk),765 "Failed to get system clk\n");766 767 csi2->vclk = devm_clk_get(&pdev->dev, "video");768 if (IS_ERR(csi2->vclk))769 return dev_err_probe(&pdev->dev, PTR_ERR(csi2->vclk),770 "Failed to get video clock\n");771 csi2->vclk_rate = clk_get_rate(csi2->vclk);772 773 csi2->dev = &pdev->dev;774 775 platform_set_drvdata(pdev, csi2);776 777 ret = rzg2l_csi2_parse_dt(csi2);778 if (ret)779 return ret;780 781 pm_runtime_enable(&pdev->dev);782 783 ret = rzg2l_validate_csi2_lanes(csi2);784 if (ret)785 goto error_pm;786 787 csi2->subdev.dev = &pdev->dev;788 v4l2_subdev_init(&csi2->subdev, &rzg2l_csi2_subdev_ops);789 csi2->subdev.internal_ops = &rzg2l_csi2_internal_ops;790 v4l2_set_subdevdata(&csi2->subdev, &pdev->dev);791 snprintf(csi2->subdev.name, sizeof(csi2->subdev.name),792 "csi-%s", dev_name(&pdev->dev));793 csi2->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;794 795 csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;796 csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops;797 798 csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;799 /*800 * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual801 * channels should be implemented by streams API which is under802 * development lets hardcode to VC0 for now.803 */804 csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE;805 ret = media_entity_pads_init(&csi2->subdev.entity, 2, csi2->pads);806 if (ret)807 goto error_pm;808 809 ret = v4l2_subdev_init_finalize(&csi2->subdev);810 if (ret < 0)811 goto error_async;812 813 ret = v4l2_async_register_subdev(&csi2->subdev);814 if (ret < 0)815 goto error_subdev;816 817 return 0;818 819error_subdev:820 v4l2_subdev_cleanup(&csi2->subdev);821error_async:822 v4l2_async_nf_unregister(&csi2->notifier);823 v4l2_async_nf_cleanup(&csi2->notifier);824 media_entity_cleanup(&csi2->subdev.entity);825error_pm:826 pm_runtime_disable(&pdev->dev);827 828 return ret;829}830 831static void rzg2l_csi2_remove(struct platform_device *pdev)832{833 struct rzg2l_csi2 *csi2 = platform_get_drvdata(pdev);834 835 v4l2_async_nf_unregister(&csi2->notifier);836 v4l2_async_nf_cleanup(&csi2->notifier);837 v4l2_async_unregister_subdev(&csi2->subdev);838 v4l2_subdev_cleanup(&csi2->subdev);839 media_entity_cleanup(&csi2->subdev.entity);840 pm_runtime_disable(&pdev->dev);841}842 843static int rzg2l_csi2_pm_runtime_suspend(struct device *dev)844{845 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);846 847 reset_control_assert(csi2->presetn);848 849 return 0;850}851 852static int rzg2l_csi2_pm_runtime_resume(struct device *dev)853{854 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);855 856 return reset_control_deassert(csi2->presetn);857}858 859static const struct dev_pm_ops rzg2l_csi2_pm_ops = {860 RUNTIME_PM_OPS(rzg2l_csi2_pm_runtime_suspend,861 rzg2l_csi2_pm_runtime_resume, NULL)862};863 864static const struct of_device_id rzg2l_csi2_of_table[] = {865 { .compatible = "renesas,rzg2l-csi2", },866 { /* sentinel */ }867};868MODULE_DEVICE_TABLE(of, rzg2l_csi2_of_table);869 870static struct platform_driver rzg2l_csi2_pdrv = {871 .remove_new = rzg2l_csi2_remove,872 .probe = rzg2l_csi2_probe,873 .driver = {874 .name = "rzg2l-csi2",875 .of_match_table = rzg2l_csi2_of_table,876 .pm = pm_ptr(&rzg2l_csi2_pm_ops),877 },878};879 880module_platform_driver(rzg2l_csi2_pdrv);881 882MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");883MODULE_DESCRIPTION("Renesas RZ/G2L MIPI CSI2 receiver driver");884MODULE_LICENSE("GPL");885