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1// SPDX-License-Identifier: GPL-2.0+2/*3 * vsp1_drm.c -- R-Car VSP1 DRM/KMS Interface4 *5 * Copyright (C) 2015 Renesas Electronics Corporation6 *7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)8 */9 10#include <linux/device.h>11#include <linux/dma-mapping.h>12#include <linux/slab.h>13 14#include <media/media-entity.h>15#include <media/v4l2-subdev.h>16#include <media/vsp1.h>17 18#include "vsp1.h"19#include "vsp1_brx.h"20#include "vsp1_dl.h"21#include "vsp1_drm.h"22#include "vsp1_lif.h"23#include "vsp1_pipe.h"24#include "vsp1_rwpf.h"25#include "vsp1_uif.h"26 27#define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"28 29/* -----------------------------------------------------------------------------30 * Interrupt Handling31 */32 33static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,34 unsigned int completion)35{36 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);37 38 if (drm_pipe->du_complete) {39 struct vsp1_entity *uif = drm_pipe->uif;40 unsigned int status = completion41 & (VSP1_DU_STATUS_COMPLETE |42 VSP1_DU_STATUS_WRITEBACK);43 u32 crc;44 45 crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0;46 drm_pipe->du_complete(drm_pipe->du_private, status, crc);47 }48 49 if (completion & VSP1_DL_FRAME_END_INTERNAL) {50 drm_pipe->force_brx_release = false;51 wake_up(&drm_pipe->wait_queue);52 }53}54 55/* -----------------------------------------------------------------------------56 * Pipeline Configuration57 */58 59/*60 * Insert the UIF in the pipeline between the prev and next entities. If no UIF61 * is available connect the two entities directly.62 */63static int vsp1_du_insert_uif(struct vsp1_device *vsp1,64 struct vsp1_pipeline *pipe,65 struct vsp1_entity *uif,66 struct vsp1_entity *prev, unsigned int prev_pad,67 struct vsp1_entity *next, unsigned int next_pad)68{69 struct v4l2_subdev_format format = {70 .which = V4L2_SUBDEV_FORMAT_ACTIVE,71 };72 int ret;73 74 if (!uif) {75 /*76 * If there's no UIF to be inserted, connect the previous and77 * next entities directly.78 */79 prev->sink = next;80 prev->sink_pad = next_pad;81 return 0;82 }83 84 prev->sink = uif;85 prev->sink_pad = UIF_PAD_SINK;86 87 format.pad = prev_pad;88 89 ret = v4l2_subdev_call(&prev->subdev, pad, get_fmt, NULL, &format);90 if (ret < 0)91 return ret;92 93 format.pad = UIF_PAD_SINK;94 95 ret = v4l2_subdev_call(&uif->subdev, pad, set_fmt, NULL, &format);96 if (ret < 0)97 return ret;98 99 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on UIF sink\n",100 __func__, format.format.width, format.format.height,101 format.format.code);102 103 /*104 * The UIF doesn't mangle the format between its sink and source pads,105 * so there is no need to retrieve the format on its source pad.106 */107 108 uif->sink = next;109 uif->sink_pad = next_pad;110 111 return 0;112}113 114/* Setup one RPF and the connected BRx sink pad. */115static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,116 struct vsp1_pipeline *pipe,117 struct vsp1_rwpf *rpf,118 struct vsp1_entity *uif,119 unsigned int brx_input)120{121 struct v4l2_subdev_selection sel = {122 .which = V4L2_SUBDEV_FORMAT_ACTIVE,123 };124 struct v4l2_subdev_format format = {125 .which = V4L2_SUBDEV_FORMAT_ACTIVE,126 };127 const struct v4l2_rect *crop;128 int ret;129 130 /*131 * Configure the format on the RPF sink pad and propagate it up to the132 * BRx sink pad.133 */134 crop = &vsp1->drm->inputs[rpf->entity.index].crop;135 136 format.pad = RWPF_PAD_SINK;137 format.format.width = crop->width + crop->left;138 format.format.height = crop->height + crop->top;139 format.format.code = rpf->fmtinfo->mbus;140 format.format.field = V4L2_FIELD_NONE;141 142 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,143 &format);144 if (ret < 0)145 return ret;146 147 dev_dbg(vsp1->dev,148 "%s: set format %ux%u (%x) on RPF%u sink\n",149 __func__, format.format.width, format.format.height,150 format.format.code, rpf->entity.index);151 152 sel.pad = RWPF_PAD_SINK;153 sel.target = V4L2_SEL_TGT_CROP;154 sel.r = *crop;155 156 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,157 &sel);158 if (ret < 0)159 return ret;160 161 dev_dbg(vsp1->dev,162 "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",163 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,164 rpf->entity.index);165 166 /*167 * RPF source, hardcode the format to ARGB8888 to turn on format168 * conversion if needed.169 */170 format.pad = RWPF_PAD_SOURCE;171 172 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,173 &format);174 if (ret < 0)175 return ret;176 177 dev_dbg(vsp1->dev,178 "%s: got format %ux%u (%x) on RPF%u source\n",179 __func__, format.format.width, format.format.height,180 format.format.code, rpf->entity.index);181 182 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;183 184 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,185 &format);186 if (ret < 0)187 return ret;188 189 /* Insert and configure the UIF if available. */190 ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,191 pipe->brx, brx_input);192 if (ret < 0)193 return ret;194 195 /* BRx sink, propagate the format from the RPF source. */196 format.pad = brx_input;197 198 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,199 &format);200 if (ret < 0)201 return ret;202 203 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",204 __func__, format.format.width, format.format.height,205 format.format.code, BRX_NAME(pipe->brx), format.pad);206 207 sel.pad = brx_input;208 sel.target = V4L2_SEL_TGT_COMPOSE;209 sel.r = vsp1->drm->inputs[rpf->entity.index].compose;210 211 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,212 &sel);213 if (ret < 0)214 return ret;215 216 dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",217 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,218 BRX_NAME(pipe->brx), sel.pad);219 220 return 0;221}222 223/* Setup the BRx source pad. */224static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,225 struct vsp1_pipeline *pipe);226static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);227 228static int vsp1_du_pipeline_setup_brx(struct vsp1_device *vsp1,229 struct vsp1_pipeline *pipe)230{231 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);232 struct v4l2_subdev_format format = {233 .which = V4L2_SUBDEV_FORMAT_ACTIVE,234 };235 struct vsp1_entity *brx;236 int ret;237 238 /*239 * Pick a BRx:240 * - If we need more than two inputs, use the BRU.241 * - Otherwise, if we are not forced to release our BRx, keep it.242 * - Else, use any free BRx (randomly starting with the BRU).243 */244 if (pipe->num_inputs > 2)245 brx = &vsp1->bru->entity;246 else if (pipe->brx && !drm_pipe->force_brx_release)247 brx = pipe->brx;248 else if (vsp1_feature(vsp1, VSP1_HAS_BRU) && !vsp1->bru->entity.pipe)249 brx = &vsp1->bru->entity;250 else251 brx = &vsp1->brs->entity;252 253 /* Switch BRx if needed. */254 if (brx != pipe->brx) {255 struct vsp1_entity *released_brx = NULL;256 257 /* Release our BRx if we have one. */258 if (pipe->brx) {259 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",260 __func__, pipe->lif->index,261 BRX_NAME(pipe->brx));262 263 /*264 * The BRx might be acquired by the other pipeline in265 * the next step. We must thus remove it from the list266 * of entities for this pipeline. The other pipeline's267 * hardware configuration will reconfigure the BRx268 * routing.269 *270 * However, if the other pipeline doesn't acquire our271 * BRx, we need to keep it in the list, otherwise the272 * hardware configuration step won't disconnect it from273 * the pipeline. To solve this, store the released BRx274 * pointer to add it back to the list of entities later275 * if it isn't acquired by the other pipeline.276 */277 released_brx = pipe->brx;278 279 list_del(&pipe->brx->list_pipe);280 pipe->brx->sink = NULL;281 pipe->brx->pipe = NULL;282 pipe->brx = NULL;283 }284 285 /*286 * If the BRx we need is in use, force the owner pipeline to287 * switch to the other BRx and wait until the switch completes.288 */289 if (brx->pipe) {290 struct vsp1_drm_pipeline *owner_pipe;291 292 dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",293 __func__, pipe->lif->index, BRX_NAME(brx));294 295 owner_pipe = to_vsp1_drm_pipeline(brx->pipe);296 owner_pipe->force_brx_release = true;297 298 vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);299 vsp1_du_pipeline_configure(&owner_pipe->pipe);300 301 ret = wait_event_timeout(owner_pipe->wait_queue,302 !owner_pipe->force_brx_release,303 msecs_to_jiffies(500));304 if (ret == 0)305 dev_warn(vsp1->dev,306 "DRM pipeline %u reconfiguration timeout\n",307 owner_pipe->pipe.lif->index);308 }309 310 /*311 * If the BRx we have released previously hasn't been acquired312 * by the other pipeline, add it back to the entities list (with313 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()314 * disconnect it from the hardware pipeline.315 */316 if (released_brx && !released_brx->pipe)317 list_add_tail(&released_brx->list_pipe,318 &pipe->entities);319 320 /*321 * Add the BRx to the pipeline, inserting it just before the322 * WPF.323 */324 dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",325 __func__, pipe->lif->index, BRX_NAME(brx));326 327 pipe->brx = brx;328 pipe->brx->pipe = pipe;329 pipe->brx->sink = &pipe->output->entity;330 pipe->brx->sink_pad = 0;331 332 list_add_tail(&pipe->brx->list_pipe,333 &pipe->output->entity.list_pipe);334 }335 336 /*337 * Configure the format on the BRx source and verify that it matches the338 * requested format. We don't set the media bus code as it is configured339 * on the BRx sink pad 0 and propagated inside the entity, not on the340 * source pad.341 */342 format.pad = brx->source_pad;343 format.format.width = drm_pipe->width;344 format.format.height = drm_pipe->height;345 format.format.field = V4L2_FIELD_NONE;346 347 ret = v4l2_subdev_call(&brx->subdev, pad, set_fmt, NULL,348 &format);349 if (ret < 0)350 return ret;351 352 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",353 __func__, format.format.width, format.format.height,354 format.format.code, BRX_NAME(brx), brx->source_pad);355 356 if (format.format.width != drm_pipe->width ||357 format.format.height != drm_pipe->height) {358 dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);359 return -EPIPE;360 }361 362 return 0;363}364 365static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)366{367 return vsp1->drm->inputs[rpf->entity.index].zpos;368}369 370/* Setup the input side of the pipeline (RPFs and BRx). */371static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,372 struct vsp1_pipeline *pipe)373{374 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);375 struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };376 struct vsp1_entity *uif;377 bool use_uif = false;378 struct vsp1_brx *brx;379 unsigned int i;380 int ret;381 382 /* Count the number of enabled inputs and sort them by Z-order. */383 pipe->num_inputs = 0;384 385 for (i = 0; i < vsp1->info->rpf_count; ++i) {386 struct vsp1_rwpf *rpf = vsp1->rpf[i];387 unsigned int j;388 389 if (!pipe->inputs[i])390 continue;391 392 /* Insert the RPF in the sorted RPFs array. */393 for (j = pipe->num_inputs++; j > 0; --j) {394 if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))395 break;396 inputs[j] = inputs[j-1];397 }398 399 inputs[j] = rpf;400 }401 402 /*403 * Setup the BRx. This must be done before setting up the RPF input404 * pipelines as the BRx sink compose rectangles depend on the BRx source405 * format.406 */407 ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);408 if (ret < 0) {409 dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,410 BRX_NAME(pipe->brx));411 return ret;412 }413 414 brx = to_brx(&pipe->brx->subdev);415 416 /* Setup the RPF input pipeline for every enabled input. */417 for (i = 0; i < pipe->brx->source_pad; ++i) {418 struct vsp1_rwpf *rpf = inputs[i];419 420 if (!rpf) {421 brx->inputs[i].rpf = NULL;422 continue;423 }424 425 if (!rpf->entity.pipe) {426 rpf->entity.pipe = pipe;427 list_add(&rpf->entity.list_pipe, &pipe->entities);428 }429 430 brx->inputs[i].rpf = rpf;431 rpf->brx_input = i;432 rpf->entity.sink = pipe->brx;433 rpf->entity.sink_pad = i;434 435 dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",436 __func__, rpf->entity.index, BRX_NAME(pipe->brx), i);437 438 uif = drm_pipe->crc.source == VSP1_DU_CRC_PLANE &&439 drm_pipe->crc.index == i ? drm_pipe->uif : NULL;440 if (uif)441 use_uif = true;442 ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);443 if (ret < 0) {444 dev_err(vsp1->dev,445 "%s: failed to setup RPF.%u\n",446 __func__, rpf->entity.index);447 return ret;448 }449 }450 451 /* Insert and configure the UIF at the BRx output if available. */452 uif = drm_pipe->crc.source == VSP1_DU_CRC_OUTPUT ? drm_pipe->uif : NULL;453 if (uif)454 use_uif = true;455 ret = vsp1_du_insert_uif(vsp1, pipe, uif,456 pipe->brx, pipe->brx->source_pad,457 &pipe->output->entity, 0);458 if (ret < 0)459 dev_err(vsp1->dev, "%s: failed to setup UIF after %s\n",460 __func__, BRX_NAME(pipe->brx));461 462 /* If the DRM pipe does not have a UIF there is nothing we can update. */463 if (!drm_pipe->uif)464 return 0;465 466 /*467 * If the UIF is not in use schedule it for removal by setting its pipe468 * pointer to NULL, vsp1_du_pipeline_configure() will remove it from the469 * hardware pipeline and from the pipeline's list of entities. Otherwise470 * make sure it is present in the pipeline's list of entities if it471 * wasn't already.472 */473 if (!use_uif) {474 drm_pipe->uif->pipe = NULL;475 } else if (!drm_pipe->uif->pipe) {476 drm_pipe->uif->pipe = pipe;477 list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);478 }479 480 return 0;481}482 483/* Setup the output side of the pipeline (WPF and LIF). */484static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,485 struct vsp1_pipeline *pipe)486{487 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);488 struct v4l2_subdev_format format = {489 .which = V4L2_SUBDEV_FORMAT_ACTIVE,490 };491 int ret;492 493 format.pad = RWPF_PAD_SINK;494 format.format.width = drm_pipe->width;495 format.format.height = drm_pipe->height;496 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;497 format.format.field = V4L2_FIELD_NONE;498 499 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,500 &format);501 if (ret < 0)502 return ret;503 504 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",505 __func__, format.format.width, format.format.height,506 format.format.code, pipe->output->entity.index);507 508 format.pad = RWPF_PAD_SOURCE;509 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,510 &format);511 if (ret < 0)512 return ret;513 514 dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",515 __func__, format.format.width, format.format.height,516 format.format.code, pipe->output->entity.index);517 518 format.pad = LIF_PAD_SINK;519 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,520 &format);521 if (ret < 0)522 return ret;523 524 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",525 __func__, format.format.width, format.format.height,526 format.format.code, pipe->lif->index);527 528 /*529 * Verify that the format at the output of the pipeline matches the530 * requested frame size and media bus code.531 */532 if (format.format.width != drm_pipe->width ||533 format.format.height != drm_pipe->height ||534 format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {535 dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,536 pipe->lif->index);537 return -EPIPE;538 }539 540 return 0;541}542 543/* Configure all entities in the pipeline. */544static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)545{546 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);547 struct vsp1_entity *entity;548 struct vsp1_entity *next;549 struct vsp1_dl_list *dl;550 struct vsp1_dl_body *dlb;551 unsigned int dl_flags = 0;552 553 vsp1_pipeline_calculate_partition(pipe, &pipe->part_table[0],554 drm_pipe->width, 0);555 556 if (drm_pipe->force_brx_release)557 dl_flags |= VSP1_DL_FRAME_END_INTERNAL;558 if (pipe->output->writeback)559 dl_flags |= VSP1_DL_FRAME_END_WRITEBACK;560 561 dl = vsp1_dl_list_get(pipe->output->dlm);562 dlb = vsp1_dl_list_get_body0(dl);563 564 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {565 /* Disconnect unused entities from the pipeline. */566 if (!entity->pipe) {567 vsp1_dl_body_write(dlb, entity->route->reg,568 VI6_DPR_NODE_UNUSED);569 570 entity->sink = NULL;571 list_del(&entity->list_pipe);572 573 continue;574 }575 576 vsp1_entity_route_setup(entity, pipe, dlb);577 vsp1_entity_configure_stream(entity, entity->state, pipe,578 dl, dlb);579 vsp1_entity_configure_frame(entity, pipe, dl, dlb);580 vsp1_entity_configure_partition(entity, pipe,581 &pipe->part_table[0], dl, dlb);582 }583 584 vsp1_dl_list_commit(dl, dl_flags);585}586 587static int vsp1_du_pipeline_set_rwpf_format(struct vsp1_device *vsp1,588 struct vsp1_rwpf *rwpf,589 u32 pixelformat, unsigned int pitch)590{591 const struct vsp1_format_info *fmtinfo;592 unsigned int chroma_hsub;593 594 fmtinfo = vsp1_get_format_info(vsp1, pixelformat);595 if (!fmtinfo) {596 dev_dbg(vsp1->dev, "Unsupported pixel format %08x\n",597 pixelformat);598 return -EINVAL;599 }600 601 /*602 * Only formats with three planes can affect the chroma planes pitch.603 * All formats with two planes have a horizontal subsampling value of 2,604 * but combine U and V in a single chroma plane, which thus results in605 * the luma plane and chroma plane having the same pitch.606 */607 chroma_hsub = (fmtinfo->planes == 3) ? fmtinfo->hsub : 1;608 609 rwpf->fmtinfo = fmtinfo;610 rwpf->format.num_planes = fmtinfo->planes;611 rwpf->format.plane_fmt[0].bytesperline = pitch;612 rwpf->format.plane_fmt[1].bytesperline = pitch / chroma_hsub;613 614 return 0;615}616 617/* -----------------------------------------------------------------------------618 * DU Driver API619 */620 621int vsp1_du_init(struct device *dev)622{623 struct vsp1_device *vsp1 = dev_get_drvdata(dev);624 625 if (!vsp1)626 return -EPROBE_DEFER;627 628 return 0;629}630EXPORT_SYMBOL_GPL(vsp1_du_init);631 632/**633 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline634 * @dev: the VSP device635 * @pipe_index: the DRM pipeline index636 * @cfg: the LIF configuration637 *638 * Configure the output part of VSP DRM pipeline for the given frame @cfg.width639 * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and640 * source pads, and the LIF sink pad.641 *642 * The @pipe_index argument selects which DRM pipeline to setup. The number of643 * available pipelines depend on the VSP instance.644 *645 * As the media bus code on the blend unit source pad is conditioned by the646 * configuration of its sink 0 pad, we also set up the formats on all blend unit647 * sinks, even if the configuration will be overwritten later by648 * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to649 * a well defined state.650 *651 * Return 0 on success or a negative error code on failure.652 */653int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,654 const struct vsp1_du_lif_config *cfg)655{656 struct vsp1_device *vsp1 = dev_get_drvdata(dev);657 struct vsp1_drm_pipeline *drm_pipe;658 struct vsp1_pipeline *pipe;659 unsigned long flags;660 unsigned int i;661 int ret;662 663 if (pipe_index >= vsp1->info->lif_count)664 return -EINVAL;665 666 drm_pipe = &vsp1->drm->pipe[pipe_index];667 pipe = &drm_pipe->pipe;668 669 if (!cfg) {670 struct vsp1_brx *brx;671 672 mutex_lock(&vsp1->drm->lock);673 674 brx = to_brx(&pipe->brx->subdev);675 676 /*677 * NULL configuration means the CRTC is being disabled, stop678 * the pipeline and turn the light off.679 */680 ret = vsp1_pipeline_stop(pipe);681 if (ret == -ETIMEDOUT)682 dev_err(vsp1->dev, "DRM pipeline stop timeout\n");683 684 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {685 struct vsp1_rwpf *rpf = pipe->inputs[i];686 687 if (!rpf)688 continue;689 690 /*691 * Remove the RPF from the pipe and the list of BRx692 * inputs.693 */694 WARN_ON(!rpf->entity.pipe);695 rpf->entity.pipe = NULL;696 list_del(&rpf->entity.list_pipe);697 pipe->inputs[i] = NULL;698 699 brx->inputs[rpf->brx_input].rpf = NULL;700 }701 702 drm_pipe->du_complete = NULL;703 pipe->num_inputs = 0;704 705 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",706 __func__, pipe->lif->index,707 BRX_NAME(pipe->brx));708 709 list_del(&pipe->brx->list_pipe);710 pipe->brx->pipe = NULL;711 pipe->brx = NULL;712 713 mutex_unlock(&vsp1->drm->lock);714 715 vsp1_dlm_reset(pipe->output->dlm);716 vsp1_device_put(vsp1);717 718 dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);719 720 return 0;721 }722 723 /* Reset the underrun counter */724 pipe->underrun_count = 0;725 726 drm_pipe->width = cfg->width;727 drm_pipe->height = cfg->height;728 pipe->interlaced = cfg->interlaced;729 730 dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u%s\n",731 __func__, pipe_index, cfg->width, cfg->height,732 pipe->interlaced ? "i" : "");733 734 mutex_lock(&vsp1->drm->lock);735 736 /* Setup formats through the pipeline. */737 ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);738 if (ret < 0)739 goto unlock;740 741 ret = vsp1_du_pipeline_setup_output(vsp1, pipe);742 if (ret < 0)743 goto unlock;744 745 vsp1_pipeline_dump(pipe, "LIF setup");746 747 /* Enable the VSP1. */748 ret = vsp1_device_get(vsp1);749 if (ret < 0)750 goto unlock;751 752 /*753 * Register a callback to allow us to notify the DRM driver of frame754 * completion events.755 */756 drm_pipe->du_complete = cfg->callback;757 drm_pipe->du_private = cfg->callback_data;758 759 /* Disable the display interrupts. */760 vsp1_write(vsp1, VI6_DISP_IRQ_STA(pipe_index), 0);761 vsp1_write(vsp1, VI6_DISP_IRQ_ENB(pipe_index), 0);762 763 /* Configure all entities in the pipeline. */764 vsp1_du_pipeline_configure(pipe);765 766unlock:767 mutex_unlock(&vsp1->drm->lock);768 769 if (ret < 0)770 return ret;771 772 /* Start the pipeline. */773 spin_lock_irqsave(&pipe->irqlock, flags);774 vsp1_pipeline_run(pipe);775 spin_unlock_irqrestore(&pipe->irqlock, flags);776 777 dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);778 779 return 0;780}781EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);782 783/**784 * vsp1_du_atomic_begin - Prepare for an atomic update785 * @dev: the VSP device786 * @pipe_index: the DRM pipeline index787 */788void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)789{790}791EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);792 793/**794 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline795 * @dev: the VSP device796 * @pipe_index: the DRM pipeline index797 * @rpf_index: index of the RPF to setup (0-based)798 * @cfg: the RPF configuration799 *800 * Configure the VSP to perform image composition through RPF @rpf_index as801 * described by the @cfg configuration. The image to compose is referenced by802 * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst803 * composition rectangle. The Z-order is configurable with higher @zpos values804 * displayed on top.805 *806 * If the @cfg configuration is NULL, the RPF will be disabled. Calling the807 * function on a disabled RPF is allowed.808 *809 * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat810 * value. The memory pitch is configurable to allow for padding at end of lines,811 * or simply for images that extend beyond the crop rectangle boundaries. The812 * @cfg.pitch value is expressed in bytes and applies to all planes for813 * multiplanar formats.814 *815 * The source memory buffer is referenced by the DMA address of its planes in816 * the @cfg.mem array. Up to two planes are supported. The second plane DMA817 * address is ignored for formats using a single plane.818 *819 * This function isn't reentrant, the caller needs to serialize calls.820 *821 * Return 0 on success or a negative error code on failure.822 */823int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,824 unsigned int rpf_index,825 const struct vsp1_du_atomic_config *cfg)826{827 struct vsp1_device *vsp1 = dev_get_drvdata(dev);828 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];829 struct vsp1_rwpf *rpf;830 int ret;831 832 if (rpf_index >= vsp1->info->rpf_count)833 return -EINVAL;834 835 rpf = vsp1->rpf[rpf_index];836 837 if (!cfg) {838 dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,839 rpf_index);840 841 /*842 * Remove the RPF from the pipeline's inputs. Keep it in the843 * pipeline's entity list to let vsp1_du_pipeline_configure()844 * remove it from the hardware pipeline.845 */846 rpf->entity.pipe = NULL;847 drm_pipe->pipe.inputs[rpf_index] = NULL;848 return 0;849 }850 851 dev_dbg(vsp1->dev,852 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n",853 __func__, rpf_index,854 cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height,855 cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height,856 cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1],857 &cfg->mem[2], cfg->zpos);858 859 /*860 * Store the format, stride, memory buffer address, crop and compose861 * rectangles and Z-order position and for the input.862 */863 ret = vsp1_du_pipeline_set_rwpf_format(vsp1, rpf, cfg->pixelformat,864 cfg->pitch);865 if (ret < 0)866 return ret;867 868 rpf->alpha = cfg->alpha;869 870 rpf->mem.addr[0] = cfg->mem[0];871 rpf->mem.addr[1] = cfg->mem[1];872 rpf->mem.addr[2] = cfg->mem[2];873 874 rpf->format.flags = cfg->premult ? V4L2_PIX_FMT_FLAG_PREMUL_ALPHA : 0;875 876 vsp1->drm->inputs[rpf_index].crop = cfg->src;877 vsp1->drm->inputs[rpf_index].compose = cfg->dst;878 vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;879 880 drm_pipe->pipe.inputs[rpf_index] = rpf;881 882 return 0;883}884EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);885 886/**887 * vsp1_du_atomic_flush - Commit an atomic update888 * @dev: the VSP device889 * @pipe_index: the DRM pipeline index890 * @cfg: atomic pipe configuration891 */892void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,893 const struct vsp1_du_atomic_pipe_config *cfg)894{895 struct vsp1_device *vsp1 = dev_get_drvdata(dev);896 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];897 struct vsp1_pipeline *pipe = &drm_pipe->pipe;898 int ret;899 900 drm_pipe->crc = cfg->crc;901 902 mutex_lock(&vsp1->drm->lock);903 904 if (cfg->writeback.pixelformat) {905 const struct vsp1_du_writeback_config *wb_cfg = &cfg->writeback;906 907 ret = vsp1_du_pipeline_set_rwpf_format(vsp1, pipe->output,908 wb_cfg->pixelformat,909 wb_cfg->pitch);910 if (WARN_ON(ret < 0))911 goto done;912 913 pipe->output->mem.addr[0] = wb_cfg->mem[0];914 pipe->output->mem.addr[1] = wb_cfg->mem[1];915 pipe->output->mem.addr[2] = wb_cfg->mem[2];916 pipe->output->writeback = true;917 }918 919 vsp1_du_pipeline_setup_inputs(vsp1, pipe);920 921 vsp1_pipeline_dump(pipe, "atomic update");922 923 vsp1_du_pipeline_configure(pipe);924 925done:926 mutex_unlock(&vsp1->drm->lock);927}928EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);929 930int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt)931{932 struct vsp1_device *vsp1 = dev_get_drvdata(dev);933 934 /*935 * As all the buffers allocated by the DU driver are coherent, we can936 * skip cache sync. This will need to be revisited when support for937 * non-coherent buffers will be added to the DU driver.938 */939 return dma_map_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE,940 DMA_ATTR_SKIP_CPU_SYNC);941}942EXPORT_SYMBOL_GPL(vsp1_du_map_sg);943 944void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt)945{946 struct vsp1_device *vsp1 = dev_get_drvdata(dev);947 948 dma_unmap_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE,949 DMA_ATTR_SKIP_CPU_SYNC);950}951EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);952 953/* -----------------------------------------------------------------------------954 * Initialization955 */956 957int vsp1_drm_init(struct vsp1_device *vsp1)958{959 unsigned int i;960 961 vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);962 if (!vsp1->drm)963 return -ENOMEM;964 965 mutex_init(&vsp1->drm->lock);966 967 /* Create one DRM pipeline per LIF. */968 for (i = 0; i < vsp1->info->lif_count; ++i) {969 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];970 struct vsp1_pipeline *pipe = &drm_pipe->pipe;971 972 init_waitqueue_head(&drm_pipe->wait_queue);973 974 vsp1_pipeline_init(pipe);975 976 pipe->partitions = 1;977 pipe->part_table = &drm_pipe->partition;978 979 pipe->frame_end = vsp1_du_pipeline_frame_end;980 981 /*982 * The output side of the DRM pipeline is static, add the983 * corresponding entities manually.984 */985 pipe->output = vsp1->wpf[i];986 pipe->lif = &vsp1->lif[i]->entity;987 988 pipe->output->entity.pipe = pipe;989 pipe->output->entity.sink = pipe->lif;990 pipe->output->entity.sink_pad = 0;991 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);992 993 pipe->lif->pipe = pipe;994 list_add_tail(&pipe->lif->list_pipe, &pipe->entities);995 996 /*997 * CRC computation is initially disabled, don't add the UIF to998 * the pipeline.999 */1000 if (i < vsp1->info->uif_count)1001 drm_pipe->uif = &vsp1->uif[i]->entity;1002 }1003 1004 /* Disable all RPFs initially. */1005 for (i = 0; i < vsp1->info->rpf_count; ++i) {1006 struct vsp1_rwpf *input = vsp1->rpf[i];1007 1008 INIT_LIST_HEAD(&input->entity.list_pipe);1009 }1010 1011 return 0;1012}1013 1014void vsp1_drm_cleanup(struct vsp1_device *vsp1)1015{1016 mutex_destroy(&vsp1->drm->lock);1017}1018