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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd4 * Author: Jacob Chen <jacob-chen@iotwrt.com>5 */6#ifndef __RGA_HW_H__7#define __RGA_HW_H__8 9#define RGA_CMDBUF_SIZE 0x2010 11/* Hardware limits */12#define MAX_WIDTH 819213#define MAX_HEIGHT 819214 15#define MIN_WIDTH 3416#define MIN_HEIGHT 3417 18#define DEFAULT_WIDTH 10019#define DEFAULT_HEIGHT 10020 21#define RGA_TIMEOUT 50022 23/* Registers address */24#define RGA_SYS_CTRL 0x000025#define RGA_CMD_CTRL 0x000426#define RGA_CMD_BASE 0x000827#define RGA_INT 0x001028#define RGA_MMU_CTRL0 0x001429#define RGA_VERSION_INFO 0x002830 31#define RGA_MODE_BASE_REG 0x010032#define RGA_MODE_MAX_REG 0x017C33 34#define RGA_MODE_CTRL 0x010035#define RGA_SRC_INFO 0x010436#define RGA_SRC_Y_RGB_BASE_ADDR 0x010837#define RGA_SRC_CB_BASE_ADDR 0x010c38#define RGA_SRC_CR_BASE_ADDR 0x011039#define RGA_SRC1_RGB_BASE_ADDR 0x011440#define RGA_SRC_VIR_INFO 0x011841#define RGA_SRC_ACT_INFO 0x011c42#define RGA_SRC_X_FACTOR 0x012043#define RGA_SRC_Y_FACTOR 0x012444#define RGA_SRC_BG_COLOR 0x012845#define RGA_SRC_FG_COLOR 0x012c46#define RGA_SRC_TR_COLOR0 0x013047#define RGA_SRC_TR_COLOR1 0x013448 49#define RGA_DST_INFO 0x013850#define RGA_DST_Y_RGB_BASE_ADDR 0x013c51#define RGA_DST_CB_BASE_ADDR 0x014052#define RGA_DST_CR_BASE_ADDR 0x014453#define RGA_DST_VIR_INFO 0x014854#define RGA_DST_ACT_INFO 0x014c55 56#define RGA_ALPHA_CTRL0 0x015057#define RGA_ALPHA_CTRL1 0x015458#define RGA_FADING_CTRL 0x015859#define RGA_PAT_CON 0x015c60#define RGA_ROP_CON0 0x016061#define RGA_ROP_CON1 0x016462#define RGA_MASK_BASE 0x016863 64#define RGA_MMU_CTRL1 0x016C65#define RGA_MMU_SRC_BASE 0x017066#define RGA_MMU_SRC1_BASE 0x017467#define RGA_MMU_DST_BASE 0x017868 69/* Registers value */70#define RGA_MODE_RENDER_BITBLT 071#define RGA_MODE_RENDER_COLOR_PALETTE 172#define RGA_MODE_RENDER_RECTANGLE_FILL 273#define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 374 75#define RGA_MODE_BITBLT_MODE_SRC_TO_DST 076#define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 177 78#define RGA_MODE_CF_ROP4_SOLID 079#define RGA_MODE_CF_ROP4_PATTERN 180 81#define RGA_COLOR_FMT_ABGR8888 082#define RGA_COLOR_FMT_XBGR8888 183#define RGA_COLOR_FMT_RGB888 284#define RGA_COLOR_FMT_BGR565 485#define RGA_COLOR_FMT_ABGR1555 586#define RGA_COLOR_FMT_ABGR4444 687#define RGA_COLOR_FMT_YUV422SP 888#define RGA_COLOR_FMT_YUV422P 989#define RGA_COLOR_FMT_YUV420SP 1090#define RGA_COLOR_FMT_YUV420P 1191/* SRC_COLOR Palette */92#define RGA_COLOR_FMT_CP_1BPP 1293#define RGA_COLOR_FMT_CP_2BPP 1394#define RGA_COLOR_FMT_CP_4BPP 1495#define RGA_COLOR_FMT_CP_8BPP 1596#define RGA_COLOR_FMT_MASK 1597 98#define RGA_COLOR_FMT_IS_YUV(fmt) \99 (((fmt) >= RGA_COLOR_FMT_YUV422SP) && ((fmt) < RGA_COLOR_FMT_CP_1BPP))100#define RGA_COLOR_FMT_IS_RGB(fmt) \101 ((fmt) < RGA_COLOR_FMT_YUV422SP)102 103#define RGA_COLOR_NONE_SWAP 0104#define RGA_COLOR_RB_SWAP 1105#define RGA_COLOR_ALPHA_SWAP 2106#define RGA_COLOR_UV_SWAP 4107 108#define RGA_SRC_CSC_MODE_BYPASS 0109#define RGA_SRC_CSC_MODE_BT601_R0 1110#define RGA_SRC_CSC_MODE_BT601_R1 2111#define RGA_SRC_CSC_MODE_BT709_R0 3112#define RGA_SRC_CSC_MODE_BT709_R1 4113 114#define RGA_SRC_ROT_MODE_0_DEGREE 0115#define RGA_SRC_ROT_MODE_90_DEGREE 1116#define RGA_SRC_ROT_MODE_180_DEGREE 2117#define RGA_SRC_ROT_MODE_270_DEGREE 3118 119#define RGA_SRC_MIRR_MODE_NO 0120#define RGA_SRC_MIRR_MODE_X 1121#define RGA_SRC_MIRR_MODE_Y 2122#define RGA_SRC_MIRR_MODE_X_Y 3123 124#define RGA_SRC_HSCL_MODE_NO 0125#define RGA_SRC_HSCL_MODE_DOWN 1126#define RGA_SRC_HSCL_MODE_UP 2127 128#define RGA_SRC_VSCL_MODE_NO 0129#define RGA_SRC_VSCL_MODE_DOWN 1130#define RGA_SRC_VSCL_MODE_UP 2131 132#define RGA_SRC_TRANS_ENABLE_R 1133#define RGA_SRC_TRANS_ENABLE_G 2134#define RGA_SRC_TRANS_ENABLE_B 4135#define RGA_SRC_TRANS_ENABLE_A 8136 137#define RGA_SRC_BIC_COE_SELEC_CATROM 0138#define RGA_SRC_BIC_COE_SELEC_MITCHELL 1139#define RGA_SRC_BIC_COE_SELEC_HERMITE 2140#define RGA_SRC_BIC_COE_SELEC_BSPLINE 3141 142#define RGA_DST_DITHER_MODE_888_TO_666 0143#define RGA_DST_DITHER_MODE_888_TO_565 1144#define RGA_DST_DITHER_MODE_888_TO_555 2145#define RGA_DST_DITHER_MODE_888_TO_444 3146 147#define RGA_DST_CSC_MODE_BYPASS 0148#define RGA_DST_CSC_MODE_BT601_R0 1149#define RGA_DST_CSC_MODE_BT601_R1 2150#define RGA_DST_CSC_MODE_BT709_R0 3151 152#define RGA_ALPHA_ROP_MODE_2 0153#define RGA_ALPHA_ROP_MODE_3 1154#define RGA_ALPHA_ROP_MODE_4 2155 156#define RGA_ALPHA_SELECT_ALPHA 0157#define RGA_ALPHA_SELECT_ROP 1158 159#define RGA_ALPHA_MASK_BIG_ENDIAN 0160#define RGA_ALPHA_MASK_LITTLE_ENDIAN 1161 162#define RGA_ALPHA_NORMAL 0163#define RGA_ALPHA_REVERSE 1164 165#define RGA_ALPHA_BLEND_GLOBAL 0166#define RGA_ALPHA_BLEND_NORMAL 1167#define RGA_ALPHA_BLEND_MULTIPLY 2168 169#define RGA_ALPHA_CAL_CUT 0170#define RGA_ALPHA_CAL_NORMAL 1171 172#define RGA_ALPHA_FACTOR_ZERO 0173#define RGA_ALPHA_FACTOR_ONE 1174#define RGA_ALPHA_FACTOR_OTHER 2175#define RGA_ALPHA_FACTOR_OTHER_REVERSE 3176#define RGA_ALPHA_FACTOR_SELF 4177 178#define RGA_ALPHA_COLOR_NORMAL 0179#define RGA_ALPHA_COLOR_MULTIPLY_CAL 1180 181/* Registers union */182union rga_mode_ctrl {183 unsigned int val;184 struct {185 /* [0:2] */186 unsigned int render:3;187 /* [3:6] */188 unsigned int bitblt:1;189 unsigned int cf_rop4_pat:1;190 unsigned int alpha_zero_key:1;191 unsigned int gradient_sat:1;192 /* [7:31] */193 unsigned int reserved:25;194 } data;195};196 197union rga_src_info {198 unsigned int val;199 struct {200 /* [0:3] */201 unsigned int format:4;202 /* [4:7] */203 unsigned int swap:3;204 unsigned int cp_endian:1;205 /* [8:17] */206 unsigned int csc_mode:2;207 unsigned int rot_mode:2;208 unsigned int mir_mode:2;209 unsigned int hscl_mode:2;210 unsigned int vscl_mode:2;211 /* [18:22] */212 unsigned int trans_mode:1;213 unsigned int trans_enable:4;214 /* [23:25] */215 unsigned int dither_up_en:1;216 unsigned int bic_coe_sel:2;217 /* [26:31] */218 unsigned int reserved:6;219 } data;220};221 222union rga_src_vir_info {223 unsigned int val;224 struct {225 /* [0:15] */226 unsigned int vir_width:15;227 unsigned int reserved:1;228 /* [16:25] */229 unsigned int vir_stride:10;230 /* [26:31] */231 unsigned int reserved1:6;232 } data;233};234 235union rga_src_act_info {236 unsigned int val;237 struct {238 /* [0:15] */239 unsigned int act_width:13;240 unsigned int reserved:3;241 /* [16:31] */242 unsigned int act_height:13;243 unsigned int reserved1:3;244 } data;245};246 247union rga_src_x_factor {248 unsigned int val;249 struct {250 /* [0:15] */251 unsigned int down_scale_factor:16;252 /* [16:31] */253 unsigned int up_scale_factor:16;254 } data;255};256 257union rga_src_y_factor {258 unsigned int val;259 struct {260 /* [0:15] */261 unsigned int down_scale_factor:16;262 /* [16:31] */263 unsigned int up_scale_factor:16;264 } data;265};266 267/* Alpha / Red / Green / Blue */268union rga_src_cp_gr_color {269 unsigned int val;270 struct {271 /* [0:15] */272 unsigned int gradient_x:16;273 /* [16:31] */274 unsigned int gradient_y:16;275 } data;276};277 278union rga_src_transparency_color0 {279 unsigned int val;280 struct {281 /* [0:7] */282 unsigned int trans_rmin:8;283 /* [8:15] */284 unsigned int trans_gmin:8;285 /* [16:23] */286 unsigned int trans_bmin:8;287 /* [24:31] */288 unsigned int trans_amin:8;289 } data;290};291 292union rga_src_transparency_color1 {293 unsigned int val;294 struct {295 /* [0:7] */296 unsigned int trans_rmax:8;297 /* [8:15] */298 unsigned int trans_gmax:8;299 /* [16:23] */300 unsigned int trans_bmax:8;301 /* [24:31] */302 unsigned int trans_amax:8;303 } data;304};305 306union rga_dst_info {307 unsigned int val;308 struct {309 /* [0:3] */310 unsigned int format:4;311 /* [4:6] */312 unsigned int swap:3;313 /* [7:9] */314 unsigned int src1_format:3;315 /* [10:11] */316 unsigned int src1_swap:2;317 /* [12:15] */318 unsigned int dither_up_en:1;319 unsigned int dither_down_en:1;320 unsigned int dither_down_mode:2;321 /* [16:18] */322 unsigned int csc_mode:2;323 unsigned int csc_clip:1;324 /* [19:31] */325 unsigned int reserved:13;326 } data;327};328 329union rga_dst_vir_info {330 unsigned int val;331 struct {332 /* [0:15] */333 unsigned int vir_stride:15;334 unsigned int reserved:1;335 /* [16:31] */336 unsigned int src1_vir_stride:15;337 unsigned int reserved1:1;338 } data;339};340 341union rga_dst_act_info {342 unsigned int val;343 struct {344 /* [0:15] */345 unsigned int act_width:12;346 unsigned int reserved:4;347 /* [16:31] */348 unsigned int act_height:12;349 unsigned int reserved1:4;350 } data;351};352 353union rga_alpha_ctrl0 {354 unsigned int val;355 struct {356 /* [0:3] */357 unsigned int rop_en:1;358 unsigned int rop_select:1;359 unsigned int rop_mode:2;360 /* [4:11] */361 unsigned int src_fading_val:8;362 /* [12:20] */363 unsigned int dst_fading_val:8;364 unsigned int mask_endian:1;365 /* [21:31] */366 unsigned int reserved:11;367 } data;368};369 370union rga_alpha_ctrl1 {371 unsigned int val;372 struct {373 /* [0:1] */374 unsigned int dst_color_m0:1;375 unsigned int src_color_m0:1;376 /* [2:7] */377 unsigned int dst_factor_m0:3;378 unsigned int src_factor_m0:3;379 /* [8:9] */380 unsigned int dst_alpha_cal_m0:1;381 unsigned int src_alpha_cal_m0:1;382 /* [10:13] */383 unsigned int dst_blend_m0:2;384 unsigned int src_blend_m0:2;385 /* [14:15] */386 unsigned int dst_alpha_m0:1;387 unsigned int src_alpha_m0:1;388 /* [16:21] */389 unsigned int dst_factor_m1:3;390 unsigned int src_factor_m1:3;391 /* [22:23] */392 unsigned int dst_alpha_cal_m1:1;393 unsigned int src_alpha_cal_m1:1;394 /* [24:27] */395 unsigned int dst_blend_m1:2;396 unsigned int src_blend_m1:2;397 /* [28:29] */398 unsigned int dst_alpha_m1:1;399 unsigned int src_alpha_m1:1;400 /* [30:31] */401 unsigned int reserved:2;402 } data;403};404 405union rga_fading_ctrl {406 unsigned int val;407 struct {408 /* [0:7] */409 unsigned int fading_offset_r:8;410 /* [8:15] */411 unsigned int fading_offset_g:8;412 /* [16:23] */413 unsigned int fading_offset_b:8;414 /* [24:31] */415 unsigned int fading_en:1;416 unsigned int reserved:7;417 } data;418};419 420union rga_pat_con {421 unsigned int val;422 struct {423 /* [0:7] */424 unsigned int width:8;425 /* [8:15] */426 unsigned int height:8;427 /* [16:23] */428 unsigned int offset_x:8;429 /* [24:31] */430 unsigned int offset_y:8;431 } data;432};433 434#endif435