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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.4 */5 6#ifndef FIMC_CORE_H_7#define FIMC_CORE_H_8 9/*#define DEBUG*/10 11#include <linux/platform_device.h>12#include <linux/regmap.h>13#include <linux/sched.h>14#include <linux/spinlock.h>15#include <linux/mfd/syscon.h>16#include <linux/types.h>17#include <linux/videodev2.h>18#include <linux/io.h>19#include <linux/sizes.h>20 21#include <media/media-entity.h>22#include <media/videobuf2-v4l2.h>23#include <media/v4l2-ctrls.h>24#include <media/v4l2-device.h>25#include <media/v4l2-mem2mem.h>26#include <media/v4l2-mediabus.h>27#include <media/drv-intf/exynos-fimc.h>28 29#define dbg(fmt, args...) \30 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)31 32/* Time to wait for next frame VSYNC interrupt while stopping operation. */33#define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)34#define MAX_FIMC_CLOCKS 235#define FIMC_DRIVER_NAME "exynos4-fimc"36#define FIMC_MAX_DEVS 437#define FIMC_MAX_OUT_BUFS 438#define SCALER_MAX_HRATIO 6439#define SCALER_MAX_VRATIO 6440#define DMA_MIN_SIZE 841#define FIMC_CAMIF_MAX_HEIGHT 0x200042#define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)43#define FIMC_MAX_PLANES 344#define FIMC_PIX_LIMITS_MAX 445#define FIMC_DEF_MIN_SIZE 1646#define FIMC_DEF_HEIGHT_ALIGN 247#define FIMC_DEF_HOR_OFFS_ALIGN 148#define FIMC_DEFAULT_WIDTH 64049#define FIMC_DEFAULT_HEIGHT 48050 51/* indices to the clocks array */52enum {53 CLK_BUS,54 CLK_GATE,55};56 57enum fimc_dev_flags {58 ST_LPM,59 /* m2m node */60 ST_M2M_RUN,61 ST_M2M_PEND,62 ST_M2M_SUSPENDING,63 ST_M2M_SUSPENDED,64 /* capture node */65 ST_CAPT_PEND,66 ST_CAPT_RUN,67 ST_CAPT_STREAM,68 ST_CAPT_ISP_STREAM,69 ST_CAPT_SUSPENDED,70 ST_CAPT_SHUT,71 ST_CAPT_BUSY,72 ST_CAPT_APPLY_CFG,73 ST_CAPT_JPEG,74};75 76#define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)77#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)78 79#define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)80#define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)81#define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)82 83enum fimc_datapath {84 FIMC_IO_NONE,85 FIMC_IO_CAMERA,86 FIMC_IO_DMA,87 FIMC_IO_LCDFIFO,88 FIMC_IO_WRITEBACK,89 FIMC_IO_ISP,90};91 92enum fimc_color_fmt {93 FIMC_FMT_RGB444 = 0x10,94 FIMC_FMT_RGB555,95 FIMC_FMT_RGB565,96 FIMC_FMT_RGB666,97 FIMC_FMT_RGB888,98 FIMC_FMT_RGB30_LOCAL,99 FIMC_FMT_YCBCR420 = 0x20,100 FIMC_FMT_YCBYCR422,101 FIMC_FMT_YCRYCB422,102 FIMC_FMT_CBYCRY422,103 FIMC_FMT_CRYCBY422,104 FIMC_FMT_YCBCR444_LOCAL,105 FIMC_FMT_RAW8 = 0x40,106 FIMC_FMT_RAW10,107 FIMC_FMT_RAW12,108 FIMC_FMT_JPEG = 0x80,109 FIMC_FMT_YUYV_JPEG = 0x100,110};111 112#define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))113#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))114 115#define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \116 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)117 118/* The hardware context state. */119#define FIMC_PARAMS (1 << 0)120#define FIMC_COMPOSE (1 << 1)121#define FIMC_CTX_M2M (1 << 16)122#define FIMC_CTX_CAP (1 << 17)123#define FIMC_CTX_SHUT (1 << 18)124 125/* Image conversion flags */126#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)127#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)128#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)129#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)130#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)131#define FIMC_SCAN_MODE_INTERLACED (1 << 2)132/*133 * YCbCr data dynamic range for RGB-YUV color conversion.134 * Y/Cb/Cr: (0 ~ 255) */135#define FIMC_COLOR_RANGE_WIDE (0 << 3)136/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */137#define FIMC_COLOR_RANGE_NARROW (1 << 3)138 139/**140 * struct fimc_dma_offset - pixel offset information for DMA141 * @y_h: y value horizontal offset142 * @y_v: y value vertical offset143 * @cb_h: cb value horizontal offset144 * @cb_v: cb value vertical offset145 * @cr_h: cr value horizontal offset146 * @cr_v: cr value vertical offset147 */148struct fimc_dma_offset {149 int y_h;150 int y_v;151 int cb_h;152 int cb_v;153 int cr_h;154 int cr_v;155};156 157/**158 * struct fimc_effect - color effect information159 * @type: effect type160 * @pat_cb: cr value when type is "arbitrary"161 * @pat_cr: cr value when type is "arbitrary"162 */163struct fimc_effect {164 u32 type;165 u8 pat_cb;166 u8 pat_cr;167};168 169/**170 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler171 * @scaleup_h: flag indicating scaling up horizontally172 * @scaleup_v: flag indicating scaling up vertically173 * @copy_mode: flag indicating transparent DMA transfer (no scaling174 * and color format conversion)175 * @enabled: flag indicating if the scaler is used176 * @hfactor: horizontal shift factor177 * @vfactor: vertical shift factor178 * @pre_hratio: horizontal ratio of the prescaler179 * @pre_vratio: vertical ratio of the prescaler180 * @pre_dst_width: the prescaler's destination width181 * @pre_dst_height: the prescaler's destination height182 * @main_hratio: the main scaler's horizontal ratio183 * @main_vratio: the main scaler's vertical ratio184 * @real_width: source pixel (width - offset)185 * @real_height: source pixel (height - offset)186 */187struct fimc_scaler {188 unsigned int scaleup_h:1;189 unsigned int scaleup_v:1;190 unsigned int copy_mode:1;191 unsigned int enabled:1;192 u32 hfactor;193 u32 vfactor;194 u32 pre_hratio;195 u32 pre_vratio;196 u32 pre_dst_width;197 u32 pre_dst_height;198 u32 main_hratio;199 u32 main_vratio;200 u32 real_width;201 u32 real_height;202};203 204/**205 * struct fimc_addr - the FIMC address set for DMA206 * @y: luminance plane address207 * @cb: Cb plane address208 * @cr: Cr plane address209 */210struct fimc_addr {211 u32 y;212 u32 cb;213 u32 cr;214};215 216/**217 * struct fimc_vid_buffer - the driver's video buffer218 * @vb: v4l vb2 buffer219 * @list: linked list structure for buffer queue220 * @addr: precalculated DMA address set221 * @index: buffer index for the output DMA engine222 */223struct fimc_vid_buffer {224 struct vb2_v4l2_buffer vb;225 struct list_head list;226 struct fimc_addr addr;227 int index;228};229 230/**231 * struct fimc_frame - source/target frame properties232 * @f_width: image full width (virtual screen size)233 * @f_height: image full height (virtual screen size)234 * @o_width: original image width as set by S_FMT235 * @o_height: original image height as set by S_FMT236 * @offs_h: image horizontal pixel offset237 * @offs_v: image vertical pixel offset238 * @width: image pixel width239 * @height: image pixel weight240 * @payload: image size in bytes (w x h x bpp)241 * @bytesperline: bytesperline value for each plane242 * @addr: image frame buffer DMA addresses243 * @dma_offset: DMA offset in bytes244 * @fmt: fimc color format pointer245 * @alpha: alpha value246 */247struct fimc_frame {248 u32 f_width;249 u32 f_height;250 u32 o_width;251 u32 o_height;252 u32 offs_h;253 u32 offs_v;254 u32 width;255 u32 height;256 unsigned int payload[VIDEO_MAX_PLANES];257 unsigned int bytesperline[VIDEO_MAX_PLANES];258 struct fimc_addr addr;259 struct fimc_dma_offset dma_offset;260 const struct fimc_fmt *fmt;261 u8 alpha;262};263 264/**265 * struct fimc_m2m_device - v4l2 memory-to-memory device data266 * @vfd: the video device node for v4l2 m2m mode267 * @m2m_dev: v4l2 memory-to-memory device data268 * @ctx: hardware context data269 * @refcnt: the reference counter270 */271struct fimc_m2m_device {272 struct video_device vfd;273 struct v4l2_m2m_dev *m2m_dev;274 struct fimc_ctx *ctx;275 int refcnt;276};277 278#define FIMC_SD_PAD_SINK_CAM 0279#define FIMC_SD_PAD_SINK_FIFO 1280#define FIMC_SD_PAD_SOURCE 2281#define FIMC_SD_PADS_NUM 3282 283/**284 * struct fimc_vid_cap - camera capture device information285 * @ctx: hardware context data286 * @subdev: subdev exposing the FIMC processing block287 * @ve: exynos video device entity structure288 * @vd_pad: fimc video capture node pad289 * @sd_pads: fimc video processing block pads290 * @ci_fmt: image format at the FIMC camera input (and the scaler output)291 * @wb_fmt: image format at the FIMC ISP Writeback input292 * @source_config: external image source related configuration structure293 * @pending_buf_q: the pending buffer queue head294 * @active_buf_q: the queue head of buffers scheduled in hardware295 * @vbq: the capture am video buffer queue296 * @active_buf_cnt: number of video buffers scheduled in hardware297 * @buf_index: index for managing the output DMA buffers298 * @frame_count: the frame counter for statistics299 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl300 * @streaming: is streaming in progress?301 * @input: capture input type, grp_id of the attached subdev302 * @user_subdev_api: true if subdevs are not configured by the host driver303 */304struct fimc_vid_cap {305 struct fimc_ctx *ctx;306 struct v4l2_subdev subdev;307 struct exynos_video_entity ve;308 struct media_pad vd_pad;309 struct media_pad sd_pads[FIMC_SD_PADS_NUM];310 struct v4l2_mbus_framefmt ci_fmt;311 struct v4l2_mbus_framefmt wb_fmt;312 struct fimc_source_info source_config;313 struct list_head pending_buf_q;314 struct list_head active_buf_q;315 struct vb2_queue vbq;316 int active_buf_cnt;317 int buf_index;318 unsigned int frame_count;319 unsigned int reqbufs_count;320 bool streaming;321 u32 input;322 bool user_subdev_api;323};324 325/**326 * struct fimc_pix_limit - image pixel size limits in various IP configurations327 *328 * @scaler_en_w: max input pixel width when the scaler is enabled329 * @scaler_dis_w: max input pixel width when the scaler is disabled330 * @in_rot_en_h: max input width with the input rotator is on331 * @in_rot_dis_w: max input width with the input rotator is off332 * @out_rot_en_w: max output width with the output rotator on333 * @out_rot_dis_w: max output width with the output rotator off334 */335struct fimc_pix_limit {336 u16 scaler_en_w;337 u16 scaler_dis_w;338 u16 in_rot_en_h;339 u16 in_rot_dis_w;340 u16 out_rot_en_w;341 u16 out_rot_dis_w;342};343 344/**345 * struct fimc_variant - FIMC device variant information346 * @has_inp_rot: set if has input rotator347 * @has_out_rot: set if has output rotator348 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register349 * are present in this IP revision350 * @has_cam_if: set if this instance has a camera input interface351 * @has_isp_wb: set if this instance has ISP writeback input352 * @pix_limit: pixel size constraints for the scaler353 * @min_inp_pixsize: minimum input pixel size354 * @min_out_pixsize: minimum output pixel size355 * @hor_offs_align: horizontal pixel offset alignment356 * @min_vsize_align: minimum vertical pixel size alignment357 */358struct fimc_variant {359 unsigned int has_inp_rot:1;360 unsigned int has_out_rot:1;361 unsigned int has_mainscaler_ext:1;362 unsigned int has_cam_if:1;363 unsigned int has_isp_wb:1;364 const struct fimc_pix_limit *pix_limit;365 u16 min_inp_pixsize;366 u16 min_out_pixsize;367 u16 hor_offs_align;368 u16 min_vsize_align;369};370 371/**372 * struct fimc_drvdata - per device type driver data373 * @variant: variant information for this device374 * @num_entities: number of fimc instances available in a SoC375 * @lclk_frequency: local bus clock frequency376 * @cistatus2: 1 if the FIMC IPs have CISTATUS2 register377 * @dma_pix_hoff: the horizontal DMA offset unit: 1 - pixels, 0 - bytes378 * @alpha_color: 1 if alpha color component is supported379 * @out_buf_count: maximum number of output DMA buffers supported380 */381struct fimc_drvdata {382 const struct fimc_variant *variant[FIMC_MAX_DEVS];383 int num_entities;384 unsigned long lclk_frequency;385 /* Fields common to all FIMC IP instances */386 u8 cistatus2;387 u8 dma_pix_hoff;388 u8 alpha_color;389 u8 out_buf_count;390};391 392#define fimc_get_drvdata(_pdev) \393 ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)394 395struct fimc_ctx;396 397/**398 * struct fimc_dev - abstraction for FIMC entity399 * @slock: the spinlock protecting this data structure400 * @lock: the mutex protecting this data structure401 * @pdev: pointer to the FIMC platform device402 * @pdata: pointer to the device platform data403 * @sysreg: pointer to the SYSREG regmap404 * @variant: the IP variant information405 * @drv_data: driver data406 * @id: FIMC device index (0..FIMC_MAX_DEVS)407 * @clock: clocks required for FIMC operation408 * @regs: the mapped hardware registers409 * @irq_queue: interrupt handler waitqueue410 * @v4l2_dev: root v4l2_device411 * @m2m: memory-to-memory V4L2 device information412 * @vid_cap: camera capture device information413 * @state: flags used to synchronize m2m and capture mode operation414 */415struct fimc_dev {416 spinlock_t slock;417 struct mutex lock;418 struct platform_device *pdev;419 struct s5p_platform_fimc *pdata;420 struct regmap *sysreg;421 const struct fimc_variant *variant;422 const struct fimc_drvdata *drv_data;423 int id;424 struct clk *clock[MAX_FIMC_CLOCKS];425 void __iomem *regs;426 wait_queue_head_t irq_queue;427 struct v4l2_device *v4l2_dev;428 struct fimc_m2m_device m2m;429 struct fimc_vid_cap vid_cap;430 unsigned long state;431};432 433/**434 * struct fimc_ctrls - v4l2 controls structure435 * @handler: the control handler436 * @colorfx: image effect control437 * @colorfx_cbcr: Cb/Cr coefficients control438 * @rotate: image rotation control439 * @hflip: horizontal flip control440 * @vflip: vertical flip control441 * @alpha: RGB alpha control442 * @ready: true if @handler is initialized443 */444struct fimc_ctrls {445 struct v4l2_ctrl_handler handler;446 struct {447 struct v4l2_ctrl *colorfx;448 struct v4l2_ctrl *colorfx_cbcr;449 };450 struct v4l2_ctrl *rotate;451 struct v4l2_ctrl *hflip;452 struct v4l2_ctrl *vflip;453 struct v4l2_ctrl *alpha;454 bool ready;455};456 457/**458 * struct fimc_ctx - the device context data459 * @s_frame: source frame properties460 * @d_frame: destination frame properties461 * @out_order_1p: output 1-plane YCBCR order462 * @out_order_2p: output 2-plane YCBCR order463 * @in_order_1p: input 1-plane YCBCR order464 * @in_order_2p: input 2-plane YCBCR order465 * @in_path: input mode (DMA or camera)466 * @out_path: output mode (DMA or FIFO)467 * @scaler: image scaler properties468 * @effect: image effect469 * @rotation: image clockwise rotation in degrees470 * @hflip: indicates image horizontal flip if set471 * @vflip: indicates image vertical flip if set472 * @flags: additional flags for image conversion473 * @state: flags to keep track of user configuration474 * @fimc_dev: the FIMC device this context applies to475 * @fh: v4l2 file handle476 * @ctrls: v4l2 controls structure477 */478struct fimc_ctx {479 struct fimc_frame s_frame;480 struct fimc_frame d_frame;481 u32 out_order_1p;482 u32 out_order_2p;483 u32 in_order_1p;484 u32 in_order_2p;485 enum fimc_datapath in_path;486 enum fimc_datapath out_path;487 struct fimc_scaler scaler;488 struct fimc_effect effect;489 int rotation;490 unsigned int hflip:1;491 unsigned int vflip:1;492 u32 flags;493 u32 state;494 struct fimc_dev *fimc_dev;495 struct v4l2_fh fh;496 struct fimc_ctrls ctrls;497};498 499#define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)500 501static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)502{503 f->o_width = width;504 f->o_height = height;505 f->f_width = width;506 f->f_height = height;507}508 509static inline void set_frame_crop(struct fimc_frame *f,510 u32 left, u32 top, u32 width, u32 height)511{512 f->offs_h = left;513 f->offs_v = top;514 f->width = width;515 f->height = height;516}517 518static inline u32 fimc_get_format_depth(const struct fimc_fmt *ff)519{520 u32 i, depth = 0;521 522 if (ff != NULL)523 for (i = 0; i < ff->colplanes; i++)524 depth += ff->depth[i];525 return depth;526}527 528static inline bool fimc_capture_active(struct fimc_dev *fimc)529{530 unsigned long flags;531 bool ret;532 533 spin_lock_irqsave(&fimc->slock, flags);534 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||535 fimc->state & (1 << ST_CAPT_PEND));536 spin_unlock_irqrestore(&fimc->slock, flags);537 return ret;538}539 540static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)541{542 unsigned long flags;543 544 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);545 ctx->state |= state;546 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);547}548 549static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)550{551 unsigned long flags;552 bool ret;553 554 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);555 ret = (ctx->state & mask) == mask;556 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);557 return ret;558}559 560static inline int tiled_fmt(const struct fimc_fmt *fmt)561{562 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;563}564 565static inline bool fimc_jpeg_fourcc(u32 pixelformat)566{567 return (pixelformat == V4L2_PIX_FMT_JPEG ||568 pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);569}570 571static inline bool fimc_user_defined_mbus_fmt(u32 code)572{573 return (code == MEDIA_BUS_FMT_JPEG_1X8 ||574 code == MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8);575}576 577/* Return the alpha component bit mask */578static inline int fimc_get_alpha_mask(const struct fimc_fmt *fmt)579{580 switch (fmt->color) {581 case FIMC_FMT_RGB444: return 0x0f;582 case FIMC_FMT_RGB555: return 0x01;583 case FIMC_FMT_RGB888: return 0xff;584 default: return 0;585 };586}587 588static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,589 enum v4l2_buf_type type)590{591 struct fimc_frame *frame;592 593 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ||594 type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {595 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))596 frame = &ctx->s_frame;597 else598 return ERR_PTR(-EINVAL);599 } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||600 type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {601 frame = &ctx->d_frame;602 } else {603 v4l2_err(ctx->fimc_dev->v4l2_dev,604 "Wrong buffer/video queue type (%d)\n", type);605 return ERR_PTR(-EINVAL);606 }607 608 return frame;609}610 611/* -----------------------------------------------------*/612/* fimc-core.c */613int fimc_ctrls_create(struct fimc_ctx *ctx);614void fimc_ctrls_delete(struct fimc_ctx *ctx);615void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);616void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);617void __fimc_get_format(const struct fimc_frame *frame, struct v4l2_format *f);618void fimc_adjust_mplane_format(const struct fimc_fmt *fmt, u32 width, u32 height,619 struct v4l2_pix_format_mplane *pix);620const struct fimc_fmt *fimc_find_format(const u32 *pixelformat,621 const u32 *mbus_code,622 unsigned int mask, int index);623const struct fimc_fmt *fimc_get_format(unsigned int index);624 625int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,626 int dw, int dh, int rotation);627int fimc_set_scaler_info(struct fimc_ctx *ctx);628int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);629int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,630 const struct fimc_frame *frame, struct fimc_addr *addr);631void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);632void fimc_set_yuv_order(struct fimc_ctx *ctx);633void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);634 635int fimc_register_m2m_device(struct fimc_dev *fimc,636 struct v4l2_device *v4l2_dev);637void fimc_unregister_m2m_device(struct fimc_dev *fimc);638int fimc_register_driver(void);639void fimc_unregister_driver(void);640 641#ifdef CONFIG_MFD_SYSCON642static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)643{644 return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");645}646#else647#define fimc_get_sysreg_regmap(node) (NULL)648#endif649 650/* -----------------------------------------------------*/651/* fimc-m2m.c */652void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);653 654/* -----------------------------------------------------*/655/* fimc-capture.c */656int fimc_initialize_capture_subdev(struct fimc_dev *fimc);657void fimc_unregister_capture_subdev(struct fimc_dev *fimc);658int fimc_capture_ctrls_create(struct fimc_dev *fimc);659void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,660 void *arg);661int fimc_capture_suspend(struct fimc_dev *fimc);662int fimc_capture_resume(struct fimc_dev *fimc);663 664/*665 * Buffer list manipulation functions. Must be called with fimc.slock held.666 */667 668/**669 * fimc_active_queue_add - add buffer to the capture active buffers queue670 * @vid_cap: camera capture device information671 * @buf: buffer to add to the active buffers list672 */673static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,674 struct fimc_vid_buffer *buf)675{676 list_add_tail(&buf->list, &vid_cap->active_buf_q);677 vid_cap->active_buf_cnt++;678}679 680/**681 * fimc_active_queue_pop - pop buffer from the capture active buffers queue682 * @vid_cap: camera capture device information683 *684 * The caller must assure the active_buf_q list is not empty.685 */686static inline struct fimc_vid_buffer *fimc_active_queue_pop(687 struct fimc_vid_cap *vid_cap)688{689 struct fimc_vid_buffer *buf;690 buf = list_entry(vid_cap->active_buf_q.next,691 struct fimc_vid_buffer, list);692 list_del(&buf->list);693 vid_cap->active_buf_cnt--;694 return buf;695}696 697/**698 * fimc_pending_queue_add - add buffer to the capture pending buffers queue699 * @vid_cap: camera capture device information700 * @buf: buffer to add to the pending buffers list701 */702static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,703 struct fimc_vid_buffer *buf)704{705 list_add_tail(&buf->list, &vid_cap->pending_buf_q);706}707 708/**709 * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue710 * @vid_cap: camera capture device information711 *712 * The caller must assure the pending_buf_q list is not empty.713 */714static inline struct fimc_vid_buffer *fimc_pending_queue_pop(715 struct fimc_vid_cap *vid_cap)716{717 struct fimc_vid_buffer *buf;718 buf = list_entry(vid_cap->pending_buf_q.next,719 struct fimc_vid_buffer, list);720 list_del(&buf->list);721 return buf;722}723 724#endif /* FIMC_CORE_H_ */725