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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Register definition file for Samsung MFC V8.x Interface (FIMV) driver4 *5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.6 * http://www.samsung.com/7 */8 9#ifndef _REGS_MFC_V8_H10#define _REGS_MFC_V8_H11 12#include <linux/sizes.h>13#include "regs-mfc-v7.h"14 15/* Additional registers for v8 */16#define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf10417#define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf10818#define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf14419#define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf14820#define S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8 0xf14C21#define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf15022 23#define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf13824#define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c25#define S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8 0xf14026 27#define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf16028#define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf26029#define S5P_FIMV_D_THIRD_PLANE_DPB_V8 0xf36030#define S5P_FIMV_D_MV_BUFFER_V8 0xf46031 32#define S5P_FIMV_D_NUM_MV_V8 0xf13433#define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 0xf15434 35#define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 0xf56036#define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 0xf56437 38#define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 0xf5b039#define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 0xf5b440#define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 0xf5bc41#define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 0xf5c042#define S5P_FIMV_D_SLICE_IF_ENABLE_V8 0xf5c443#define S5P_FIMV_D_STREAM_DATA_SIZE_V8 0xf5d044 45/* Display information register */46#define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 0xf60047#define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 0xf60448 49/* Display status */50#define S5P_FIMV_D_DISPLAY_STATUS_V8 0xf60851 52#define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 0xf60c53#define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf61054 55#define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 0xf61856#define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 0xf61c57#define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 0xf62058#define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 0xf62459 60/* Decoded picture information register */61#define S5P_FIMV_D_DECODED_STATUS_V8 0xf64462#define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 0xf64863#define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c64#define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 0xf65065#define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 0xf65466#define S5P_FIMV_D_DECODED_NAL_SIZE_V8 0xf66467 68/* Returned value register for specific setting */69#define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 0xf67470#define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 0xf67871#define S5P_FIMV_D_MVC_VIEW_ID_V8 0xf6d872 73/* SEI related information */74#define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 0xf6dc75 76/* Encoder Registers */77#define S5P_FIMV_E_FIXED_PICTURE_QP_V8 0xf79478#define S5P_FIMV_E_RC_CONFIG_V8 0xf79879#define S5P_FIMV_E_RC_QP_BOUND_V8 0xf79c80#define S5P_FIMV_E_RC_RPARAM_V8 0xf7a481#define S5P_FIMV_E_MB_RC_CONFIG_V8 0xf7a882#define S5P_FIMV_E_PADDING_CTRL_V8 0xf7ac83#define S5P_FIMV_E_MV_HOR_RANGE_V8 0xf7b484#define S5P_FIMV_E_MV_VER_RANGE_V8 0xf7b885 86#define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 0xf78c87#define S5P_FIMV_E_VBV_INIT_DELAY_V8 0xf79088#define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8 0xf89489 90#define S5P_FIMV_E_ASPECT_RATIO_V8 0xfb4c91#define S5P_FIMV_E_EXTENDED_SAR_V8 0xfb5092#define S5P_FIMV_E_H264_OPTIONS_V8 0xfb5493 94/* MFCv8 Context buffer sizes */95#define MFC_CTX_BUF_SIZE_V8 (36 * SZ_1K) /* 36KB */96#define MFC_H264_DEC_CTX_BUF_SIZE_V8 (2 * SZ_1M) /* 2MB */97#define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */98#define MFC_H264_ENC_CTX_BUF_SIZE_V8 (100 * SZ_1K) /* 100KB */99#define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 (10 * SZ_1K) /* 10KB */100 101/* Buffer size defines */102#define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) (((w) + 1) * ((h) + 1) * 8)103 104#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176)105#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \106 (((w) * 576 + (h) * 128) + 4128)107 108#define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \109 (((w) * 592) + 2336)110#define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \111 (((w) * 576) + 10512 + \112 ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4))113#define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \114 ((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \115 + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16))116 117/* BUffer alignment defines */118#define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 64119 120/* MFCv8 variant defines */121#define MAX_FW_SIZE_V8 (SZ_512K) /* 512KB */122#define MAX_CPB_SIZE_V8 (3 * SZ_1M) /* 3MB */123#define MFC_VERSION_V8 0x80124#define MFC_NUM_PORTS_V8 1125 126#endif /*_REGS_MFC_V8_H*/127