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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Register definition file for Samsung MFC V5.1 Interface (FIMV) driver4 *5 * Kamil Debski, Copyright (c) 2010 Samsung Electronics6 * http://www.samsung.com/7*/8 9#ifndef _REGS_FIMV_H10#define _REGS_FIMV_H11 12#include <linux/kernel.h>13#include <linux/sizes.h>14 15#define S5P_FIMV_REG_SIZE (S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR)16#define S5P_FIMV_REG_COUNT ((S5P_FIMV_END_ADDR - S5P_FIMV_START_ADDR) / 4)17 18/* Number of bits that the buffer address should be shifted for particular19 * MFC buffers. */20#define S5P_FIMV_START_ADDR 0x000021#define S5P_FIMV_END_ADDR 0xe00822 23#define S5P_FIMV_SW_RESET 0x000024#define S5P_FIMV_RISC_HOST_INT 0x000825 26/* Command from HOST to RISC */27#define S5P_FIMV_HOST2RISC_CMD 0x003028#define S5P_FIMV_HOST2RISC_ARG1 0x003429#define S5P_FIMV_HOST2RISC_ARG2 0x003830#define S5P_FIMV_HOST2RISC_ARG3 0x003c31#define S5P_FIMV_HOST2RISC_ARG4 0x004032 33/* Command from RISC to HOST */34#define S5P_FIMV_RISC2HOST_CMD 0x004435#define S5P_FIMV_RISC2HOST_CMD_MASK 0x1FFFF36#define S5P_FIMV_RISC2HOST_ARG1 0x004837#define S5P_FIMV_RISC2HOST_ARG2 0x004c38#define S5P_FIMV_RISC2HOST_ARG3 0x005039#define S5P_FIMV_RISC2HOST_ARG4 0x005440 41#define S5P_FIMV_FW_VERSION 0x005842#define S5P_FIMV_SYS_MEM_SZ 0x005c43#define S5P_FIMV_FW_STATUS 0x008044 45/* Memory controller register */46#define S5P_FIMV_MC_DRAMBASE_ADR_A 0x050847#define S5P_FIMV_MC_DRAMBASE_ADR_B 0x050c48#define S5P_FIMV_MC_STATUS 0x051049 50/* Common register */51#define S5P_FIMV_COMMON_BASE_A 0x060052#define S5P_FIMV_COMMON_BASE_B 0x070053 54/* Decoder */55#define S5P_FIMV_DEC_CHROMA_ADR (S5P_FIMV_COMMON_BASE_A)56#define S5P_FIMV_DEC_LUMA_ADR (S5P_FIMV_COMMON_BASE_B)57 58/* H.264 decoding */59#define S5P_FIMV_H264_VERT_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)60 /* vertical neighbor motion vector */61#define S5P_FIMV_H264_NB_IP_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)62 /* neighbor pixels for intra pred */63#define S5P_FIMV_H264_MV_ADR (S5P_FIMV_COMMON_BASE_B + 0x80)64 /* H264 motion vector */65 66/* MPEG4 decoding */67#define S5P_FIMV_MPEG4_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)68 /* neighbor AC/DC coeff. */69#define S5P_FIMV_MPEG4_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)70 /* upper neighbor motion vector */71#define S5P_FIMV_MPEG4_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)72 /* subseq. anchor motion vector */73#define S5P_FIMV_MPEG4_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)74 /* overlap transform line */75#define S5P_FIMV_MPEG4_SP_ADR (S5P_FIMV_COMMON_BASE_A + 0xa8)76 /* syntax parser */77 78/* H.263 decoding */79#define S5P_FIMV_H263_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)80#define S5P_FIMV_H263_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)81#define S5P_FIMV_H263_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)82#define S5P_FIMV_H263_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)83 84/* VC-1 decoding */85#define S5P_FIMV_VC1_NB_DCAC_ADR (S5P_FIMV_COMMON_BASE_A + 0x8c)86#define S5P_FIMV_VC1_UP_NB_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x90)87#define S5P_FIMV_VC1_SA_MV_ADR (S5P_FIMV_COMMON_BASE_A + 0x94)88#define S5P_FIMV_VC1_OT_LINE_ADR (S5P_FIMV_COMMON_BASE_A + 0x98)89#define S5P_FIMV_VC1_BITPLANE3_ADR (S5P_FIMV_COMMON_BASE_A + 0x9c)90 /* bitplane3 */91#define S5P_FIMV_VC1_BITPLANE2_ADR (S5P_FIMV_COMMON_BASE_A + 0xa0)92 /* bitplane2 */93#define S5P_FIMV_VC1_BITPLANE1_ADR (S5P_FIMV_COMMON_BASE_A + 0xa4)94 /* bitplane1 */95 96/* Encoder */97#define S5P_FIMV_ENC_REF0_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x1c)98#define S5P_FIMV_ENC_REF1_LUMA_ADR (S5P_FIMV_COMMON_BASE_A + 0x20)99 /* reconstructed luma */100#define S5P_FIMV_ENC_REF0_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B)101#define S5P_FIMV_ENC_REF1_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x04)102 /* reconstructed chroma */103#define S5P_FIMV_ENC_REF2_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x10)104#define S5P_FIMV_ENC_REF2_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x08)105#define S5P_FIMV_ENC_REF3_LUMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x14)106#define S5P_FIMV_ENC_REF3_CHROMA_ADR (S5P_FIMV_COMMON_BASE_B + 0x0c)107 108/* H.264 encoding */109#define S5P_FIMV_H264_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)110 /* upper motion vector */111#define S5P_FIMV_H264_NBOR_INFO_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)112 /* entropy engine's neighbor info. */113#define S5P_FIMV_H264_UP_INTRA_MD_ADR (S5P_FIMV_COMMON_BASE_A + 0x08)114 /* upper intra MD */115#define S5P_FIMV_H264_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)116 /* direct cozero flag */117#define S5P_FIMV_H264_UP_INTRA_PRED_ADR (S5P_FIMV_COMMON_BASE_B + 0x40)118 /* upper intra PRED */119 120/* H.263 encoding */121#define S5P_FIMV_H263_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)122 /* upper motion vector */123#define S5P_FIMV_H263_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)124 /* upper Q coeff. */125 126/* MPEG4 encoding */127#define S5P_FIMV_MPEG4_UP_MV_ADR (S5P_FIMV_COMMON_BASE_A)128 /* upper motion vector */129#define S5P_FIMV_MPEG4_ACDC_COEF_ADR (S5P_FIMV_COMMON_BASE_A + 0x04)130 /* upper Q coeff. */131#define S5P_FIMV_MPEG4_COZERO_FLAG_ADR (S5P_FIMV_COMMON_BASE_A + 0x10)132 /* direct cozero flag */133 134#define S5P_FIMV_ENC_REF_B_LUMA_ADR 0x062c /* ref B Luma addr */135#define S5P_FIMV_ENC_REF_B_CHROMA_ADR 0x0630 /* ref B Chroma addr */136 137#define S5P_FIMV_ENC_CUR_LUMA_ADR 0x0718 /* current Luma addr */138#define S5P_FIMV_ENC_CUR_CHROMA_ADR 0x071C /* current Chroma addr */139 140/* Codec common register */141#define S5P_FIMV_ENC_HSIZE_PX 0x0818 /* frame width at encoder */142#define S5P_FIMV_ENC_VSIZE_PX 0x081c /* frame height at encoder */143#define S5P_FIMV_ENC_PROFILE 0x0830 /* profile register */144#define S5P_FIMV_ENC_PROFILE_H264_MAIN 0145#define S5P_FIMV_ENC_PROFILE_H264_HIGH 1146#define S5P_FIMV_ENC_PROFILE_H264_BASELINE 2147#define S5P_FIMV_ENC_PROFILE_H264_CONSTRAINED_BASELINE 3148#define S5P_FIMV_ENC_PROFILE_MPEG4_SIMPLE 0149#define S5P_FIMV_ENC_PROFILE_MPEG4_ADVANCED_SIMPLE 1150#define S5P_FIMV_ENC_PIC_STRUCT 0x083c /* picture field/frame flag */151#define S5P_FIMV_ENC_LF_CTRL 0x0848 /* loop filter control */152#define S5P_FIMV_ENC_ALPHA_OFF 0x084c /* loop filter alpha offset */153#define S5P_FIMV_ENC_BETA_OFF 0x0850 /* loop filter beta offset */154#define S5P_FIMV_MR_BUSIF_CTRL 0x0854 /* hidden, bus interface ctrl */155#define S5P_FIMV_ENC_PXL_CACHE_CTRL 0x0a00 /* pixel cache control */156 157/* Channel & stream interface register */158#define S5P_FIMV_SI_RTN_CHID 0x2000 /* Return CH inst ID register */159#define S5P_FIMV_SI_CH0_INST_ID 0x2040 /* codec instance ID */160#define S5P_FIMV_SI_CH1_INST_ID 0x2080 /* codec instance ID */161/* Decoder */162#define S5P_FIMV_SI_VRESOL 0x2004 /* vertical res of decoder */163#define S5P_FIMV_SI_HRESOL 0x2008 /* horizontal res of decoder */164#define S5P_FIMV_SI_BUF_NUMBER 0x200c /* number of frames in the165 decoded pic */166#define S5P_FIMV_SI_DISPLAY_Y_ADR 0x2010 /* luma addr of displayed pic */167#define S5P_FIMV_SI_DISPLAY_C_ADR 0x2014 /* chroma addrof displayed pic */168 169#define S5P_FIMV_SI_CONSUMED_BYTES 0x2018 /* Consumed number of bytes to170 decode a frame */171#define S5P_FIMV_SI_DISPLAY_STATUS 0x201c /* status of decoded picture */172 173#define S5P_FIMV_SI_DECODE_Y_ADR 0x2024 /* luma addr of decoded pic */174#define S5P_FIMV_SI_DECODE_C_ADR 0x2028 /* chroma addrof decoded pic */175#define S5P_FIMV_SI_DECODE_STATUS 0x202c /* status of decoded picture */176 177#define S5P_FIMV_SI_CH0_SB_ST_ADR 0x2044 /* start addr of stream buf */178#define S5P_FIMV_SI_CH0_SB_FRM_SIZE 0x2048 /* size of stream buf */179#define S5P_FIMV_SI_CH0_DESC_ADR 0x204c /* addr of descriptor buf */180#define S5P_FIMV_SI_CH0_CPB_SIZE 0x2058 /* max size of coded pic. buf */181#define S5P_FIMV_SI_CH0_DESC_SIZE 0x205c /* max size of descriptor buf */182 183#define S5P_FIMV_SI_CH1_SB_ST_ADR 0x2084 /* start addr of stream buf */184#define S5P_FIMV_SI_CH1_SB_FRM_SIZE 0x2088 /* size of stream buf */185#define S5P_FIMV_SI_CH1_DESC_ADR 0x208c /* addr of descriptor buf */186#define S5P_FIMV_SI_CH1_CPB_SIZE 0x2098 /* max size of coded pic. buf */187#define S5P_FIMV_SI_CH1_DESC_SIZE 0x209c /* max size of descriptor buf */188 189#define S5P_FIMV_CRC_LUMA0 0x2030 /* luma crc data per frame190 (top field) */191#define S5P_FIMV_CRC_CHROMA0 0x2034 /* chroma crc data per frame192 (top field) */193#define S5P_FIMV_CRC_LUMA1 0x2038 /* luma crc data per bottom194 field */195#define S5P_FIMV_CRC_CHROMA1 0x203c /* chroma crc data per bottom196 field */197 198/* Display status */199#define S5P_FIMV_DEC_STATUS_DECODING_ONLY 0200#define S5P_FIMV_DEC_STATUS_DECODING_DISPLAY 1201#define S5P_FIMV_DEC_STATUS_DISPLAY_ONLY 2202#define S5P_FIMV_DEC_STATUS_DECODING_EMPTY 3203#define S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK 7204#define S5P_FIMV_DEC_STATUS_PROGRESSIVE (0<<3)205#define S5P_FIMV_DEC_STATUS_INTERLACE (1<<3)206#define S5P_FIMV_DEC_STATUS_INTERLACE_MASK (1<<3)207#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_TWO (0<<4)208#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_FOUR (1<<4)209#define S5P_FIMV_DEC_STATUS_CRC_NUMBER_MASK (1<<4)210#define S5P_FIMV_DEC_STATUS_CRC_GENERATED (1<<5)211#define S5P_FIMV_DEC_STATUS_CRC_NOT_GENERATED (0<<5)212#define S5P_FIMV_DEC_STATUS_CRC_MASK (1<<5)213 214#define S5P_FIMV_DEC_STATUS_RESOLUTION_MASK (3<<4)215#define S5P_FIMV_DEC_STATUS_RESOLUTION_INC (1<<4)216#define S5P_FIMV_DEC_STATUS_RESOLUTION_DEC (2<<4)217#define S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT 4218 219/* Decode frame address */220#define S5P_FIMV_DECODE_Y_ADR 0x2024221#define S5P_FIMV_DECODE_C_ADR 0x2028222 223/* Decoded frame tpe */224#define S5P_FIMV_DECODE_FRAME_TYPE 0x2020225#define S5P_FIMV_DECODE_FRAME_MASK 7226 227#define S5P_FIMV_DECODE_FRAME_SKIPPED 0228#define S5P_FIMV_DECODE_FRAME_I_FRAME 1229#define S5P_FIMV_DECODE_FRAME_P_FRAME 2230#define S5P_FIMV_DECODE_FRAME_B_FRAME 3231#define S5P_FIMV_DECODE_FRAME_OTHER_FRAME 4232 233/* Sizes of buffers required for decoding */234#define S5P_FIMV_DEC_NB_IP_SIZE (32 * 1024)235#define S5P_FIMV_DEC_VERT_NB_MV_SIZE (16 * 1024)236#define S5P_FIMV_DEC_NB_DCAC_SIZE (16 * 1024)237#define S5P_FIMV_DEC_UPNB_MV_SIZE (68 * 1024)238#define S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE (136 * 1024)239#define S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE (32 * 1024)240#define S5P_FIMV_DEC_VC1_BITPLANE_SIZE (2 * 1024)241#define S5P_FIMV_DEC_STX_PARSER_SIZE (68 * 1024)242 243#define S5P_FIMV_DEC_BUF_ALIGN (8 * 1024)244#define S5P_FIMV_ENC_BUF_ALIGN (8 * 1024)245#define S5P_FIMV_NV12M_HALIGN 16246#define S5P_FIMV_NV12M_LVALIGN 16247#define S5P_FIMV_NV12M_CVALIGN 8248#define S5P_FIMV_NV12MT_HALIGN 128249#define S5P_FIMV_NV12MT_VALIGN 32250#define S5P_FIMV_NV12M_SALIGN 2048251#define S5P_FIMV_NV12MT_SALIGN 8192252 253/* Sizes of buffers required for encoding */254#define S5P_FIMV_ENC_UPMV_SIZE 0x10000255#define S5P_FIMV_ENC_COLFLG_SIZE 0x10000256#define S5P_FIMV_ENC_INTRAMD_SIZE 0x10000257#define S5P_FIMV_ENC_INTRAPRED_SIZE 0x4000258#define S5P_FIMV_ENC_NBORINFO_SIZE 0x10000259#define S5P_FIMV_ENC_ACDCCOEF_SIZE 0x10000260 261/* Encoder */262#define S5P_FIMV_ENC_SI_STRM_SIZE 0x2004 /* stream size */263#define S5P_FIMV_ENC_SI_PIC_CNT 0x2008 /* picture count */264#define S5P_FIMV_ENC_SI_WRITE_PTR 0x200c /* write pointer */265#define S5P_FIMV_ENC_SI_SLICE_TYPE 0x2010 /* slice type(I/P/B/IDR) */266#define S5P_FIMV_ENC_SI_SLICE_TYPE_NON_CODED 0267#define S5P_FIMV_ENC_SI_SLICE_TYPE_I 1268#define S5P_FIMV_ENC_SI_SLICE_TYPE_P 2269#define S5P_FIMV_ENC_SI_SLICE_TYPE_B 3270#define S5P_FIMV_ENC_SI_SLICE_TYPE_SKIPPED 4271#define S5P_FIMV_ENC_SI_SLICE_TYPE_OTHERS 5272#define S5P_FIMV_ENCODED_Y_ADDR 0x2014 /* the addr of the encoded273 luma pic */274#define S5P_FIMV_ENCODED_C_ADDR 0x2018 /* the addr of the encoded275 chroma pic */276 277#define S5P_FIMV_ENC_SI_CH0_SB_ADR 0x2044 /* addr of stream buf */278#define S5P_FIMV_ENC_SI_CH0_SB_SIZE 0x204c /* size of stream buf */279#define S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR 0x2050 /* current Luma addr */280#define S5P_FIMV_ENC_SI_CH0_CUR_C_ADR 0x2054 /* current Chroma addr */281#define S5P_FIMV_ENC_SI_CH0_FRAME_INS 0x2058 /* frame insertion */282 283#define S5P_FIMV_ENC_SI_CH1_SB_ADR 0x2084 /* addr of stream buf */284#define S5P_FIMV_ENC_SI_CH1_SB_SIZE 0x208c /* size of stream buf */285#define S5P_FIMV_ENC_SI_CH1_CUR_Y_ADR 0x2090 /* current Luma addr */286#define S5P_FIMV_ENC_SI_CH1_CUR_C_ADR 0x2094 /* current Chroma addr */287#define S5P_FIMV_ENC_SI_CH1_FRAME_INS 0x2098 /* frame insertion */288 289#define S5P_FIMV_ENC_PIC_TYPE_CTRL 0xc504 /* pic type level control */290#define S5P_FIMV_ENC_B_RECON_WRITE_ON 0xc508 /* B frame recon write ctrl */291#define S5P_FIMV_ENC_MSLICE_CTRL 0xc50c /* multi slice control */292#define S5P_FIMV_ENC_MSLICE_MB 0xc510 /* MB number in the one slice */293#define S5P_FIMV_ENC_MSLICE_BIT 0xc514 /* bit count for one slice */294#define S5P_FIMV_ENC_CIR_CTRL 0xc518 /* number of intra refresh MB */295#define S5P_FIMV_ENC_MAP_FOR_CUR 0xc51c /* linear or tiled mode */296#define S5P_FIMV_ENC_PADDING_CTRL 0xc520 /* padding control */297 298#define S5P_FIMV_ENC_RC_CONFIG 0xc5a0 /* RC config */299#define S5P_FIMV_ENC_RC_BIT_RATE 0xc5a8 /* bit rate */300#define S5P_FIMV_ENC_RC_QBOUND 0xc5ac /* max/min QP */301#define S5P_FIMV_ENC_RC_RPARA 0xc5b0 /* rate control reaction coeff */302#define S5P_FIMV_ENC_RC_MB_CTRL 0xc5b4 /* MB adaptive scaling */303 304/* Encoder for H264 only */305#define S5P_FIMV_ENC_H264_ENTROPY_MODE 0xd004 /* CAVLC or CABAC */306#define S5P_FIMV_ENC_H264_ALPHA_OFF 0xd008 /* loop filter alpha offset */307#define S5P_FIMV_ENC_H264_BETA_OFF 0xd00c /* loop filter beta offset */308#define S5P_FIMV_ENC_H264_NUM_OF_REF 0xd010 /* number of reference for P/B */309#define S5P_FIMV_ENC_H264_TRANS_FLAG 0xd034 /* 8x8 transform flag in PPS &310 high profile */311 312#define S5P_FIMV_ENC_RC_FRAME_RATE 0xd0d0 /* frame rate */313 314/* Encoder for MPEG4 only */315#define S5P_FIMV_ENC_MPEG4_QUART_PXL 0xe008 /* qpel interpolation ctrl */316 317/* Additional */318#define S5P_FIMV_SI_CH0_DPB_CONF_CTRL 0x2068 /* DPB Config Control Register */319#define S5P_FIMV_SLICE_INT_MASK 1320#define S5P_FIMV_SLICE_INT_SHIFT 31321#define S5P_FIMV_DDELAY_ENA_SHIFT 30322#define S5P_FIMV_DDELAY_VAL_MASK 0xff323#define S5P_FIMV_DDELAY_VAL_SHIFT 16324#define S5P_FIMV_DPB_COUNT_MASK 0xffff325#define S5P_FIMV_DPB_FLUSH_MASK 1326#define S5P_FIMV_DPB_FLUSH_SHIFT 14327 328 329#define S5P_FIMV_SI_CH0_RELEASE_BUF 0x2060 /* DPB release buffer register */330#define S5P_FIMV_SI_CH0_HOST_WR_ADR 0x2064 /* address of shared memory */331 332/* Codec numbers */333#define S5P_FIMV_CODEC_NONE -1334 335#define S5P_FIMV_CODEC_H264_DEC 0336#define S5P_FIMV_CODEC_VC1_DEC 1337#define S5P_FIMV_CODEC_MPEG4_DEC 2338#define S5P_FIMV_CODEC_MPEG2_DEC 3339#define S5P_FIMV_CODEC_H263_DEC 4340#define S5P_FIMV_CODEC_VC1RCV_DEC 5341 342#define S5P_FIMV_CODEC_H264_ENC 16343#define S5P_FIMV_CODEC_MPEG4_ENC 17344#define S5P_FIMV_CODEC_H263_ENC 18345 346/* Channel Control Register */347#define S5P_FIMV_CH_SEQ_HEADER 1348#define S5P_FIMV_CH_FRAME_START 2349#define S5P_FIMV_CH_LAST_FRAME 3350#define S5P_FIMV_CH_INIT_BUFS 4351#define S5P_FIMV_CH_FRAME_START_REALLOC 5352#define S5P_FIMV_CH_MASK 7353#define S5P_FIMV_CH_SHIFT 16354 355 356/* Host to RISC command */357#define S5P_FIMV_H2R_CMD_EMPTY 0358#define S5P_FIMV_H2R_CMD_OPEN_INSTANCE 1359#define S5P_FIMV_H2R_CMD_CLOSE_INSTANCE 2360#define S5P_FIMV_H2R_CMD_SYS_INIT 3361#define S5P_FIMV_H2R_CMD_FLUSH 4362#define S5P_FIMV_H2R_CMD_SLEEP 5363#define S5P_FIMV_H2R_CMD_WAKEUP 6364 365#define S5P_FIMV_R2H_CMD_EMPTY 0366#define S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET 1367#define S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET 2368#define S5P_FIMV_R2H_CMD_RSV_RET 3369#define S5P_FIMV_R2H_CMD_SEQ_DONE_RET 4370#define S5P_FIMV_R2H_CMD_FRAME_DONE_RET 5371#define S5P_FIMV_R2H_CMD_SLICE_DONE_RET 6372#define S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET 7373#define S5P_FIMV_R2H_CMD_SYS_INIT_RET 8374#define S5P_FIMV_R2H_CMD_FW_STATUS_RET 9375#define S5P_FIMV_R2H_CMD_SLEEP_RET 10376#define S5P_FIMV_R2H_CMD_WAKEUP_RET 11377#define S5P_FIMV_R2H_CMD_FLUSH_RET 12378#define S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET 15379#define S5P_FIMV_R2H_CMD_EDFU_INIT_RET 16380#define S5P_FIMV_R2H_CMD_ERR_RET 32381 382/* Dummy definition for MFCv6 compatibility */383#define S5P_FIMV_CODEC_H264_MVC_DEC -1384#define S5P_FIMV_R2H_CMD_FIELD_DONE_RET -1385#define S5P_FIMV_MFC_RESET -1386#define S5P_FIMV_RISC_ON -1387#define S5P_FIMV_RISC_BASE_ADDRESS -1388#define S5P_FIMV_CODEC_VP8_DEC -1389#define S5P_FIMV_REG_CLEAR_BEGIN 0390#define S5P_FIMV_REG_CLEAR_COUNT 0391 392/* Error handling defines */393#define S5P_FIMV_ERR_NO_VALID_SEQ_HDR 67394#define S5P_FIMV_ERR_INCOMPLETE_FRAME 124395#define S5P_FIMV_ERR_TIMEOUT 140396#define S5P_FIMV_ERR_WARNINGS_START 145397#define S5P_FIMV_ERR_DEC_MASK 0xFFFF398#define S5P_FIMV_ERR_DEC_SHIFT 0399#define S5P_FIMV_ERR_DSPL_MASK 0xFFFF0000400#define S5P_FIMV_ERR_DSPL_SHIFT 16401 402/* Shared memory registers' offsets */403 404/* An offset of the start position in the stream when405 * the start position is not aligned */406#define S5P_FIMV_SHARED_CROP_INFO_H 0x0020407#define S5P_FIMV_SHARED_CROP_LEFT_MASK 0xFFFF408#define S5P_FIMV_SHARED_CROP_LEFT_SHIFT 0409#define S5P_FIMV_SHARED_CROP_RIGHT_MASK 0xFFFF0000410#define S5P_FIMV_SHARED_CROP_RIGHT_SHIFT 16411#define S5P_FIMV_SHARED_CROP_INFO_V 0x0024412#define S5P_FIMV_SHARED_CROP_TOP_MASK 0xFFFF413#define S5P_FIMV_SHARED_CROP_TOP_SHIFT 0414#define S5P_FIMV_SHARED_CROP_BOTTOM_MASK 0xFFFF0000415#define S5P_FIMV_SHARED_CROP_BOTTOM_SHIFT 16416#define S5P_FIMV_SHARED_SET_FRAME_TAG 0x0004417#define S5P_FIMV_SHARED_GET_FRAME_TAG_TOP 0x0008418#define S5P_FIMV_SHARED_GET_FRAME_TAG_BOT 0x000C419#define S5P_FIMV_SHARED_START_BYTE_NUM 0x0018420#define S5P_FIMV_SHARED_RC_VOP_TIMING 0x0030421#define S5P_FIMV_SHARED_LUMA_DPB_SIZE 0x0064422#define S5P_FIMV_SHARED_CHROMA_DPB_SIZE 0x0068423#define S5P_FIMV_SHARED_MV_SIZE 0x006C424#define S5P_FIMV_SHARED_PIC_TIME_TOP 0x0010425#define S5P_FIMV_SHARED_PIC_TIME_BOTTOM 0x0014426#define S5P_FIMV_SHARED_EXT_ENC_CONTROL 0x0028427#define S5P_FIMV_SHARED_P_B_FRAME_QP 0x0070428#define S5P_FIMV_SHARED_ASPECT_RATIO_IDC 0x0074429#define S5P_FIMV_SHARED_EXTENDED_SAR 0x0078430#define S5P_FIMV_SHARED_H264_I_PERIOD 0x009C431#define S5P_FIMV_SHARED_RC_CONTROL_CONFIG 0x00A0432#define S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT 2433 434/* Offset used by the hardware to store addresses */435#define MFC_OFFSET_SHIFT 11436 437#define FIRMWARE_ALIGN (128 * SZ_1K) /* 128KB */438#define MFC_H264_CTX_BUF_SIZE (600 * SZ_1K) /* 600KB per H264 instance */439#define MFC_CTX_BUF_SIZE (10 * SZ_1K) /* 10KB per instance */440#define DESC_BUF_SIZE (128 * SZ_1K) /* 128KB for DESC buffer */441#define SHARED_BUF_SIZE (8 * SZ_1K) /* 8KB for shared buffer */442 443#define DEF_CPB_SIZE (256 * SZ_1K) /* 256KB */444#define MAX_CPB_SIZE (4 * SZ_1M) /* 4MB */445#define MAX_FW_SIZE (384 * SZ_1K)446 447#define MFC_VERSION 0x51448#define MFC_NUM_PORTS 2449 450#define S5P_FIMV_SHARED_FRAME_PACK_SEI_AVAIL 0x16C451#define S5P_FIMV_SHARED_FRAME_PACK_ARRGMENT_ID 0x170452#define S5P_FIMV_SHARED_FRAME_PACK_SEI_INFO 0x174453#define S5P_FIMV_SHARED_FRAME_PACK_GRID_POS 0x178454 455/* Values for resolution change in display status */456#define S5P_FIMV_RES_INCREASE 1457#define S5P_FIMV_RES_DECREASE 2458 459#endif /* _REGS_FIMV_H */460