brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 * drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c4 *5 * Samsung MFC (Multi Function Codec - FIMV) driver6 * This file contains hw related functions.7 *8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.9 *		http://www.samsung.com/10 */11 12#undef DEBUG13 14#include <linux/delay.h>15#include <linux/mm.h>16#include <linux/io.h>17#include <linux/jiffies.h>18#include <linux/firmware.h>19#include <linux/err.h>20#include <linux/sched.h>21#include <linux/dma-mapping.h>22 23#include <asm/cacheflush.h>24 25#include "s5p_mfc_common.h"26#include "s5p_mfc_cmd.h"27#include "s5p_mfc_intr.h"28#include "s5p_mfc_pm.h"29#include "s5p_mfc_debug.h"30#include "s5p_mfc_opr.h"31#include "s5p_mfc_opr_v6.h"32 33/* #define S5P_MFC_DEBUG_REGWRITE  */34#ifdef S5P_MFC_DEBUG_REGWRITE35#undef writel36#define writel(v, r)							\37	do {								\38		pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v);	\39	__raw_writel(v, r);						\40	} while (0)41#endif /* S5P_MFC_DEBUG_REGWRITE */42 43#define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)44 45/* Allocate temporary buffers for decoding */46static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)47{48	/* NOP */49 50	return 0;51}52 53/* Release temporary buffers for decoding */54static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)55{56	/* NOP */57}58 59/* Allocate codec buffers */60static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)61{62	struct s5p_mfc_dev *dev = ctx->dev;63	unsigned int mb_width, mb_height, width64, height32;64	unsigned int lcu_width = 0, lcu_height = 0;65	int ret;66 67	mb_width = MB_WIDTH(ctx->img_width);68	mb_height = MB_HEIGHT(ctx->img_height);69	width64 = ALIGN(ctx->img_width, 64);70	height32 = ALIGN(ctx->img_height, 32);71 72	if (ctx->type == MFCINST_DECODER) {73		mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",74			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);75		mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);76	} else if (ctx->type == MFCINST_ENCODER) {77		if (IS_MFCV10_PLUS(dev))78			ctx->tmv_buffer_size = 0;79		else if (IS_MFCV8_PLUS(dev))80			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *81			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),82			S5P_FIMV_TMV_BUFFER_ALIGN_V6);83		else84			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *85			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),86			S5P_FIMV_TMV_BUFFER_ALIGN_V6);87		if (IS_MFCV12(dev)) {88			lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);89			lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);90			if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC && ctx->is_10bit) {91				ctx->luma_dpb_size =92					width64 * height32 +93					ALIGN(DIV_ROUND_UP(lcu_width * 32, 4), 16) * height32 + 128;94				if (ctx->is_422)95					ctx->chroma_dpb_size =96						ctx->luma_dpb_size;97				else98					ctx->chroma_dpb_size =99						width64 * height32 / 2 +100						ALIGN(DIV_ROUND_UP(lcu_width *101							32, 4), 16) * height32 / 2 + 128;102			} else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC &&	ctx->is_10bit) {103				ctx->luma_dpb_size =104					ALIGN(ctx->img_width * 2, 128) * height32 + 64;105				ctx->chroma_dpb_size =106					ALIGN(ctx->img_width * 2, 128) * height32 / 2 + 64;107			} else {108				ctx->luma_dpb_size =109					width64 * height32 + 64;110				if (ctx->is_422)111					ctx->chroma_dpb_size =112						ctx->luma_dpb_size;113				else114					ctx->chroma_dpb_size =115						width64 * height32 / 2 + 64;116			}117			ctx->luma_dpb_size = ALIGN(ctx->luma_dpb_size + 256, SZ_2K);118			ctx->chroma_dpb_size = ALIGN(ctx->chroma_dpb_size + 256, SZ_2K);119		} else if (IS_MFCV10_PLUS(dev)) {120			lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);121			lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);122			if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {123				ctx->luma_dpb_size =124					ALIGN((mb_width * 16), 64)125					* ALIGN((mb_height * 16), 32)126						+ 64;127				ctx->chroma_dpb_size =128					ALIGN((mb_width * 16), 64)129							* (mb_height * 8)130							+ 64;131			} else {132				ctx->luma_dpb_size =133					ALIGN((lcu_width * 32), 64)134					* ALIGN((lcu_height * 32), 32)135						+ 64;136				ctx->chroma_dpb_size =137					ALIGN((lcu_width * 32), 64)138							* (lcu_height * 16)139							+ 64;140			}141		} else {142			ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *143					S5P_FIMV_LUMA_MB_TO_PIXEL_V6,144					S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);145			ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *146					S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,147					S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);148		}149		if (IS_MFCV8_PLUS(dev))150			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(151						ctx->img_width, ctx->img_height,152						mb_width, mb_height),153						S5P_FIMV_ME_BUFFER_ALIGN_V6);154		else155			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(156						ctx->img_width, ctx->img_height,157						mb_width, mb_height),158						S5P_FIMV_ME_BUFFER_ALIGN_V6);159 160		mfc_debug(2, "recon luma size: %zu chroma size: %zu\n",161			  ctx->luma_dpb_size, ctx->chroma_dpb_size);162	} else {163		return -EINVAL;164	}165 166	/* Codecs have different memory requirements */167	switch (ctx->codec_mode) {168	case S5P_MFC_CODEC_H264_DEC:169	case S5P_MFC_CODEC_H264_MVC_DEC:170		if (IS_MFCV10_PLUS(dev))171			mfc_debug(2, "Use min scratch buffer size\n");172		else if (IS_MFCV8_PLUS(dev))173			ctx->scratch_buf_size =174				S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(175					mb_width,176					mb_height);177		else178			ctx->scratch_buf_size =179				S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(180					mb_width,181					mb_height);182		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,183				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);184		ctx->bank1.size =185			ctx->scratch_buf_size +186			(ctx->mv_count * ctx->mv_size);187		break;188	case S5P_MFC_CODEC_MPEG4_DEC:189		if (IS_MFCV10_PLUS(dev))190			mfc_debug(2, "Use min scratch buffer size\n");191		else if (IS_MFCV7_PLUS(dev)) {192			ctx->scratch_buf_size =193				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(194						mb_width,195						mb_height);196		} else {197			ctx->scratch_buf_size =198				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(199						mb_width,200						mb_height);201		}202 203		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,204				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);205		ctx->bank1.size = ctx->scratch_buf_size;206		break;207	case S5P_MFC_CODEC_VC1RCV_DEC:208	case S5P_MFC_CODEC_VC1_DEC:209		if (IS_MFCV10_PLUS(dev))210			mfc_debug(2, "Use min scratch buffer size\n");211		else212			ctx->scratch_buf_size =213				S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(214						mb_width,215						mb_height);216 217		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,218				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);219		ctx->bank1.size = ctx->scratch_buf_size;220		break;221	case S5P_MFC_CODEC_MPEG2_DEC:222		ctx->bank1.size = 0;223		ctx->bank2.size = 0;224		break;225	case S5P_MFC_CODEC_H263_DEC:226		if (IS_MFCV10_PLUS(dev))227			mfc_debug(2, "Use min scratch buffer size\n");228		else229			ctx->scratch_buf_size =230				S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(231						mb_width,232						mb_height);233		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,234				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);235		ctx->bank1.size = ctx->scratch_buf_size;236		break;237	case S5P_MFC_CODEC_VP8_DEC:238		if (IS_MFCV10_PLUS(dev))239			mfc_debug(2, "Use min scratch buffer size\n");240		else if (IS_MFCV8_PLUS(dev))241			ctx->scratch_buf_size =242				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(243						mb_width,244						mb_height);245		else246			ctx->scratch_buf_size =247				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(248						mb_width,249						mb_height);250		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,251				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);252		ctx->bank1.size = ctx->scratch_buf_size;253		break;254	case S5P_MFC_CODEC_HEVC_DEC:255		mfc_debug(2, "Use min scratch buffer size\n");256		ctx->bank1.size =257			ctx->scratch_buf_size +258			(ctx->mv_count * ctx->mv_size);259		break;260	case S5P_MFC_CODEC_VP9_DEC:261		mfc_debug(2, "Use min scratch buffer size\n");262		ctx->bank1.size =263			ctx->scratch_buf_size +264			DEC_VP9_STATIC_BUFFER_SIZE;265		break;266	case S5P_MFC_CODEC_H264_ENC:267		if (IS_MFCV12(dev)) {268			mfc_debug(2, "Use min scratch buffer size\n");269			ctx->me_buffer_size =270				ENC_V120_H264_ME_SIZE(mb_width, mb_height);271		} else if (IS_MFCV10_PLUS(dev)) {272			mfc_debug(2, "Use min scratch buffer size\n");273			ctx->me_buffer_size =274			ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);275		} else if (IS_MFCV8_PLUS(dev))276			ctx->scratch_buf_size =277				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(278					mb_width,279					mb_height);280		else281			ctx->scratch_buf_size =282				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(283						mb_width,284						mb_height);285		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,286				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);287		ctx->bank1.size =288			ctx->scratch_buf_size + ctx->tmv_buffer_size +289			(ctx->pb_count * (ctx->luma_dpb_size +290			ctx->chroma_dpb_size + ctx->me_buffer_size));291		ctx->bank2.size = 0;292		break;293	case S5P_MFC_CODEC_MPEG4_ENC:294	case S5P_MFC_CODEC_H263_ENC:295		if (IS_MFCV12(dev)) {296			mfc_debug(2, "Use min scratch buffer size\n");297			ctx->me_buffer_size =298				ENC_V120_MPEG4_ME_SIZE(mb_width, mb_height);299		} else if (IS_MFCV10_PLUS(dev)) {300			mfc_debug(2, "Use min scratch buffer size\n");301			ctx->me_buffer_size =302				ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,303							mb_height), 16);304		} else305			ctx->scratch_buf_size =306				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(307						mb_width,308						mb_height);309		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,310					S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);311		ctx->bank1.size =312			ctx->scratch_buf_size + ctx->tmv_buffer_size +313			(ctx->pb_count * (ctx->luma_dpb_size +314			ctx->chroma_dpb_size + ctx->me_buffer_size));315		ctx->bank2.size = 0;316		break;317	case S5P_MFC_CODEC_VP8_ENC:318		if (IS_MFCV12(dev)) {319			mfc_debug(2, "Use min scratch buffer size\n");320			ctx->me_buffer_size =321				ENC_V120_VP8_ME_SIZE(mb_width, mb_height);322		} else if (IS_MFCV10_PLUS(dev)) {323			mfc_debug(2, "Use min scratch buffer size\n");324			ctx->me_buffer_size =325				ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),326						16);327		} else if (IS_MFCV8_PLUS(dev))328			ctx->scratch_buf_size =329				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(330					mb_width,331					mb_height);332		else333			ctx->scratch_buf_size =334				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(335						mb_width,336						mb_height);337		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,338				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);339		ctx->bank1.size =340			ctx->scratch_buf_size + ctx->tmv_buffer_size +341			(ctx->pb_count * (ctx->luma_dpb_size +342			ctx->chroma_dpb_size + ctx->me_buffer_size));343		ctx->bank2.size = 0;344		break;345	case S5P_MFC_CODEC_HEVC_ENC:346		if (IS_MFCV12(dev))347			ctx->me_buffer_size =348				ENC_V120_HEVC_ME_SIZE(lcu_width, lcu_height);349		else350			ctx->me_buffer_size =351				ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);352		mfc_debug(2, "Use min scratch buffer size\n");353		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);354		ctx->bank1.size =355			ctx->scratch_buf_size + ctx->tmv_buffer_size +356			(ctx->pb_count * (ctx->luma_dpb_size +357			ctx->chroma_dpb_size + ctx->me_buffer_size));358		ctx->bank2.size = 0;359		break;360	default:361		break;362	}363 364	/* Allocate only if memory from bank 1 is necessary */365	if (ctx->bank1.size > 0) {366		ret = s5p_mfc_alloc_generic_buf(dev, BANK_L_CTX, &ctx->bank1);367		if (ret) {368			mfc_err("Failed to allocate Bank1 memory\n");369			return ret;370		}371		BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));372	}373	return 0;374}375 376/* Release buffers allocated for codec */377static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)378{379	s5p_mfc_release_generic_buf(ctx->dev, &ctx->bank1);380}381 382/* Allocate memory for instance data buffer */383static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)384{385	struct s5p_mfc_dev *dev = ctx->dev;386	const struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;387	int ret;388 389	mfc_debug_enter();390 391	switch (ctx->codec_mode) {392	case S5P_MFC_CODEC_H264_DEC:393	case S5P_MFC_CODEC_H264_MVC_DEC:394	case S5P_MFC_CODEC_HEVC_DEC:395		ctx->ctx.size = buf_size->h264_dec_ctx;396		break;397	case S5P_MFC_CODEC_MPEG4_DEC:398	case S5P_MFC_CODEC_H263_DEC:399	case S5P_MFC_CODEC_VC1RCV_DEC:400	case S5P_MFC_CODEC_VC1_DEC:401	case S5P_MFC_CODEC_MPEG2_DEC:402	case S5P_MFC_CODEC_VP8_DEC:403	case S5P_MFC_CODEC_VP9_DEC:404		ctx->ctx.size = buf_size->other_dec_ctx;405		break;406	case S5P_MFC_CODEC_H264_ENC:407		ctx->ctx.size = buf_size->h264_enc_ctx;408		break;409	case S5P_MFC_CODEC_HEVC_ENC:410		ctx->ctx.size = buf_size->hevc_enc_ctx;411		break;412	case S5P_MFC_CODEC_MPEG4_ENC:413	case S5P_MFC_CODEC_H263_ENC:414	case S5P_MFC_CODEC_VP8_ENC:415		ctx->ctx.size = buf_size->other_enc_ctx;416		break;417	default:418		ctx->ctx.size = 0;419		mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);420		break;421	}422 423	ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->ctx);424	if (ret) {425		mfc_err("Failed to allocate instance buffer\n");426		return ret;427	}428 429	memset(ctx->ctx.virt, 0, ctx->ctx.size);430	wmb();431 432	mfc_debug_leave();433 434	return 0;435}436 437/* Release instance buffer */438static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)439{440	s5p_mfc_release_priv_buf(ctx->dev, &ctx->ctx);441}442 443/* Allocate context buffers for SYS_INIT */444static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)445{446	const struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;447	int ret;448 449	mfc_debug_enter();450 451	dev->ctx_buf.size = buf_size->dev_ctx;452	ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->ctx_buf);453	if (ret) {454		mfc_err("Failed to allocate device context buffer\n");455		return ret;456	}457 458	memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);459	wmb();460 461	mfc_debug_leave();462 463	return 0;464}465 466/* Release context buffers for SYS_INIT */467static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)468{469	s5p_mfc_release_priv_buf(dev, &dev->ctx_buf);470}471 472static int calc_plane(int width, int height)473{474	int mbX, mbY;475 476	mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);477	mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);478 479	if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)480		mbY = (mbY + 1) / 2 * 2;481 482	return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *483		(mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);484}485 486static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)487{488	struct s5p_mfc_dev *dev = ctx->dev;489	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);490	ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);491	ctx->chroma_size_1 = 0;492	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"493			"buffer dimensions: %dx%d\n", ctx->img_width,494			ctx->img_height, ctx->buf_width, ctx->buf_height);495 496	switch (ctx->dst_fmt->fourcc) {497	case V4L2_PIX_FMT_NV12M:498	case V4L2_PIX_FMT_NV21M:499		ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);500		ctx->stride[1] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);501		ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);502		ctx->chroma_size = calc_plane(ctx->stride[1], (ctx->img_height / 2));503		break;504	case V4L2_PIX_FMT_YUV420M:505	case V4L2_PIX_FMT_YVU420M:506		ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);507		ctx->stride[1] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);508		ctx->stride[2] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);509		ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);510		ctx->chroma_size = calc_plane(ctx->stride[1], (ctx->img_height / 2));511		ctx->chroma_size_1 = calc_plane(ctx->stride[2], (ctx->img_height / 2));512		break;513	}514 515	if (IS_MFCV8_PLUS(ctx->dev)) {516		/* MFCv8 needs additional 64 bytes for luma,chroma dpb*/517		ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;518		ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;519		ctx->chroma_size_1 += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;520	}521 522	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||523			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {524		if (IS_MFCV12(dev))525			ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 1024);526		else if (IS_MFCV10_PLUS(dev))527			ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 512);528		else529			ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 128);530 531	} else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {532		ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width, ctx->img_height);533		ctx->mv_size = ALIGN(ctx->mv_size, 32);534	} else {535		ctx->mv_size = 0;536	}537}538 539static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)540{541	unsigned int mb_width, mb_height;542 543	mb_width = MB_WIDTH(ctx->img_width);544	mb_height = MB_HEIGHT(ctx->img_height);545 546	if (IS_MFCV12(ctx->dev)) {547		switch (ctx->src_fmt->fourcc) {548		case V4L2_PIX_FMT_NV12M:549		case V4L2_PIX_FMT_NV21M:550			ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);551			ctx->stride[1] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);552			ctx->luma_size = ctx->stride[0] * ALIGN(ctx->img_height, 16);553			ctx->chroma_size =  ctx->stride[0] * ALIGN(ctx->img_height / 2, 16);554			break;555		case V4L2_PIX_FMT_YUV420M:556		case V4L2_PIX_FMT_YVU420M:557			ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);558			ctx->stride[1] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);559			ctx->stride[2] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);560			ctx->luma_size = ctx->stride[0] * ALIGN(ctx->img_height, 16);561			ctx->chroma_size =  ctx->stride[1] * ALIGN(ctx->img_height / 2, 16);562			ctx->chroma_size_1 =  ctx->stride[2] * ALIGN(ctx->img_height / 2, 16);563			break;564		}565		ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;566		ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V12;567		ctx->chroma_size_1 += MFC_CHROMA_PAD_BYTES_V12;568	} else {569		ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);570		ctx->stride[0] = ctx->buf_width;571		ctx->stride[1] = ctx->buf_width;572		ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);573		ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);574		ctx->chroma_size_1 = 0;575		/* MFCv7 needs pad bytes for Luma and Chroma */576		if (IS_MFCV7_PLUS(ctx->dev)) {577			ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;578			ctx->chroma_size += MFC_LUMA_PAD_BYTES_V7;579		}580	}581}582 583/* Set registers for decoding stream buffer */584static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,585			int buf_addr, unsigned int start_num_byte,586			unsigned int strm_size)587{588	struct s5p_mfc_dev *dev = ctx->dev;589	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;590	const struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;591 592	mfc_debug_enter();593	mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"594		"buf_size: 0x%08x (%d)\n",595		ctx->inst_no, buf_addr, strm_size, strm_size);596	writel(strm_size, mfc_regs->d_stream_data_size);597	writel(buf_addr, mfc_regs->d_cpb_buffer_addr);598	writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size);599	writel(start_num_byte, mfc_regs->d_cpb_buffer_offset);600 601	mfc_debug_leave();602	return 0;603}604 605/* Set decoding frame buffer */606static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)607{608	unsigned int frame_size, i;609	unsigned int frame_size_ch, frame_size_mv;610	struct s5p_mfc_dev *dev = ctx->dev;611	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;612	size_t buf_addr1;613	int buf_size1;614	int align_gap;615 616	buf_addr1 = ctx->bank1.dma;617	buf_size1 = ctx->bank1.size;618 619	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);620	mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);621	mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);622 623	writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);624	writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);625	writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);626	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==627			V4L2_PIX_FMT_YVU420M)628		writel(ctx->chroma_size_1, mfc_regs->d_third_plane_dpb_size);629	writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);630	writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);631 632	if (IS_MFCV8_PLUS(dev)) {633		writel(ctx->stride[0], mfc_regs->d_first_plane_dpb_stride_size);634		writel(ctx->stride[1], mfc_regs->d_second_plane_dpb_stride_size);635		if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==636				V4L2_PIX_FMT_YVU420M)637			writel(ctx->stride[2], mfc_regs->d_third_plane_dpb_stride_size);638	}639 640	buf_addr1 += ctx->scratch_buf_size;641	buf_size1 -= ctx->scratch_buf_size;642 643	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||644			ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC ||645			ctx->codec_mode == S5P_FIMV_CODEC_HEVC_DEC) {646		writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);647		writel(ctx->mv_count, mfc_regs->d_num_mv);648	}649 650	frame_size = ctx->luma_size;651	frame_size_ch = ctx->chroma_size;652	frame_size_mv = ctx->mv_size;653	mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",654			frame_size, frame_size_ch, frame_size_mv);655 656	for (i = 0; i < ctx->total_dpb_count; i++) {657		/* Bank2 */658		mfc_debug(2, "Luma %d: %zx\n", i,659					ctx->dst_bufs[i].cookie.raw.luma);660		writel(ctx->dst_bufs[i].cookie.raw.luma,661				mfc_regs->d_first_plane_dpb + i * 4);662		mfc_debug(2, "\tChroma %d: %zx\n", i,663					ctx->dst_bufs[i].cookie.raw.chroma);664		writel(ctx->dst_bufs[i].cookie.raw.chroma,665				mfc_regs->d_second_plane_dpb + i * 4);666		if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==667				V4L2_PIX_FMT_YVU420M) {668			mfc_debug(2, "\tChroma_1 %d: %zx\n", i, ctx669					->dst_bufs[i].cookie.raw.chroma_1);670			writel(ctx->dst_bufs[i].cookie.raw.chroma_1, mfc_regs->d_third_plane_dpb +671					i * 4);672		}673	}674	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||675			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||676			ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {677		for (i = 0; i < ctx->mv_count; i++) {678			/* To test alignment */679			align_gap = buf_addr1;680			buf_addr1 = ALIGN(buf_addr1, 16);681			align_gap = buf_addr1 - align_gap;682			buf_size1 -= align_gap;683 684			mfc_debug(2, "\tBuf1: %zx, size: %d\n",685					buf_addr1, buf_size1);686			writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4);687			buf_addr1 += frame_size_mv;688			buf_size1 -= frame_size_mv;689		}690	}691	if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_DEC) {692		writel(buf_addr1, mfc_regs->d_static_buffer_addr);693		writel(DEC_VP9_STATIC_BUFFER_SIZE,694				mfc_regs->d_static_buffer_size);695		buf_addr1 += DEC_VP9_STATIC_BUFFER_SIZE;696		buf_size1 -= DEC_VP9_STATIC_BUFFER_SIZE;697	}698 699	mfc_debug(2, "Buf1: %zx, buf_size1: %d (frames %d)\n",700			buf_addr1, buf_size1, ctx->total_dpb_count);701	if (buf_size1 < 0) {702		mfc_debug(2, "Not enough memory has been allocated.\n");703		return -ENOMEM;704	}705 706	writel(ctx->inst_no, mfc_regs->instance_id);707	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,708			S5P_FIMV_CH_INIT_BUFS_V6, NULL);709 710	mfc_debug(2, "After setting buffers.\n");711	return 0;712}713 714/* Set registers for encoding stream buffer */715static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,716		unsigned long addr, unsigned int size)717{718	struct s5p_mfc_dev *dev = ctx->dev;719	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;720 721	writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */722	writel(size, mfc_regs->e_stream_buffer_size);723 724	mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%x\n",725		  addr, size);726 727	return 0;728}729 730static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,731		unsigned long y_addr, unsigned long c_addr,732		unsigned long c_1_addr)733{734	struct s5p_mfc_dev *dev = ctx->dev;735	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;736 737	writel(y_addr, mfc_regs->e_source_first_plane_addr);738	writel(c_addr, mfc_regs->e_source_second_plane_addr);739	writel(c_1_addr, mfc_regs->e_source_third_plane_addr);740 741	mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);742	mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);743	mfc_debug(2, "enc src cr buf addr: 0x%08lx\n", c_1_addr);744}745 746static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,747		unsigned long *y_addr, unsigned long *c_addr,748		unsigned long *c_1_addr)749{750	struct s5p_mfc_dev *dev = ctx->dev;751	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;752	unsigned long enc_recon_y_addr, enc_recon_c_addr;753 754	*y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr);755	*c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr);756	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==757			V4L2_PIX_FMT_YVU420M)758		*c_1_addr = readl(mfc_regs->e_encoded_source_third_plane_addr);759	else760		*c_1_addr = 0;761 762	enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr);763	enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr);764 765	mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr);766	mfc_debug(2, "recon c addr: 0x%08lx c_addr: 0x%08lx\n", enc_recon_c_addr, *c_addr);767}768 769/* Set encoding ref & codec buffer */770static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)771{772	struct s5p_mfc_dev *dev = ctx->dev;773	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;774	size_t buf_addr1;775	int i, buf_size1;776 777	mfc_debug_enter();778 779	buf_addr1 = ctx->bank1.dma;780	buf_size1 = ctx->bank1.size;781 782	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);783 784	if (IS_MFCV10_PLUS(dev)) {785		/* start address of per buffer is aligned */786		for (i = 0; i < ctx->pb_count; i++) {787			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));788			buf_addr1 += ctx->luma_dpb_size;789			buf_size1 -= ctx->luma_dpb_size;790		}791		for (i = 0; i < ctx->pb_count; i++) {792			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));793			buf_addr1 += ctx->chroma_dpb_size;794			buf_size1 -= ctx->chroma_dpb_size;795		}796		for (i = 0; i < ctx->pb_count; i++) {797			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));798			buf_addr1 += ctx->me_buffer_size;799			buf_size1 -= ctx->me_buffer_size;800		}801	} else {802		for (i = 0; i < ctx->pb_count; i++) {803			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));804			buf_addr1 += ctx->luma_dpb_size;805			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));806			buf_addr1 += ctx->chroma_dpb_size;807			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));808			buf_addr1 += ctx->me_buffer_size;809			buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size810					+ ctx->me_buffer_size);811		}812	}813 814	writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);815	writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);816	buf_addr1 += ctx->scratch_buf_size;817	buf_size1 -= ctx->scratch_buf_size;818 819	writel(buf_addr1, mfc_regs->e_tmv_buffer0);820	buf_addr1 += ctx->tmv_buffer_size >> 1;821	writel(buf_addr1, mfc_regs->e_tmv_buffer1);822	buf_addr1 += ctx->tmv_buffer_size >> 1;823	buf_size1 -= ctx->tmv_buffer_size;824 825	mfc_debug(2, "Buf1: %zu, buf_size1: %d (ref frames %d)\n",826			buf_addr1, buf_size1, ctx->pb_count);827	if (buf_size1 < 0) {828		mfc_debug(2, "Not enough memory has been allocated.\n");829		return -ENOMEM;830	}831 832	writel(ctx->inst_no, mfc_regs->instance_id);833	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,834			S5P_FIMV_CH_INIT_BUFS_V6, NULL);835 836	mfc_debug_leave();837 838	return 0;839}840 841static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)842{843	struct s5p_mfc_dev *dev = ctx->dev;844	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;845 846	/* multi-slice control */847	/* multi-slice MB number or bit size */848	writel(ctx->slice_mode, mfc_regs->e_mslice_mode);849	if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {850		writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);851	} else if (ctx->slice_mode ==852			V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {853		writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);854	} else {855		writel(0x0, mfc_regs->e_mslice_size_mb);856		writel(0x0, mfc_regs->e_mslice_size_bits);857	}858 859	return 0;860}861 862static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)863{864	struct s5p_mfc_dev *dev = ctx->dev;865	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;866	const struct s5p_mfc_enc_params *p = &ctx->enc_params;867	unsigned int reg = 0;868 869	mfc_debug_enter();870 871	/* width */872	writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */873	/* height */874	writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */875 876	/* cropped width */877	writel(ctx->img_width, mfc_regs->e_cropped_frame_width);878	/* cropped height */879	writel(ctx->img_height, mfc_regs->e_cropped_frame_height);880	/* cropped offset */881	writel(0x0, mfc_regs->e_frame_crop_offset);882 883	/* pictype : IDR period */884	reg = 0;885	reg |= p->gop_size & 0xFFFF;886	writel(reg, mfc_regs->e_gop_config);887 888	/* multi-slice control */889	/* multi-slice MB number or bit size */890	ctx->slice_mode = p->slice_mode;891	reg = 0;892	if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {893		reg |= (0x1 << 3);894		writel(reg, mfc_regs->e_enc_options);895		ctx->slice_size.mb = p->slice_mb;896	} else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES) {897		reg |= (0x1 << 3);898		writel(reg, mfc_regs->e_enc_options);899		ctx->slice_size.bits = p->slice_bit;900	} else {901		reg &= ~(0x1 << 3);902		writel(reg, mfc_regs->e_enc_options);903	}904 905	s5p_mfc_set_slice_mode(ctx);906 907	/* cyclic intra refresh */908	writel(p->intra_refresh_mb, mfc_regs->e_ir_size);909	reg = readl(mfc_regs->e_enc_options);910	if (p->intra_refresh_mb == 0)911		reg &= ~(0x1 << 4);912	else913		reg |= (0x1 << 4);914	writel(reg, mfc_regs->e_enc_options);915 916	/* 'NON_REFERENCE_STORE_ENABLE' for debugging */917	reg = readl(mfc_regs->e_enc_options);918	reg &= ~(0x1 << 9);919	writel(reg, mfc_regs->e_enc_options);920 921	/* memory structure cur. frame */922	if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {923		/* 0: Linear, 1: 2D tiled*/924		reg = readl(mfc_regs->e_enc_options);925		reg &= ~(0x1 << 7);926		writel(reg, mfc_regs->e_enc_options);927		/* 0: NV12(CbCr), 1: NV21(CrCb) */928		writel(0x0, mfc_regs->pixel_format);929	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {930		/* 0: Linear, 1: 2D tiled*/931		reg = readl(mfc_regs->e_enc_options);932		reg &= ~(0x1 << 7);933		writel(reg, mfc_regs->e_enc_options);934		/* 0: NV12(CbCr), 1: NV21(CrCb) */935		writel(0x1, mfc_regs->pixel_format);936	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {937		/* 0: Linear, 1: 2D tiled*/938		reg = readl(mfc_regs->e_enc_options);939		reg |= (0x1 << 7);940		writel(reg, mfc_regs->e_enc_options);941		/* 0: NV12(CbCr), 1: NV21(CrCb) */942		writel(0x0, mfc_regs->pixel_format);943	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {944		/* 0: Linear, 1: 2D tiled*/945		reg = readl(mfc_regs->e_enc_options);946		reg &= ~(0x1 << 7);947		writel(reg, mfc_regs->e_enc_options);948		/* 2: YV12(CrCb), 3: I420(CrCb) */949		writel(0x2, mfc_regs->pixel_format);950	} else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M) {951		/* 0: Linear, 1: 2D tiled*/952		reg = readl(mfc_regs->e_enc_options);953		reg &= ~(0x1 << 7);954		writel(reg, mfc_regs->e_enc_options);955		/* 2: YV12(CrCb), 3: I420(CrCb) */956		writel(0x3, mfc_regs->pixel_format);957	}958 959	/* memory structure recon. frame */960	/* 0: Linear, 1: 2D tiled */961	reg = readl(mfc_regs->e_enc_options);962	reg |= (0x1 << 8);963	writel(reg, mfc_regs->e_enc_options);964 965	/* padding control & value */966	writel(0x0, mfc_regs->e_padding_ctrl);967	if (p->pad) {968		reg = 0;969		/** enable */970		reg |= (1UL << 31);971		/** cr value */972		reg |= ((p->pad_cr & 0xFF) << 16);973		/** cb value */974		reg |= ((p->pad_cb & 0xFF) << 8);975		/** y value */976		reg |= p->pad_luma & 0xFF;977		writel(reg, mfc_regs->e_padding_ctrl);978	}979 980	/* rate control config. */981	reg = 0;982	/* frame-level rate control */983	reg |= ((p->rc_frame & 0x1) << 9);984	writel(reg, mfc_regs->e_rc_config);985 986	/* bit rate */987	if (p->rc_frame)988		writel(p->rc_bitrate,989			mfc_regs->e_rc_bit_rate);990	else991		writel(1, mfc_regs->e_rc_bit_rate);992 993	/* reaction coefficient */994	if (p->rc_frame) {995		if (IS_MFCV12(dev)) {996			/* loose CBR */997			if (p->rc_reaction_coeff < LOOSE_CBR_MAX)998				writel(1, mfc_regs->e_rc_mode);999			/* tight CBR */1000			else if (p->rc_reaction_coeff < TIGHT_CBR_MAX)1001				writel(0, mfc_regs->e_rc_mode);1002			/* VBR */1003			else1004				writel(2, mfc_regs->e_rc_mode);1005		} else {1006			/* tight CBR */1007			if (p->rc_reaction_coeff < TIGHT_CBR_MAX)1008				writel(1, mfc_regs->e_rc_mode);1009			/* loose CBR */1010			else1011				writel(2, mfc_regs->e_rc_mode);1012		}1013	}1014 1015	/* seq header ctrl */1016	reg = readl(mfc_regs->e_enc_options);1017	reg &= ~(0x1 << 2);1018	reg |= ((p->seq_hdr_mode & 0x1) << 2);1019 1020	/* frame skip mode */1021	reg &= ~(0x3);1022	reg |= (p->frame_skip_mode & 0x3);1023	writel(reg, mfc_regs->e_enc_options);1024 1025	/* 'DROP_CONTROL_ENABLE', disable */1026	reg = readl(mfc_regs->e_rc_config);1027	reg &= ~(0x1 << 10);1028	writel(reg, mfc_regs->e_rc_config);1029 1030	/* setting for MV range [16, 256] */1031	reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);1032	writel(reg, mfc_regs->e_mv_hor_range);1033 1034	reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);1035	writel(reg, mfc_regs->e_mv_ver_range);1036 1037	writel(0x0, mfc_regs->e_frame_insertion);1038	writel(0x0, mfc_regs->e_roi_buffer_addr);1039	writel(0x0, mfc_regs->e_param_change);1040	writel(0x0, mfc_regs->e_rc_roi_ctrl);1041	writel(0x0, mfc_regs->e_picture_tag);1042 1043	writel(0x0, mfc_regs->e_bit_count_enable);1044	writel(0x0, mfc_regs->e_max_bit_count);1045	writel(0x0, mfc_regs->e_min_bit_count);1046 1047	writel(0x0, mfc_regs->e_metadata_buffer_addr);1048	writel(0x0, mfc_regs->e_metadata_buffer_size);1049 1050	mfc_debug_leave();1051 1052	return 0;1053}1054 1055static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)1056{1057	struct s5p_mfc_dev *dev = ctx->dev;1058	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1059	struct s5p_mfc_enc_params *p = &ctx->enc_params;1060	struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;1061	unsigned int reg = 0;1062	int i;1063 1064	mfc_debug_enter();1065 1066	s5p_mfc_set_enc_params(ctx);1067 1068	/* pictype : number of B */1069	reg = readl(mfc_regs->e_gop_config);1070	reg &= ~(0x3 << 16);1071	reg |= ((p->num_b_frame & 0x3) << 16);1072	writel(reg, mfc_regs->e_gop_config);1073 1074	/* UHD encoding case */1075	if (ctx->img_width == 3840 && ctx->img_height == 2160) {1076		if (p_h264->level < 51) {1077			mfc_debug(2, "Set Level 5.1 for UHD\n");1078			p_h264->level = 51;1079		}1080		if (p_h264->profile != 0x2) {1081			mfc_debug(2, "Set High profile for UHD\n");1082			p_h264->profile = 0x2;1083		}1084	}1085 1086	/* profile & level */1087	reg = 0;1088	/** level */1089	reg |= ((p_h264->level & 0xFF) << 8);1090	/** profile - 0 ~ 3 */1091	reg |= p_h264->profile & 0x3F;1092	writel(reg, mfc_regs->e_picture_profile);1093 1094	/* rate control config. */1095	reg = readl(mfc_regs->e_rc_config);1096	/** macroblock level rate control */1097	reg &= ~(0x1 << 8);1098	reg |= ((p->rc_mb & 0x1) << 8);1099	writel(reg, mfc_regs->e_rc_config);1100 1101	/** frame QP */1102	reg &= ~(0x3F);1103	reg |= p_h264->rc_frame_qp & 0x3F;1104	writel(reg, mfc_regs->e_rc_config);1105 1106	/* max & min value of QP */1107	reg = 0;1108	/** max QP */1109	reg |= ((p_h264->rc_max_qp & 0x3F) << 8);1110	/** min QP */1111	reg |= p_h264->rc_min_qp & 0x3F;1112	writel(reg, mfc_regs->e_rc_qp_bound);1113 1114	/* other QPs */1115	writel(0x0, mfc_regs->e_fixed_picture_qp);1116	if (!p->rc_frame && !p->rc_mb) {1117		reg = 0;1118		reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);1119		reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);1120		reg |= p_h264->rc_frame_qp & 0x3F;1121		writel(reg, mfc_regs->e_fixed_picture_qp);1122	}1123 1124	/* frame rate */1125	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {1126		reg = 0;1127		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);1128		reg |= p->rc_framerate_denom & 0xFFFF;1129		writel(reg, mfc_regs->e_rc_frame_rate);1130	}1131 1132	/* vbv buffer size */1133	if (p->frame_skip_mode ==1134			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {1135		writel(p_h264->cpb_size & 0xFFFF,1136				mfc_regs->e_vbv_buffer_size);1137 1138		if (p->rc_frame)1139			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);1140	}1141 1142	/* interlace */1143	reg = 0;1144	reg |= ((p_h264->interlace & 0x1) << 3);1145	writel(reg, mfc_regs->e_h264_options);1146 1147	/* height */1148	if (p_h264->interlace) {1149		writel(ctx->img_height >> 1,1150				mfc_regs->e_frame_height); /* 32 align */1151		/* cropped height */1152		writel(ctx->img_height >> 1,1153				mfc_regs->e_cropped_frame_height);1154	}1155 1156	/* loop filter ctrl */1157	reg = readl(mfc_regs->e_h264_options);1158	reg &= ~(0x3 << 1);1159	reg |= ((p_h264->loop_filter_mode & 0x3) << 1);1160	writel(reg, mfc_regs->e_h264_options);1161 1162	/* loopfilter alpha offset */1163	if (p_h264->loop_filter_alpha < 0) {1164		reg = 0x10;1165		reg |= (0xFF - p_h264->loop_filter_alpha) + 1;1166	} else {1167		reg = 0x00;1168		reg |= (p_h264->loop_filter_alpha & 0xF);1169	}1170	writel(reg, mfc_regs->e_h264_lf_alpha_offset);1171 1172	/* loopfilter beta offset */1173	if (p_h264->loop_filter_beta < 0) {1174		reg = 0x10;1175		reg |= (0xFF - p_h264->loop_filter_beta) + 1;1176	} else {1177		reg = 0x00;1178		reg |= (p_h264->loop_filter_beta & 0xF);1179	}1180	writel(reg, mfc_regs->e_h264_lf_beta_offset);1181 1182	/* entropy coding mode */1183	reg = readl(mfc_regs->e_h264_options);1184	reg &= ~(0x1);1185	reg |= p_h264->entropy_mode & 0x1;1186	writel(reg, mfc_regs->e_h264_options);1187 1188	/* number of ref. picture */1189	reg = readl(mfc_regs->e_h264_options);1190	reg &= ~(0x1 << 7);1191	reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);1192	writel(reg, mfc_regs->e_h264_options);1193 1194	/* 8x8 transform enable */1195	reg = readl(mfc_regs->e_h264_options);1196	reg &= ~(0x3 << 12);1197	reg |= ((p_h264->_8x8_transform & 0x3) << 12);1198	writel(reg, mfc_regs->e_h264_options);1199 1200	/* macroblock adaptive scaling features */1201	writel(0x0, mfc_regs->e_mb_rc_config);1202	if (p->rc_mb) {1203		reg = 0;1204		/** dark region */1205		reg |= ((p_h264->rc_mb_dark & 0x1) << 3);1206		/** smooth region */1207		reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);1208		/** static region */1209		reg |= ((p_h264->rc_mb_static & 0x1) << 1);1210		/** high activity region */1211		reg |= p_h264->rc_mb_activity & 0x1;1212		writel(reg, mfc_regs->e_mb_rc_config);1213	}1214 1215	/* aspect ratio VUI */1216	reg = readl(mfc_regs->e_h264_options);1217	reg &= ~(0x1 << 5);1218	reg |= ((p_h264->vui_sar & 0x1) << 5);1219	writel(reg, mfc_regs->e_h264_options);1220 1221	writel(0x0, mfc_regs->e_aspect_ratio);1222	writel(0x0, mfc_regs->e_extended_sar);1223	if (p_h264->vui_sar) {1224		/* aspect ration IDC */1225		reg = 0;1226		reg |= p_h264->vui_sar_idc & 0xFF;1227		writel(reg, mfc_regs->e_aspect_ratio);1228		if (p_h264->vui_sar_idc == 0xFF) {1229			/* extended SAR */1230			reg = 0;1231			reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;1232			reg |= p_h264->vui_ext_sar_height & 0xFFFF;1233			writel(reg, mfc_regs->e_extended_sar);1234		}1235	}1236 1237	/* intra picture period for H.264 open GOP */1238	/* control */1239	reg = readl(mfc_regs->e_h264_options);1240	reg &= ~(0x1 << 4);1241	reg |= ((p_h264->open_gop & 0x1) << 4);1242	writel(reg, mfc_regs->e_h264_options);1243 1244	/* value */1245	writel(0x0, mfc_regs->e_h264_i_period);1246	if (p_h264->open_gop) {1247		reg = 0;1248		reg |= p_h264->open_gop_size & 0xFFFF;1249		writel(reg, mfc_regs->e_h264_i_period);1250	}1251 1252	/* 'WEIGHTED_BI_PREDICTION' for B is disable */1253	reg = readl(mfc_regs->e_h264_options);1254	reg &= ~(0x3 << 9);1255	writel(reg, mfc_regs->e_h264_options);1256 1257	/* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */1258	reg = readl(mfc_regs->e_h264_options);1259	reg &= ~(0x1 << 14);1260	writel(reg, mfc_regs->e_h264_options);1261 1262	/* ASO */1263	reg = readl(mfc_regs->e_h264_options);1264	reg &= ~(0x1 << 6);1265	reg |= ((p_h264->aso & 0x1) << 6);1266	writel(reg, mfc_regs->e_h264_options);1267 1268	/* hier qp enable */1269	reg = readl(mfc_regs->e_h264_options);1270	reg &= ~(0x1 << 8);1271	reg |= ((p_h264->open_gop & 0x1) << 8);1272	writel(reg, mfc_regs->e_h264_options);1273	reg = 0;1274	if (p_h264->hier_qp && p_h264->hier_qp_layer) {1275		reg |= (p_h264->hier_qp_type & 0x1) << 0x3;1276		reg |= p_h264->hier_qp_layer & 0x7;1277		writel(reg, mfc_regs->e_h264_num_t_layer);1278		/* QP value for each layer */1279		for (i = 0; i < p_h264->hier_qp_layer &&1280				i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {1281			writel(p_h264->hier_qp_layer_qp[i],1282				mfc_regs->e_h264_hierarchical_qp_layer01283				+ i * 4);1284		}1285	}1286	/* number of coding layer should be zero when hierarchical is disable */1287	writel(reg, mfc_regs->e_h264_num_t_layer);1288 1289	/* frame packing SEI generation */1290	reg = readl(mfc_regs->e_h264_options);1291	reg &= ~(0x1 << 25);1292	reg |= ((p_h264->sei_frame_packing & 0x1) << 25);1293	writel(reg, mfc_regs->e_h264_options);1294	if (p_h264->sei_frame_packing) {1295		reg = 0;1296		/** current frame0 flag */1297		reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);1298		/** arrangement type */1299		reg |= p_h264->sei_fp_arrangement_type & 0x3;1300		writel(reg, mfc_regs->e_h264_frame_packing_sei_info);1301	}1302 1303	if (p_h264->fmo) {1304		switch (p_h264->fmo_map_type) {1305		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:1306			if (p_h264->fmo_slice_grp > 4)1307				p_h264->fmo_slice_grp = 4;1308			for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)1309				writel(p_h264->fmo_run_len[i] - 1,1310					mfc_regs->e_h264_fmo_run_length_minus1_01311					+ i * 4);1312			break;1313		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:1314			if (p_h264->fmo_slice_grp > 4)1315				p_h264->fmo_slice_grp = 4;1316			break;1317		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:1318		case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:1319			if (p_h264->fmo_slice_grp > 2)1320				p_h264->fmo_slice_grp = 2;1321			writel(p_h264->fmo_chg_dir & 0x1,1322				mfc_regs->e_h264_fmo_slice_grp_change_dir);1323			/* the valid range is 0 ~ number of macroblocks -1 */1324			writel(p_h264->fmo_chg_rate,1325			mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);1326			break;1327		default:1328			mfc_err("Unsupported map type for FMO: %d\n",1329					p_h264->fmo_map_type);1330			p_h264->fmo_map_type = 0;1331			p_h264->fmo_slice_grp = 1;1332			break;1333		}1334 1335		writel(p_h264->fmo_map_type,1336				mfc_regs->e_h264_fmo_slice_grp_map_type);1337		writel(p_h264->fmo_slice_grp - 1,1338				mfc_regs->e_h264_fmo_num_slice_grp_minus1);1339	} else {1340		writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);1341	}1342 1343	mfc_debug_leave();1344 1345	return 0;1346}1347 1348static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)1349{1350	struct s5p_mfc_dev *dev = ctx->dev;1351	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1352	const struct s5p_mfc_enc_params *p = &ctx->enc_params;1353	const struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;1354	unsigned int reg = 0;1355 1356	mfc_debug_enter();1357 1358	s5p_mfc_set_enc_params(ctx);1359 1360	/* pictype : number of B */1361	reg = readl(mfc_regs->e_gop_config);1362	reg &= ~(0x3 << 16);1363	reg |= ((p->num_b_frame & 0x3) << 16);1364	writel(reg, mfc_regs->e_gop_config);1365 1366	/* profile & level */1367	reg = 0;1368	/** level */1369	reg |= ((p_mpeg4->level & 0xFF) << 8);1370	/** profile - 0 ~ 1 */1371	reg |= p_mpeg4->profile & 0x3F;1372	writel(reg, mfc_regs->e_picture_profile);1373 1374	/* rate control config. */1375	reg = readl(mfc_regs->e_rc_config);1376	/** macroblock level rate control */1377	reg &= ~(0x1 << 8);1378	reg |= ((p->rc_mb & 0x1) << 8);1379	writel(reg, mfc_regs->e_rc_config);1380 1381	/** frame QP */1382	reg &= ~(0x3F);1383	reg |= p_mpeg4->rc_frame_qp & 0x3F;1384	writel(reg, mfc_regs->e_rc_config);1385 1386	/* max & min value of QP */1387	reg = 0;1388	/** max QP */1389	reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);1390	/** min QP */1391	reg |= p_mpeg4->rc_min_qp & 0x3F;1392	writel(reg, mfc_regs->e_rc_qp_bound);1393 1394	/* other QPs */1395	writel(0x0, mfc_regs->e_fixed_picture_qp);1396	if (!p->rc_frame && !p->rc_mb) {1397		reg = 0;1398		reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);1399		reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);1400		reg |= p_mpeg4->rc_frame_qp & 0x3F;1401		writel(reg, mfc_regs->e_fixed_picture_qp);1402	}1403 1404	/* frame rate */1405	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {1406		reg = 0;1407		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);1408		reg |= p->rc_framerate_denom & 0xFFFF;1409		writel(reg, mfc_regs->e_rc_frame_rate);1410	}1411 1412	/* vbv buffer size */1413	if (p->frame_skip_mode ==1414			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {1415		writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);1416 1417		if (p->rc_frame)1418			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);1419	}1420 1421	/* Disable HEC */1422	writel(0x0, mfc_regs->e_mpeg4_options);1423	writel(0x0, mfc_regs->e_mpeg4_hec_period);1424 1425	mfc_debug_leave();1426 1427	return 0;1428}1429 1430static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)1431{1432	struct s5p_mfc_dev *dev = ctx->dev;1433	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1434	const struct s5p_mfc_enc_params *p = &ctx->enc_params;1435	const struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;1436	unsigned int reg = 0;1437 1438	mfc_debug_enter();1439 1440	s5p_mfc_set_enc_params(ctx);1441 1442	/* profile & level */1443	reg = 0;1444	/** profile */1445	reg |= (0x1 << 4);1446	writel(reg, mfc_regs->e_picture_profile);1447 1448	/* rate control config. */1449	reg = readl(mfc_regs->e_rc_config);1450	/** macroblock level rate control */1451	reg &= ~(0x1 << 8);1452	reg |= ((p->rc_mb & 0x1) << 8);1453	writel(reg, mfc_regs->e_rc_config);1454 1455	/** frame QP */1456	reg &= ~(0x3F);1457	reg |= p_h263->rc_frame_qp & 0x3F;1458	writel(reg, mfc_regs->e_rc_config);1459 1460	/* max & min value of QP */1461	reg = 0;1462	/** max QP */1463	reg |= ((p_h263->rc_max_qp & 0x3F) << 8);1464	/** min QP */1465	reg |= p_h263->rc_min_qp & 0x3F;1466	writel(reg, mfc_regs->e_rc_qp_bound);1467 1468	/* other QPs */1469	writel(0x0, mfc_regs->e_fixed_picture_qp);1470	if (!p->rc_frame && !p->rc_mb) {1471		reg = 0;1472		reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);1473		reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);1474		reg |= p_h263->rc_frame_qp & 0x3F;1475		writel(reg, mfc_regs->e_fixed_picture_qp);1476	}1477 1478	/* frame rate */1479	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {1480		reg = 0;1481		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);1482		reg |= p->rc_framerate_denom & 0xFFFF;1483		writel(reg, mfc_regs->e_rc_frame_rate);1484	}1485 1486	/* vbv buffer size */1487	if (p->frame_skip_mode ==1488			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {1489		writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);1490 1491		if (p->rc_frame)1492			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);1493	}1494 1495	mfc_debug_leave();1496 1497	return 0;1498}1499 1500static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)1501{1502	struct s5p_mfc_dev *dev = ctx->dev;1503	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1504	const struct s5p_mfc_enc_params *p = &ctx->enc_params;1505	const struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;1506	unsigned int reg = 0;1507	unsigned int val = 0;1508 1509	mfc_debug_enter();1510 1511	s5p_mfc_set_enc_params(ctx);1512 1513	/* pictype : number of B */1514	reg = readl(mfc_regs->e_gop_config);1515	reg &= ~(0x3 << 16);1516	reg |= ((p->num_b_frame & 0x3) << 16);1517	writel(reg, mfc_regs->e_gop_config);1518 1519	/* profile - 0 ~ 3 */1520	reg = p_vp8->profile & 0x3;1521	writel(reg, mfc_regs->e_picture_profile);1522 1523	/* rate control config. */1524	reg = readl(mfc_regs->e_rc_config);1525	/** macroblock level rate control */1526	reg &= ~(0x1 << 8);1527	reg |= ((p->rc_mb & 0x1) << 8);1528	writel(reg, mfc_regs->e_rc_config);1529 1530	/* frame rate */1531	if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {1532		reg = 0;1533		reg |= ((p->rc_framerate_num & 0xFFFF) << 16);1534		reg |= p->rc_framerate_denom & 0xFFFF;1535		writel(reg, mfc_regs->e_rc_frame_rate);1536	}1537 1538	/* frame QP */1539	reg &= ~(0x7F);1540	reg |= p_vp8->rc_frame_qp & 0x7F;1541	writel(reg, mfc_regs->e_rc_config);1542 1543	/* other QPs */1544	writel(0x0, mfc_regs->e_fixed_picture_qp);1545	if (!p->rc_frame && !p->rc_mb) {1546		reg = 0;1547		reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);1548		reg |= p_vp8->rc_frame_qp & 0x7F;1549		writel(reg, mfc_regs->e_fixed_picture_qp);1550	}1551 1552	/* max QP */1553	reg = ((p_vp8->rc_max_qp & 0x7F) << 8);1554	/* min QP */1555	reg |= p_vp8->rc_min_qp & 0x7F;1556	writel(reg, mfc_regs->e_rc_qp_bound);1557 1558	/* vbv buffer size */1559	if (p->frame_skip_mode ==1560			V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {1561		writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);1562 1563		if (p->rc_frame)1564			writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);1565	}1566 1567	/* VP8 specific params */1568	reg = 0;1569	reg |= (p_vp8->imd_4x4 & 0x1) << 10;1570	switch (p_vp8->num_partitions) {1571	case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:1572		val = 0;1573		break;1574	case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:1575		val = 2;1576		break;1577	case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:1578		val = 4;1579		break;1580	case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:1581		val = 8;1582		break;1583	}1584	reg |= (val & 0xF) << 3;1585	reg |= (p_vp8->num_ref & 0x2);1586	writel(reg, mfc_regs->e_vp8_options);1587 1588	mfc_debug_leave();1589 1590	return 0;1591}1592 1593static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)1594{1595	struct s5p_mfc_dev *dev = ctx->dev;1596	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1597	struct s5p_mfc_enc_params *p = &ctx->enc_params;1598	struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;1599	unsigned int reg = 0;1600	int i;1601 1602	mfc_debug_enter();1603 1604	s5p_mfc_set_enc_params(ctx);1605 1606	/* pictype : number of B */1607	reg = readl(mfc_regs->e_gop_config);1608	/* num_b_frame - 0 ~ 2 */1609	reg &= ~(0x3 << 16);1610	reg |= (p->num_b_frame << 16);1611	writel(reg, mfc_regs->e_gop_config);1612 1613	/* UHD encoding case */1614	if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {1615		p_hevc->level = 51;1616		p_hevc->tier = 0;1617	/* this tier can be changed */1618	}1619 1620	/* tier & level */1621	reg = 0;1622	/* profile */1623	reg |= p_hevc->profile & 0x3;1624	/* level */1625	reg &= ~(0xFF << 8);1626	reg |= (p_hevc->level << 8);1627	/* tier - 0 ~ 1 */1628	reg |= (p_hevc->tier << 16);1629	writel(reg, mfc_regs->e_picture_profile);1630 1631	switch (p_hevc->loopfilter) {1632	case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED:1633		p_hevc->loopfilter_disable = 1;1634		break;1635	case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED:1636		p_hevc->loopfilter_disable = 0;1637		p_hevc->loopfilter_across = 1;1638		break;1639	case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY:1640		p_hevc->loopfilter_disable = 0;1641		p_hevc->loopfilter_across = 0;1642		break;1643	}1644 1645	/* max partition depth */1646	reg = 0;1647	reg |= (p_hevc->max_partition_depth & 0x1);1648	reg |= (p_hevc->num_refs_for_p-1) << 2;1649	reg |= (p_hevc->refreshtype & 0x3) << 3;1650	reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;1651	reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;1652	reg |= (p_hevc->wavefront_enable & 0x1) << 7;1653	reg |= (p_hevc->loopfilter_disable & 0x1) << 8;1654	reg |= (p_hevc->loopfilter_across & 0x1) << 9;1655	reg |= (p_hevc->enable_ltr & 0x1) << 10;1656	reg |= (p_hevc->hier_qp_enable & 0x1) << 11;1657	reg |= (p_hevc->general_pb_enable & 0x1) << 13;1658	reg |= (p_hevc->temporal_id_enable & 0x1) << 14;1659	reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;1660	reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;1661	reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;1662	reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;1663	reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 23;1664	reg |= (p_hevc->prepend_sps_pps_to_idr << 26);1665 1666	writel(reg, mfc_regs->e_hevc_options);1667	/* refresh period */1668	if (p_hevc->refreshtype) {1669		reg = 0;1670		reg |= (p_hevc->refreshperiod & 0xFFFF);1671		writel(reg, mfc_regs->e_hevc_refresh_period);1672	}1673	/* loop filter setting */1674	if (!(p_hevc->loopfilter_disable & 0x1)) {1675		reg = 0;1676		reg |= (p_hevc->lf_beta_offset_div2);1677		writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);1678		reg = 0;1679		reg |= (p_hevc->lf_tc_offset_div2);1680		writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);1681	}1682	/* hier qp enable */1683	if (p_hevc->num_hier_layer) {1684		reg = 0;1685		reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;1686		reg |= p_hevc->num_hier_layer & 0x7;1687		writel(reg, mfc_regs->e_num_t_layer);1688		/* QP value for each layer */1689		if (p_hevc->hier_qp_enable) {1690			for (i = 0; i < 7; i++)1691				writel(p_hevc->hier_qp_layer[i],1692					mfc_regs->e_hier_qp_layer0 + i * 4);1693		}1694		if (p->rc_frame) {1695			for (i = 0; i < 7; i++)1696				writel(p_hevc->hier_bit_layer[i],1697						mfc_regs->e_hier_bit_rate_layer01698						+ i * 4);1699		}1700	}1701 1702	/* rate control config. */1703	reg = readl(mfc_regs->e_rc_config);1704	/* macroblock level rate control */1705	reg &= ~(0x1 << 8);1706	reg |= (p->rc_mb << 8);1707	writel(reg, mfc_regs->e_rc_config);1708	/* frame QP */1709	reg &= ~(0xFF);1710	reg |= p_hevc->rc_frame_qp;1711	writel(reg, mfc_regs->e_rc_config);1712 1713	/* frame rate */1714	if (p->rc_frame) {1715		reg = 0;1716		reg &= ~(0xFFFF << 16);1717		reg |= ((p_hevc->rc_framerate) << 16);1718		reg &= ~(0xFFFF);1719		reg |= FRAME_DELTA_DEFAULT;1720		writel(reg, mfc_regs->e_rc_frame_rate);1721	}1722 1723	/* max & min value of QP */1724	reg = 0;1725	/* max QP */1726	reg &= ~(0xFF << 8);1727	reg |= (p_hevc->rc_max_qp << 8);1728	/* min QP */1729	reg &= ~(0xFF);1730	reg |= p_hevc->rc_min_qp;1731	writel(reg, mfc_regs->e_rc_qp_bound);1732 1733	writel(0x0, mfc_regs->e_fixed_picture_qp);1734	if (!p->rc_frame && !p->rc_mb) {1735		reg = 0;1736		reg &= ~(0xFF << 16);1737		reg |= (p_hevc->rc_b_frame_qp << 16);1738		reg &= ~(0xFF << 8);1739		reg |= (p_hevc->rc_p_frame_qp << 8);1740		reg &= ~(0xFF);1741		reg |= p_hevc->rc_frame_qp;1742		writel(reg, mfc_regs->e_fixed_picture_qp);1743	}1744	mfc_debug_leave();1745 1746	return 0;1747}1748 1749/* Initialize decoding */1750static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)1751{1752	struct s5p_mfc_dev *dev = ctx->dev;1753	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1754	unsigned int reg = 0;1755	int fmo_aso_ctrl = 0;1756 1757	mfc_debug_enter();1758	mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,1759			S5P_FIMV_CH_SEQ_HEADER_V6);1760	mfc_debug(2, "BUFs: %08x %08x %08x\n",1761		  readl(mfc_regs->d_cpb_buffer_addr),1762		  readl(mfc_regs->d_cpb_buffer_addr),1763		  readl(mfc_regs->d_cpb_buffer_addr));1764 1765	/* FMO_ASO_CTRL - 0: Enable, 1: Disable */1766	reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);1767 1768	if (ctx->display_delay_enable) {1769		reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);1770		writel(ctx->display_delay, mfc_regs->d_display_delay);1771	}1772 1773	if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {1774		writel(reg, mfc_regs->d_dec_options);1775		reg = 0;1776	}1777 1778	/* Setup loop filter, for decoding this is only valid for MPEG4 */1779	if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {1780		mfc_debug(2, "Set loop filter to: %d\n",1781				ctx->loop_filter_mpeg4);1782		reg |= (ctx->loop_filter_mpeg4 <<1783				S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);1784	}1785	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)1786		reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);1787 1788	if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))1789		writel(reg, mfc_regs->d_init_buffer_options);1790	else1791		writel(reg, mfc_regs->d_dec_options);1792 1793	/* 0: NV12(CbCr), 1: NV21(CrCb), 2: YV12(CrCb), 3: I420(CbCr) */1794	if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M)1795		writel(0x3, mfc_regs->pixel_format);1796	else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)1797		writel(0x2, mfc_regs->pixel_format);1798	else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)1799		writel(0x1, mfc_regs->pixel_format);1800	else1801		writel(0x0, mfc_regs->pixel_format);1802 1803 1804	/* sei parse */1805	writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);1806 1807	writel(ctx->inst_no, mfc_regs->instance_id);1808	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,1809			S5P_FIMV_CH_SEQ_HEADER_V6, NULL);1810 1811	mfc_debug_leave();1812	return 0;1813}1814 1815static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)1816{1817	struct s5p_mfc_dev *dev = ctx->dev;1818	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1819 1820	if (flush) {1821		dev->curr_ctx = ctx->num;1822		writel(ctx->inst_no, mfc_regs->instance_id);1823		s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,1824				S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);1825	}1826}1827 1828/* Decode a single frame */1829static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,1830			enum s5p_mfc_decode_arg last_frame)1831{1832	struct s5p_mfc_dev *dev = ctx->dev;1833	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1834 1835	writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);1836	writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);1837 1838	writel(ctx->inst_no, mfc_regs->instance_id);1839	/* Issue different commands to instance basing on whether it1840	 * is the last frame or not. */1841	switch (last_frame) {1842	case 0:1843		s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,1844				S5P_FIMV_CH_FRAME_START_V6, NULL);1845		break;1846	case 1:1847		s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,1848				S5P_FIMV_CH_LAST_FRAME_V6, NULL);1849		break;1850	default:1851		mfc_err("Unsupported last frame arg.\n");1852		return -EINVAL;1853	}1854 1855	mfc_debug(2, "Decoding a usual frame.\n");1856	return 0;1857}1858 1859static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)1860{1861	struct s5p_mfc_dev *dev = ctx->dev;1862	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1863 1864	if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)1865		s5p_mfc_set_enc_params_h264(ctx);1866	else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)1867		s5p_mfc_set_enc_params_mpeg4(ctx);1868	else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)1869		s5p_mfc_set_enc_params_h263(ctx);1870	else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)1871		s5p_mfc_set_enc_params_vp8(ctx);1872	else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)1873		s5p_mfc_set_enc_params_hevc(ctx);1874	else {1875		mfc_err("Unknown codec for encoding (%x).\n",1876			ctx->codec_mode);1877		return -EINVAL;1878	}1879 1880	/* Set stride lengths for v7 & above */1881	if (IS_MFCV7_PLUS(dev)) {1882		writel(ctx->stride[0], mfc_regs->e_source_first_plane_stride);1883		writel(ctx->stride[1], mfc_regs->e_source_second_plane_stride);1884		if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==1885				V4L2_PIX_FMT_YVU420M)1886			writel(ctx->stride[2], mfc_regs->e_source_third_plane_stride);1887	}1888 1889	writel(ctx->inst_no, mfc_regs->instance_id);1890	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,1891			S5P_FIMV_CH_SEQ_HEADER_V6, NULL);1892 1893	return 0;1894}1895 1896static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)1897{1898	struct s5p_mfc_dev *dev = ctx->dev;1899	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1900	const struct s5p_mfc_enc_params *p = &ctx->enc_params;1901	const struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;1902	int i;1903 1904	if (p_h264->aso) {1905		for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {1906			writel(p_h264->aso_slice_order[i],1907				mfc_regs->e_h264_aso_slice_order_0 + i * 4);1908		}1909	}1910	return 0;1911}1912 1913/* Encode a single frame */1914static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)1915{1916	struct s5p_mfc_dev *dev = ctx->dev;1917	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;1918	int cmd;1919 1920	mfc_debug(2, "++\n");1921 1922	/* memory structure cur. frame */1923 1924	if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)1925		s5p_mfc_h264_set_aso_slice_order_v6(ctx);1926 1927	s5p_mfc_set_slice_mode(ctx);1928 1929	if (ctx->state != MFCINST_FINISHING)1930		cmd = S5P_FIMV_CH_FRAME_START_V6;1931	else1932		cmd = S5P_FIMV_CH_LAST_FRAME_V6;1933 1934	writel(ctx->inst_no, mfc_regs->instance_id);1935	s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, cmd, NULL);1936 1937	mfc_debug(2, "--\n");1938 1939	return 0;1940}1941 1942static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)1943{1944	struct s5p_mfc_dev *dev = ctx->dev;1945 1946	s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);1947	dev->curr_ctx = ctx->num;1948	s5p_mfc_decode_one_frame_v6(ctx, MFC_DEC_LAST_FRAME);1949}1950 1951static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)1952{1953	struct s5p_mfc_dev *dev = ctx->dev;1954	struct s5p_mfc_buf *temp_vb;1955	int last_frame = 0;1956 1957	if (ctx->state == MFCINST_FINISHING) {1958		last_frame = MFC_DEC_LAST_FRAME;1959		s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);1960		dev->curr_ctx = ctx->num;1961		s5p_mfc_clean_ctx_int_flags(ctx);1962		s5p_mfc_decode_one_frame_v6(ctx, last_frame);1963		return 0;1964	}1965 1966	/* Frames are being decoded */1967	if (list_empty(&ctx->src_queue)) {1968		mfc_debug(2, "No src buffers.\n");1969		return -EAGAIN;1970	}1971	/* Get the next source buffer */1972	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);1973	temp_vb->flags |= MFC_BUF_FLAG_USED;1974	s5p_mfc_set_dec_stream_buffer_v6(ctx,1975		vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),1976			ctx->consumed_stream,1977			temp_vb->b->vb2_buf.planes[0].bytesused);1978 1979	dev->curr_ctx = ctx->num;1980	if (temp_vb->b->vb2_buf.planes[0].bytesused == 0) {1981		last_frame = 1;1982		mfc_debug(2, "Setting ctx->state to FINISHING\n");1983		ctx->state = MFCINST_FINISHING;1984	}1985	s5p_mfc_decode_one_frame_v6(ctx, last_frame);1986 1987	return 0;1988}1989 1990static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)1991{1992	struct s5p_mfc_dev *dev = ctx->dev;1993	struct s5p_mfc_buf *dst_mb;1994	struct s5p_mfc_buf *src_mb;1995	unsigned long src_y_addr, src_c_addr, src_c_1_addr, dst_addr;1996	/*1997	unsigned int src_y_size, src_c_size;1998	*/1999	unsigned int dst_size;2000 2001	if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {2002		mfc_debug(2, "no src buffers.\n");2003		return -EAGAIN;2004	}2005 2006	if (list_empty(&ctx->dst_queue)) {2007		mfc_debug(2, "no dst buffers.\n");2008		return -EAGAIN;2009	}2010 2011	if (list_empty(&ctx->src_queue)) {2012		/* send null frame */2013		s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);2014		src_mb = NULL;2015	} else {2016		src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);2017		src_mb->flags |= MFC_BUF_FLAG_USED;2018		if (src_mb->b->vb2_buf.planes[0].bytesused == 0) {2019			s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);2020			ctx->state = MFCINST_FINISHING;2021		} else {2022			src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0);2023			src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1);2024			if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==2025					V4L2_PIX_FMT_YVU420M)2026				src_c_1_addr = vb2_dma_contig_plane_dma_addr2027					(&src_mb->b->vb2_buf, 2);2028			else2029				src_c_1_addr = 0;2030 2031			mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);2032			mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);2033 2034			s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr, src_c_1_addr);2035			if (src_mb->flags & MFC_BUF_FLAG_EOS)2036				ctx->state = MFCINST_FINISHING;2037		}2038	}2039 2040	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);2041	dst_mb->flags |= MFC_BUF_FLAG_USED;2042	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);2043	dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);2044 2045	s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);2046 2047	dev->curr_ctx = ctx->num;2048	s5p_mfc_encode_one_frame_v6(ctx);2049 2050	return 0;2051}2052 2053static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)2054{2055	struct s5p_mfc_dev *dev = ctx->dev;2056	struct s5p_mfc_buf *temp_vb;2057 2058	/* Initializing decoding - parsing header */2059	mfc_debug(2, "Preparing to init decoding.\n");2060	temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);2061	mfc_debug(2, "Header size: %d\n", temp_vb->b->vb2_buf.planes[0].bytesused);2062	s5p_mfc_set_dec_stream_buffer_v6(ctx,2063		vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), 0,2064			temp_vb->b->vb2_buf.planes[0].bytesused);2065	dev->curr_ctx = ctx->num;2066	s5p_mfc_init_decode_v6(ctx);2067}2068 2069static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)2070{2071	struct s5p_mfc_dev *dev = ctx->dev;2072	struct s5p_mfc_buf *dst_mb;2073	unsigned long dst_addr;2074	unsigned int dst_size;2075 2076	dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);2077	dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);2078	dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);2079	s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);2080	dev->curr_ctx = ctx->num;2081	s5p_mfc_init_encode_v6(ctx);2082}2083 2084static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)2085{2086	struct s5p_mfc_dev *dev = ctx->dev;2087	int ret;2088	/* Header was parsed now start processing2089	 * First set the output frame buffers2090	 * s5p_mfc_alloc_dec_buffers(ctx); */2091 2092	if (ctx->capture_state != QUEUE_BUFS_MMAPED) {2093		mfc_err("It seems that not all destination buffers were\n"2094			"mmapped.MFC requires that all destination are mmapped\n"2095			"before starting processing.\n");2096		return -EAGAIN;2097	}2098 2099	dev->curr_ctx = ctx->num;2100	ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);2101	if (ret) {2102		mfc_err("Failed to alloc frame mem.\n");2103		ctx->state = MFCINST_ERROR;2104	}2105	return ret;2106}2107 2108static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)2109{2110	struct s5p_mfc_dev *dev = ctx->dev;2111	int ret;2112 2113	ret = s5p_mfc_hw_call(ctx->dev->mfc_ops, alloc_codec_buffers, ctx);2114	if (ret) {2115		mfc_err("Failed to allocate encoding buffers\n");2116		return -ENOMEM;2117	}2118	mfc_debug(2, "Allocated Internal Encoding Buffers\n");2119 2120	dev->curr_ctx = ctx->num;2121	ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);2122	if (ret) {2123		mfc_err("Failed to alloc frame mem.\n");2124		ctx->state = MFCINST_ERROR;2125	}2126	return ret;2127}2128 2129/* Try running an operation on hardware */2130static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)2131{2132	struct s5p_mfc_ctx *ctx;2133	int new_ctx;2134	unsigned int ret = 0;2135 2136	mfc_debug(1, "Try run dev: %p\n", dev);2137 2138	/* Check whether hardware is not running */2139	if (test_and_set_bit(0, &dev->hw_lock) != 0) {2140		/* This is perfectly ok, the scheduled ctx should wait */2141		mfc_debug(1, "Couldn't lock HW.\n");2142		return;2143	}2144 2145	/* Choose the context to run */2146	new_ctx = s5p_mfc_get_new_ctx(dev);2147	if (new_ctx < 0) {2148		/* No contexts to run */2149		if (test_and_clear_bit(0, &dev->hw_lock) == 0) {2150			mfc_err("Failed to unlock hardware.\n");2151			return;2152		}2153 2154		mfc_debug(1, "No ctx is scheduled to be run.\n");2155		return;2156	}2157 2158	mfc_debug(1, "New context: %d\n", new_ctx);2159	ctx = dev->ctx[new_ctx];2160	mfc_debug(1, "Setting new context to %p\n", ctx);2161	/* Got context to run in ctx */2162	mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",2163		ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);2164	mfc_debug(1, "ctx->state=%d\n", ctx->state);2165	/* Last frame has already been sent to MFC2166	 * Now obtaining frames from MFC buffer */2167 2168	s5p_mfc_clock_on(dev);2169	s5p_mfc_clean_ctx_int_flags(ctx);2170 2171	if (ctx->type == MFCINST_DECODER) {2172		switch (ctx->state) {2173		case MFCINST_FINISHING:2174			s5p_mfc_run_dec_last_frames(ctx);2175			break;2176		case MFCINST_RUNNING:2177			ret = s5p_mfc_run_dec_frame(ctx);2178			break;2179		case MFCINST_INIT:2180			ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,2181					ctx);2182			break;2183		case MFCINST_RETURN_INST:2184			ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,2185					ctx);2186			break;2187		case MFCINST_GOT_INST:2188			s5p_mfc_run_init_dec(ctx);2189			break;2190		case MFCINST_HEAD_PARSED:2191			ret = s5p_mfc_run_init_dec_buffers(ctx);2192			break;2193		case MFCINST_FLUSH:2194			s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);2195			break;2196		case MFCINST_RES_CHANGE_INIT:2197			s5p_mfc_run_dec_last_frames(ctx);2198			break;2199		case MFCINST_RES_CHANGE_FLUSH:2200			s5p_mfc_run_dec_last_frames(ctx);2201			break;2202		case MFCINST_RES_CHANGE_END:2203			mfc_debug(2, "Finished remaining frames after resolution change.\n");2204			ctx->capture_state = QUEUE_FREE;2205			mfc_debug(2, "Will re-init the codec`.\n");2206			s5p_mfc_run_init_dec(ctx);2207			break;2208		default:2209			ret = -EAGAIN;2210		}2211	} else if (ctx->type == MFCINST_ENCODER) {2212		switch (ctx->state) {2213		case MFCINST_FINISHING:2214		case MFCINST_RUNNING:2215			ret = s5p_mfc_run_enc_frame(ctx);2216			break;2217		case MFCINST_INIT:2218			ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,2219					ctx);2220			break;2221		case MFCINST_RETURN_INST:2222			ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,2223					ctx);2224			break;2225		case MFCINST_GOT_INST:2226			s5p_mfc_run_init_enc(ctx);2227			break;2228		case MFCINST_HEAD_PRODUCED:2229			ret = s5p_mfc_run_init_enc_buffers(ctx);2230			break;2231		default:2232			ret = -EAGAIN;2233		}2234	} else {2235		mfc_err("invalid context type: %d\n", ctx->type);2236		ret = -EAGAIN;2237	}2238 2239	if (ret) {2240		/* Free hardware lock */2241		if (test_and_clear_bit(0, &dev->hw_lock) == 0)2242			mfc_err("Failed to unlock hardware.\n");2243 2244		/* This is in deed imporant, as no operation has been2245		 * scheduled, reduce the clock count as no one will2246		 * ever do this, because no interrupt related to this try_run2247		 * will ever come from hardware. */2248		s5p_mfc_clock_off(dev);2249	}2250}2251 2252static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)2253{2254	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;2255	writel(0, mfc_regs->risc2host_command);2256	writel(0, mfc_regs->risc2host_int);2257}2258 2259static unsigned int2260s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned long ofs)2261{2262	int ret;2263 2264	s5p_mfc_clock_on(ctx->dev);2265	ret = readl((void __iomem *)ofs);2266	s5p_mfc_clock_off(ctx->dev);2267 2268	return ret;2269}2270 2271static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)2272{2273	return readl(dev->mfc_regs->d_display_first_plane_addr);2274}2275 2276static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)2277{2278	return readl(dev->mfc_regs->d_decoded_first_plane_addr);2279}2280 2281static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)2282{2283	return readl(dev->mfc_regs->d_display_status);2284}2285 2286static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)2287{2288	return readl(dev->mfc_regs->d_decoded_status);2289}2290 2291static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)2292{2293	return readl(dev->mfc_regs->d_decoded_frame_type) &2294		S5P_FIMV_DECODE_FRAME_MASK_V6;2295}2296 2297static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)2298{2299	struct s5p_mfc_dev *dev = ctx->dev;2300	return readl(dev->mfc_regs->d_display_frame_type) &2301		S5P_FIMV_DECODE_FRAME_MASK_V6;2302}2303 2304static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)2305{2306	return readl(dev->mfc_regs->d_decoded_nal_size);2307}2308 2309static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)2310{2311	return readl(dev->mfc_regs->risc2host_command) &2312		S5P_FIMV_RISC2HOST_CMD_MASK;2313}2314 2315static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)2316{2317	return readl(dev->mfc_regs->error_code);2318}2319 2320static int s5p_mfc_err_dec_v6(unsigned int err)2321{2322	return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;2323}2324 2325static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)2326{2327	return readl(dev->mfc_regs->d_display_frame_width);2328}2329 2330static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)2331{2332	return readl(dev->mfc_regs->d_display_frame_height);2333}2334 2335static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)2336{2337	return readl(dev->mfc_regs->d_min_num_dpb);2338}2339 2340static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)2341{2342	return readl(dev->mfc_regs->d_min_num_mv);2343}2344 2345static int s5p_mfc_get_min_scratch_buf_size(struct s5p_mfc_dev *dev)2346{2347	return readl(dev->mfc_regs->d_min_scratch_buffer_size);2348}2349 2350static int s5p_mfc_get_e_min_scratch_buf_size(struct s5p_mfc_dev *dev)2351{2352	return readl(dev->mfc_regs->e_min_scratch_buffer_size);2353}2354 2355static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)2356{2357	return readl(dev->mfc_regs->ret_instance_id);2358}2359 2360static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)2361{2362	return readl(dev->mfc_regs->e_num_dpb);2363}2364 2365static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)2366{2367	return readl(dev->mfc_regs->e_stream_size);2368}2369 2370static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)2371{2372	return readl(dev->mfc_regs->e_slice_type);2373}2374 2375static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)2376{2377	return s5p_mfc_read_info_v6(ctx,2378		(__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top);2379}2380 2381static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)2382{2383	return s5p_mfc_read_info_v6(ctx,2384		(__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot);2385}2386 2387static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)2388{2389	return s5p_mfc_read_info_v6(ctx,2390		(__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1);2391}2392 2393static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)2394{2395	return s5p_mfc_read_info_v6(ctx,2396		(__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2);2397}2398 2399static struct s5p_mfc_regs mfc_regs;2400 2401/* Initialize registers for MFC v6 onwards */2402const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)2403{2404	memset(&mfc_regs, 0, sizeof(mfc_regs));2405 2406#define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))2407#define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)2408	/* codec common registers */2409	R(risc_on, S5P_FIMV_RISC_ON_V6);2410	R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);2411	R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);2412	R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);2413	R(mfc_reset, S5P_FIMV_MFC_RESET_V6);2414	R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);2415	R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);2416	R(firmware_version, S5P_FIMV_FW_VERSION_V6);2417	R(instance_id, S5P_FIMV_INSTANCE_ID_V6);2418	R(codec_type, S5P_FIMV_CODEC_TYPE_V6);2419	R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);2420	R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);2421	R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);2422	R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);2423	R(error_code, S5P_FIMV_ERROR_CODE_V6);2424 2425	/* decoder registers */2426	R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);2427	R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);2428	R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);2429	R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);2430	R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);2431	R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);2432	R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);2433	R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);2434	R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);2435	R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);2436	R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);2437	R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);2438	R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);2439	R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);2440	R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);2441	R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);2442	R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);2443	R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);2444	R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);2445	R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);2446	R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);2447	R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);2448	R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);2449	R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);2450	R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);2451	R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);2452	R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);2453	R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);2454	R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);2455	R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);2456	R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);2457	R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);2458	R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);2459	R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);2460	R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);2461	R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);2462	R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);2463	R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);2464	R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);2465	R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);2466	R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);2467	R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);2468	R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);2469	R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);2470 2471	/* encoder registers */2472	R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);2473	R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);2474	R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);2475	R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);2476	R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);2477	R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);2478	R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);2479	R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);2480	R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);2481	R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);2482	R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);2483	R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);2484	R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);2485	R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);2486	R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);2487	R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);2488	R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);2489	R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);2490	R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);2491	R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);2492	R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);2493	R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);2494	R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);2495	R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);2496	R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);2497	R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);2498	R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);2499	R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);2500	R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);2501	R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);2502	R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);2503	R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);2504	R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);2505	R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);2506	R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);2507	R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);2508	R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);2509	R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);2510	R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);2511	R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);2512	R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);2513	R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);2514	R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);2515	R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);2516	R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);2517	R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);2518	R(e_encoded_source_first_plane_addr,2519			S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);2520	R(e_encoded_source_second_plane_addr,2521			S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);2522	R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);2523	R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);2524	R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);2525	R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);2526	R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);2527	R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);2528	R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);2529	R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);2530	R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);2531	R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);2532	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);2533	R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);2534	R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);2535	R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);2536	R(e_h264_fmo_slice_grp_map_type,2537			S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);2538	R(e_h264_fmo_num_slice_grp_minus1,2539			S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);2540	R(e_h264_fmo_slice_grp_change_dir,2541			S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);2542	R(e_h264_fmo_slice_grp_change_rate_minus1,2543			S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);2544	R(e_h264_fmo_run_length_minus1_0,2545			S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);2546	R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);2547	R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);2548	R(e_h264_hierarchical_qp_layer0,2549			S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);2550	R(e_h264_frame_packing_sei_info,2551			S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);2552 2553	if (!IS_MFCV7_PLUS(dev))2554		goto done;2555 2556	/* Initialize registers used in MFC v7+ */2557	R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);2558	R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);2559	R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);2560	R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);2561	R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);2562	R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);2563	R(e_encoded_source_first_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);2564	R(e_encoded_source_second_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);2565	R(e_encoded_source_third_plane_addr, S5P_FIMV_E_ENCODED_SOURCE_THIRD_ADDR_V7);2566	R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);2567 2568	if (!IS_MFCV8_PLUS(dev))2569		goto done;2570 2571	/* Initialize registers used in MFC v8 only.2572	 * Also, over-write the registers which have2573	 * a different offset for MFC v8. */2574	R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8);2575	R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8);2576	R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8);2577	R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);2578	R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);2579	R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);2580	R(d_third_plane_dpb_size, S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8);2581	R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);2582	R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);2583	R(d_first_plane_dpb_stride_size, S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);2584	R(d_second_plane_dpb_stride_size, S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);2585	R(d_third_plane_dpb_stride_size, S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8);2586	R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);2587	R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);2588	R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);2589	R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);2590	R(d_third_plane_dpb, S5P_FIMV_D_THIRD_PLANE_DPB_V8);2591	R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);2592	R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);2593	R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);2594	R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8);2595	R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8);2596	R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8);2597	R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8);2598	R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8);2599	R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8);2600	R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8);2601	R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8);2602	R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8);2603	R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8);2604	R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8);2605	R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8);2606	R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8);2607	R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8);2608	R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8);2609	R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8);2610	R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);2611	R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);2612	R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);2613	R(d_min_scratch_buffer_size, S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8);2614 2615	/* encoder registers */2616	R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);2617	R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);2618	R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);2619	R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);2620	R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);2621	R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);2622	R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);2623	R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);2624	R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);2625	R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);2626	R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);2627	R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);2628	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);2629	R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);2630 2631	if (!IS_MFCV10_PLUS(dev))2632		goto done;2633 2634	/* Initialize registers used in MFC v10 only.2635	 * Also, over-write the registers which have2636	 * a different offset for MFC v10.2637	 */2638 2639	/* decoder registers */2640	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);2641	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);2642 2643	/* encoder registers */2644	R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);2645	R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);2646	R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);2647	R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);2648	R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);2649	R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);2650	R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);2651	R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);2652 2653done:2654	return &mfc_regs;2655#undef S5P_MFC_REG_ADDR2656#undef R2657}2658 2659/* Initialize opr function pointers for MFC v6 */2660static const struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {2661	.alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,2662	.release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,2663	.alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,2664	.release_codec_buffers = s5p_mfc_release_codec_buffers_v6,2665	.alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,2666	.release_instance_buffer = s5p_mfc_release_instance_buffer_v6,2667	.alloc_dev_context_buffer =2668		s5p_mfc_alloc_dev_context_buffer_v6,2669	.release_dev_context_buffer =2670		s5p_mfc_release_dev_context_buffer_v6,2671	.dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,2672	.enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,2673	.set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,2674	.set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,2675	.get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,2676	.try_run = s5p_mfc_try_run_v6,2677	.clear_int_flags = s5p_mfc_clear_int_flags_v6,2678	.get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,2679	.get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,2680	.get_dspl_status = s5p_mfc_get_dspl_status_v6,2681	.get_dec_status = s5p_mfc_get_dec_status_v6,2682	.get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,2683	.get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,2684	.get_consumed_stream = s5p_mfc_get_consumed_stream_v6,2685	.get_int_reason = s5p_mfc_get_int_reason_v6,2686	.get_int_err = s5p_mfc_get_int_err_v6,2687	.err_dec = s5p_mfc_err_dec_v6,2688	.get_img_width = s5p_mfc_get_img_width_v6,2689	.get_img_height = s5p_mfc_get_img_height_v6,2690	.get_dpb_count = s5p_mfc_get_dpb_count_v6,2691	.get_mv_count = s5p_mfc_get_mv_count_v6,2692	.get_inst_no = s5p_mfc_get_inst_no_v6,2693	.get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,2694	.get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,2695	.get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,2696	.get_pic_type_top = s5p_mfc_get_pic_type_top_v6,2697	.get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,2698	.get_crop_info_h = s5p_mfc_get_crop_info_h_v6,2699	.get_crop_info_v = s5p_mfc_get_crop_info_v_v6,2700	.get_min_scratch_buf_size = s5p_mfc_get_min_scratch_buf_size,2701	.get_e_min_scratch_buf_size = s5p_mfc_get_e_min_scratch_buf_size,2702};2703 2704const struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)2705{2706	return &s5p_mfc_ops_v6;2707}2708