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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)4 * Author: Yong Deng <yong.deng@magewell.com>5 * Copyright 2021-2022 Bootlin6 * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>7 */8 9#ifndef _SUN6I_CSI_REG_H_10#define _SUN6I_CSI_REG_H_11 12#include <linux/kernel.h>13 14#define SUN6I_CSI_ADDR_VALUE(a) ((a) >> 2)15 16#define SUN6I_CSI_EN_REG 0x017#define SUN6I_CSI_EN_VER_EN BIT(30)18#define SUN6I_CSI_EN_PTN_CYCLE(v) (((v) << 16) & GENMASK(23, 16))19#define SUN6I_CSI_EN_SRAM_PWDN BIT(8)20#define SUN6I_CSI_EN_PTN_START BIT(4)21#define SUN6I_CSI_EN_CLK_CNT_SPL_VSYNC BIT(3)22#define SUN6I_CSI_EN_CLK_CNT_EN BIT(2)23#define SUN6I_CSI_EN_PTN_GEN_EN BIT(1)24#define SUN6I_CSI_EN_CSI_EN BIT(0)25 26/* Note that Allwinner manuals and code invert positive/negative definitions. */27 28#define SUN6I_CSI_IF_CFG_REG 0x429#define SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(v) (((v) << 24) & GENMASK(27, 24))30#define SUN6I_CSI_IF_CFG_SRC_TYPE_PROGRESSIVE (0 << 21)31#define SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED (1 << 21)32#define SUN6I_CSI_IF_CFG_FPS_DS BIT(20)33#define SUN6I_CSI_IF_CFG_FIELD_POSITIVE (0 << 19)34#define SUN6I_CSI_IF_CFG_FIELD_NEGATIVE (1 << 19)35#define SUN6I_CSI_IF_CFG_VREF_POL_POSITIVE (0 << 18)36#define SUN6I_CSI_IF_CFG_VREF_POL_NEGATIVE (1 << 18)37#define SUN6I_CSI_IF_CFG_HREF_POL_POSITIVE (0 << 17)38#define SUN6I_CSI_IF_CFG_HREF_POL_NEGATIVE (1 << 17)39#define SUN6I_CSI_IF_CFG_CLK_POL_FALLING (0 << 16)40#define SUN6I_CSI_IF_CFG_CLK_POL_RISING (1 << 16)41#define SUN6I_CSI_IF_CFG_FIELD_DT_FIELD_VSYNC (0 << 14)42#define SUN6I_CSI_IF_CFG_FIELD_DT_FIELD (1 << 14)43#define SUN6I_CSI_IF_CFG_FIELD_DT_VSYNC (2 << 14)44#define SUN6I_CSI_IF_CFG_DATA_WIDTH_8 (0 << 8)45#define SUN6I_CSI_IF_CFG_DATA_WIDTH_10 (1 << 8)46#define SUN6I_CSI_IF_CFG_DATA_WIDTH_12 (2 << 8)47#define SUN6I_CSI_IF_CFG_DATA_WIDTH_8_PLUS_2 (3 << 8)48#define SUN6I_CSI_IF_CFG_DATA_WIDTH_2_TIMES_8 (4 << 8)49#define SUN6I_CSI_IF_CFG_IF_CSI (0 << 7)50#define SUN6I_CSI_IF_CFG_IF_MIPI (1 << 7)51#define SUN6I_CSI_IF_CFG_IF_CSI_YUV_RAW (0 << 0)52#define SUN6I_CSI_IF_CFG_IF_CSI_YUV_COMBINED (1 << 0)53#define SUN6I_CSI_IF_CFG_IF_CSI_BT656 (4 << 0)54#define SUN6I_CSI_IF_CFG_IF_CSI_BT1120 (5 << 0)55 56#define SUN6I_CSI_CAP_REG 0x857#define SUN6I_CSI_CAP_MASK(v) (((v) << 2) & GENMASK(5, 2))58#define SUN6I_CSI_CAP_VCAP_ON BIT(1)59#define SUN6I_CSI_CAP_SCAP_ON BIT(0)60 61#define SUN6I_CSI_SYNC_CNT_REG 0xc62#define SUN6I_CSI_FIFO_THRS_REG 0x1063#define SUN6I_CSI_BT656_HEAD_CFG_REG 0x1464 65#define SUN6I_CSI_PTN_LEN_REG 0x3066#define SUN6I_CSI_PTN_ADDR_REG 0x3467#define SUN6I_CSI_VER_REG 0x3c68 69#define SUN6I_CSI_CH_CFG_REG 0x4470#define SUN6I_CSI_CH_CFG_PAD_VAL(v) (((v) << 24) & GENMASK(31, 24))71#define SUN6I_CSI_CH_CFG_INPUT_FMT(v) (((v) << 20) & GENMASK(23, 20))72#define SUN6I_CSI_CH_CFG_OUTPUT_FMT(v) (((v) << 16) & GENMASK(19, 16))73#define SUN6I_CSI_CH_CFG_VFLIP_EN BIT(13)74#define SUN6I_CSI_CH_CFG_HFLIP_EN BIT(12)75#define SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD0 (0 << 10)76#define SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD1 (1 << 10)77#define SUN6I_CSI_CH_CFG_FIELD_SEL_EITHER (2 << 10)78#define SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(v) (((v) << 8) & GENMASK(9, 8))79 80#define SUN6I_CSI_INPUT_FMT_RAW 081#define SUN6I_CSI_INPUT_FMT_YUV422 382#define SUN6I_CSI_INPUT_FMT_YUV420 483 84/* Note that Allwinner manuals and code invert frame/field definitions. */85 86/* RAW */87#define SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8 088#define SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10 189#define SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12 290#define SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565 491#define SUN6I_CSI_OUTPUT_FMT_FRAME_RGB888 592#define SUN6I_CSI_OUTPUT_FMT_FRAME_PRGB888 693#define SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8 894#define SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10 995#define SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12 1096#define SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565 1297#define SUN6I_CSI_OUTPUT_FMT_FIELD_RGB888 1398#define SUN6I_CSI_OUTPUT_FMT_FIELD_PRGB888 1499 100/* YUV */101#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422P 0102#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P 1103#define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P 2104#define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422P 3105#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP 4106#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP 5107#define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP 6108#define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP 7109#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422MB 8110#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420MB 9111#define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420MB 10112#define SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422MB 11113#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP_10 12114#define SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP_10 13115 116/* YUV Planar */117#define SUN6I_CSI_INPUT_YUV_SEQ_YUYV 0118#define SUN6I_CSI_INPUT_YUV_SEQ_YVYU 1119#define SUN6I_CSI_INPUT_YUV_SEQ_UYVY 2120#define SUN6I_CSI_INPUT_YUV_SEQ_VYUY 3121 122/* YUV Semi-planar */123#define SUN6I_CSI_INPUT_YUV_SEQ_UV 0124#define SUN6I_CSI_INPUT_YUV_SEQ_VU 1125 126#define SUN6I_CSI_CH_SCALE_REG 0x4c127#define SUN6I_CSI_CH_SCALE_QUART_EN BIT(0)128 129#define SUN6I_CSI_CH_FIFO0_ADDR_REG 0x50130#define SUN6I_CSI_CH_FIFO1_ADDR_REG 0x58131#define SUN6I_CSI_CH_FIFO2_ADDR_REG 0x60132 133#define SUN6I_CSI_CH_STA_REG 0x6c134#define SUN6I_CSI_CH_STA_FIELD BIT(2)135#define SUN6I_CSI_CH_STA_VCAP BIT(1)136#define SUN6I_CSI_CH_STA_SCAP BIT(0)137 138#define SUN6I_CSI_CH_INT_EN_REG 0x70139#define SUN6I_CSI_CH_INT_EN_VS BIT(7)140#define SUN6I_CSI_CH_INT_EN_HB_OF BIT(6)141#define SUN6I_CSI_CH_INT_EN_MUL_ERR BIT(5)142#define SUN6I_CSI_CH_INT_EN_FIFO2_OF BIT(4)143#define SUN6I_CSI_CH_INT_EN_FIFO1_OF BIT(3)144#define SUN6I_CSI_CH_INT_EN_FIFO0_OF BIT(2)145#define SUN6I_CSI_CH_INT_EN_FD BIT(1)146#define SUN6I_CSI_CH_INT_EN_CD BIT(0)147 148#define SUN6I_CSI_CH_INT_STA_REG 0x74149#define SUN6I_CSI_CH_INT_STA_CLEAR 0xff150#define SUN6I_CSI_CH_INT_STA_VS BIT(7)151#define SUN6I_CSI_CH_INT_STA_HB_OF BIT(6)152#define SUN6I_CSI_CH_INT_STA_MUL_ERR BIT(5)153#define SUN6I_CSI_CH_INT_STA_FIFO2_OF BIT(4)154#define SUN6I_CSI_CH_INT_STA_FIFO1_OF BIT(3)155#define SUN6I_CSI_CH_INT_STA_FIFO0_OF BIT(2)156#define SUN6I_CSI_CH_INT_STA_FD BIT(1)157#define SUN6I_CSI_CH_INT_STA_CD BIT(0)158 159#define SUN6I_CSI_CH_FLD1_VSIZE_REG 0x78160#define SUN6I_CSI_CH_FLD1_VSIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))161#define SUN6I_CSI_CH_FLD1_VSIZE_VER_START(v) ((v) & GENMASK(12, 0))162 163#define SUN6I_CSI_CH_HSIZE_REG 0x80164#define SUN6I_CSI_CH_HSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))165#define SUN6I_CSI_CH_HSIZE_START(v) ((v) & GENMASK(12, 0))166 167#define SUN6I_CSI_CH_VSIZE_REG 0x84168#define SUN6I_CSI_CH_VSIZE_LEN(v) (((v) << 16) & GENMASK(28, 16))169#define SUN6I_CSI_CH_VSIZE_START(v) ((v) & GENMASK(12, 0))170 171#define SUN6I_CSI_CH_BUF_LEN_REG 0x88172#define SUN6I_CSI_CH_BUF_LEN_CHROMA_LINE(v) (((v) << 16) & GENMASK(29, 16))173#define SUN6I_CSI_CH_BUF_LEN_LUMA_LINE(v) ((v) & GENMASK(13, 0))174 175#define SUN6I_CSI_CH_FLIP_SIZE_REG 0x8c176#define SUN6I_CSI_CH_FLIP_SIZE_VER_LEN(v) (((v) << 16) & GENMASK(28, 16))177#define SUN6I_CSI_CH_FLIP_SIZE_VALID_LEN(v) ((v) & GENMASK(12, 0))178 179#define SUN6I_CSI_CH_FRM_CLK_CNT_REG 0x90180#define SUN6I_CSI_CH_ACC_ITNL_CLK_CNT_REG 0x94181#define SUN6I_CSI_CH_FIFO_STAT_REG 0x98182#define SUN6I_CSI_CH_PCLK_STAT_REG 0x9c183 184#endif185