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1// SPDX-License-Identifier: GPL-2.02/*3 * Allwinner sun8i deinterlacer with scaler driver4 *5 * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>6 *7 * Based on vim2m driver.8 */9 10#include <linux/clk.h>11#include <linux/interrupt.h>12#include <linux/io.h>13#include <linux/iopoll.h>14#include <linux/mod_devicetable.h>15#include <linux/module.h>16#include <linux/platform_device.h>17#include <linux/pm_runtime.h>18#include <linux/reset.h>19 20#include <media/v4l2-device.h>21#include <media/v4l2-ioctl.h>22#include <media/v4l2-mem2mem.h>23 24#include "sun8i-di.h"25 26#define FLAG_SIZE (DEINTERLACE_MAX_WIDTH * DEINTERLACE_MAX_HEIGHT / 4)27 28static u32 deinterlace_formats[] = {29 V4L2_PIX_FMT_NV12,30 V4L2_PIX_FMT_NV21,31};32 33static inline u32 deinterlace_read(struct deinterlace_dev *dev, u32 reg)34{35 return readl(dev->base + reg);36}37 38static inline void deinterlace_write(struct deinterlace_dev *dev,39 u32 reg, u32 value)40{41 writel(value, dev->base + reg);42}43 44static inline void deinterlace_set_bits(struct deinterlace_dev *dev,45 u32 reg, u32 bits)46{47 writel(readl(dev->base + reg) | bits, dev->base + reg);48}49 50static inline void deinterlace_clr_set_bits(struct deinterlace_dev *dev,51 u32 reg, u32 clr, u32 set)52{53 u32 val = readl(dev->base + reg);54 55 val &= ~clr;56 val |= set;57 58 writel(val, dev->base + reg);59}60 61static void deinterlace_device_run(void *priv)62{63 struct deinterlace_ctx *ctx = priv;64 struct deinterlace_dev *dev = ctx->dev;65 u32 size, stride, width, height, val;66 struct vb2_v4l2_buffer *src, *dst;67 unsigned int hstep, vstep;68 dma_addr_t addr;69 int i;70 71 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);72 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);73 74 v4l2_m2m_buf_copy_metadata(src, dst, true);75 76 deinterlace_write(dev, DEINTERLACE_MOD_ENABLE,77 DEINTERLACE_MOD_ENABLE_EN);78 79 if (ctx->field) {80 deinterlace_write(dev, DEINTERLACE_TILE_FLAG0,81 ctx->flag1_buf_dma);82 deinterlace_write(dev, DEINTERLACE_TILE_FLAG1,83 ctx->flag2_buf_dma);84 } else {85 deinterlace_write(dev, DEINTERLACE_TILE_FLAG0,86 ctx->flag2_buf_dma);87 deinterlace_write(dev, DEINTERLACE_TILE_FLAG1,88 ctx->flag1_buf_dma);89 }90 deinterlace_write(dev, DEINTERLACE_FLAG_LINE_STRIDE, 0x200);91 92 width = ctx->src_fmt.width;93 height = ctx->src_fmt.height;94 stride = ctx->src_fmt.bytesperline;95 size = stride * height;96 97 addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0);98 deinterlace_write(dev, DEINTERLACE_BUF_ADDR0, addr);99 deinterlace_write(dev, DEINTERLACE_BUF_ADDR1, addr + size);100 deinterlace_write(dev, DEINTERLACE_BUF_ADDR2, 0);101 102 deinterlace_write(dev, DEINTERLACE_LINE_STRIDE0, stride);103 deinterlace_write(dev, DEINTERLACE_LINE_STRIDE1, stride);104 105 deinterlace_write(dev, DEINTERLACE_CH0_IN_SIZE,106 DEINTERLACE_SIZE(width, height));107 deinterlace_write(dev, DEINTERLACE_CH1_IN_SIZE,108 DEINTERLACE_SIZE(width / 2, height / 2));109 110 val = DEINTERLACE_IN_FMT_FMT(DEINTERLACE_IN_FMT_YUV420) |111 DEINTERLACE_IN_FMT_MOD(DEINTERLACE_MODE_UV_COMBINED);112 switch (ctx->src_fmt.pixelformat) {113 case V4L2_PIX_FMT_NV12:114 val |= DEINTERLACE_IN_FMT_PS(DEINTERLACE_PS_UVUV);115 break;116 case V4L2_PIX_FMT_NV21:117 val |= DEINTERLACE_IN_FMT_PS(DEINTERLACE_PS_VUVU);118 break;119 }120 deinterlace_write(dev, DEINTERLACE_IN_FMT, val);121 122 if (ctx->prev)123 addr = vb2_dma_contig_plane_dma_addr(&ctx->prev->vb2_buf, 0);124 125 deinterlace_write(dev, DEINTERLACE_PRELUMA, addr);126 deinterlace_write(dev, DEINTERLACE_PRECHROMA, addr + size);127 128 val = DEINTERLACE_OUT_FMT_FMT(DEINTERLACE_OUT_FMT_YUV420SP);129 switch (ctx->src_fmt.pixelformat) {130 case V4L2_PIX_FMT_NV12:131 val |= DEINTERLACE_OUT_FMT_PS(DEINTERLACE_PS_UVUV);132 break;133 case V4L2_PIX_FMT_NV21:134 val |= DEINTERLACE_OUT_FMT_PS(DEINTERLACE_PS_VUVU);135 break;136 }137 deinterlace_write(dev, DEINTERLACE_OUT_FMT, val);138 139 width = ctx->dst_fmt.width;140 height = ctx->dst_fmt.height;141 stride = ctx->dst_fmt.bytesperline;142 size = stride * height;143 144 deinterlace_write(dev, DEINTERLACE_CH0_OUT_SIZE,145 DEINTERLACE_SIZE(width, height));146 deinterlace_write(dev, DEINTERLACE_CH1_OUT_SIZE,147 DEINTERLACE_SIZE(width / 2, height / 2));148 149 deinterlace_write(dev, DEINTERLACE_WB_LINE_STRIDE0, stride);150 deinterlace_write(dev, DEINTERLACE_WB_LINE_STRIDE1, stride);151 152 addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0);153 deinterlace_write(dev, DEINTERLACE_WB_ADDR0, addr);154 deinterlace_write(dev, DEINTERLACE_WB_ADDR1, addr + size);155 deinterlace_write(dev, DEINTERLACE_WB_ADDR2, 0);156 157 hstep = (ctx->src_fmt.width << 16) / ctx->dst_fmt.width;158 vstep = (ctx->src_fmt.height << 16) / ctx->dst_fmt.height;159 deinterlace_write(dev, DEINTERLACE_CH0_HORZ_FACT, hstep);160 deinterlace_write(dev, DEINTERLACE_CH0_VERT_FACT, vstep);161 deinterlace_write(dev, DEINTERLACE_CH1_HORZ_FACT, hstep);162 deinterlace_write(dev, DEINTERLACE_CH1_VERT_FACT, vstep);163 164 /* neutral filter coefficients */165 deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL,166 DEINTERLACE_FRM_CTRL_COEF_ACCESS);167 readl_poll_timeout(dev->base + DEINTERLACE_STATUS, val,168 val & DEINTERLACE_STATUS_COEF_STATUS, 2, 40);169 170 for (i = 0; i < 32; i++) {171 deinterlace_write(dev, DEINTERLACE_CH0_HORZ_COEF0 + i * 4,172 DEINTERLACE_IDENTITY_COEF);173 deinterlace_write(dev, DEINTERLACE_CH0_VERT_COEF + i * 4,174 DEINTERLACE_IDENTITY_COEF);175 deinterlace_write(dev, DEINTERLACE_CH1_HORZ_COEF0 + i * 4,176 DEINTERLACE_IDENTITY_COEF);177 deinterlace_write(dev, DEINTERLACE_CH1_VERT_COEF + i * 4,178 DEINTERLACE_IDENTITY_COEF);179 }180 181 deinterlace_clr_set_bits(dev, DEINTERLACE_FRM_CTRL,182 DEINTERLACE_FRM_CTRL_COEF_ACCESS, 0);183 184 deinterlace_clr_set_bits(dev, DEINTERLACE_FIELD_CTRL,185 DEINTERLACE_FIELD_CTRL_FIELD_CNT_MSK,186 DEINTERLACE_FIELD_CTRL_FIELD_CNT(ctx->field));187 188 deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL,189 DEINTERLACE_FRM_CTRL_START);190 191 deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL,192 DEINTERLACE_FRM_CTRL_REG_READY);193 194 deinterlace_set_bits(dev, DEINTERLACE_INT_ENABLE,195 DEINTERLACE_INT_ENABLE_WB_EN);196 197 deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL,198 DEINTERLACE_FRM_CTRL_WB_EN);199}200 201static int deinterlace_job_ready(void *priv)202{203 struct deinterlace_ctx *ctx = priv;204 205 return v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1 &&206 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2;207}208 209static void deinterlace_job_abort(void *priv)210{211 struct deinterlace_ctx *ctx = priv;212 213 /* Will cancel the transaction in the next interrupt handler */214 ctx->aborting = 1;215}216 217static irqreturn_t deinterlace_irq(int irq, void *data)218{219 struct deinterlace_dev *dev = data;220 struct vb2_v4l2_buffer *src, *dst;221 enum vb2_buffer_state state;222 struct deinterlace_ctx *ctx;223 unsigned int val;224 225 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);226 if (!ctx) {227 v4l2_err(&dev->v4l2_dev,228 "Instance released before the end of transaction\n");229 return IRQ_NONE;230 }231 232 val = deinterlace_read(dev, DEINTERLACE_INT_STATUS);233 if (!(val & DEINTERLACE_INT_STATUS_WRITEBACK))234 return IRQ_NONE;235 236 deinterlace_write(dev, DEINTERLACE_INT_ENABLE, 0);237 deinterlace_set_bits(dev, DEINTERLACE_INT_STATUS,238 DEINTERLACE_INT_STATUS_WRITEBACK);239 deinterlace_write(dev, DEINTERLACE_MOD_ENABLE, 0);240 deinterlace_clr_set_bits(dev, DEINTERLACE_FRM_CTRL,241 DEINTERLACE_FRM_CTRL_START, 0);242 243 val = deinterlace_read(dev, DEINTERLACE_STATUS);244 if (val & DEINTERLACE_STATUS_WB_ERROR)245 state = VB2_BUF_STATE_ERROR;246 else247 state = VB2_BUF_STATE_DONE;248 249 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);250 v4l2_m2m_buf_done(dst, state);251 252 if (ctx->field != ctx->first_field || ctx->aborting) {253 ctx->field = ctx->first_field;254 255 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);256 if (ctx->prev)257 v4l2_m2m_buf_done(ctx->prev, state);258 ctx->prev = src;259 260 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);261 } else {262 ctx->field = !ctx->first_field;263 deinterlace_device_run(ctx);264 }265 266 return IRQ_HANDLED;267}268 269static void deinterlace_init(struct deinterlace_dev *dev)270{271 u32 val;272 273 deinterlace_write(dev, DEINTERLACE_BYPASS,274 DEINTERLACE_BYPASS_CSC);275 deinterlace_write(dev, DEINTERLACE_WB_LINE_STRIDE_CTRL,276 DEINTERLACE_WB_LINE_STRIDE_CTRL_EN);277 deinterlace_set_bits(dev, DEINTERLACE_FRM_CTRL,278 DEINTERLACE_FRM_CTRL_OUT_CTRL);279 deinterlace_write(dev, DEINTERLACE_AGTH_SEL,280 DEINTERLACE_AGTH_SEL_LINEBUF);281 282 val = DEINTERLACE_CTRL_EN |283 DEINTERLACE_CTRL_MODE_MIXED |284 DEINTERLACE_CTRL_DIAG_INTP_EN |285 DEINTERLACE_CTRL_TEMP_DIFF_EN;286 deinterlace_write(dev, DEINTERLACE_CTRL, val);287 288 deinterlace_clr_set_bits(dev, DEINTERLACE_LUMA_TH,289 DEINTERLACE_LUMA_TH_MIN_LUMA_MSK,290 DEINTERLACE_LUMA_TH_MIN_LUMA(4));291 292 deinterlace_clr_set_bits(dev, DEINTERLACE_SPAT_COMP,293 DEINTERLACE_SPAT_COMP_TH2_MSK,294 DEINTERLACE_SPAT_COMP_TH2(5));295 296 deinterlace_clr_set_bits(dev, DEINTERLACE_TEMP_DIFF,297 DEINTERLACE_TEMP_DIFF_AMBIGUITY_TH_MSK,298 DEINTERLACE_TEMP_DIFF_AMBIGUITY_TH(5));299 300 val = DEINTERLACE_DIAG_INTP_TH0(60) |301 DEINTERLACE_DIAG_INTP_TH1(0) |302 DEINTERLACE_DIAG_INTP_TH3(30);303 deinterlace_write(dev, DEINTERLACE_DIAG_INTP, val);304 305 deinterlace_clr_set_bits(dev, DEINTERLACE_CHROMA_DIFF,306 DEINTERLACE_CHROMA_DIFF_TH_MSK,307 DEINTERLACE_CHROMA_DIFF_TH(31));308}309 310static inline struct deinterlace_ctx *deinterlace_file2ctx(struct file *file)311{312 return container_of(file->private_data, struct deinterlace_ctx, fh);313}314 315static bool deinterlace_check_format(u32 pixelformat)316{317 unsigned int i;318 319 for (i = 0; i < ARRAY_SIZE(deinterlace_formats); i++)320 if (deinterlace_formats[i] == pixelformat)321 return true;322 323 return false;324}325 326static void deinterlace_prepare_format(struct v4l2_pix_format *pix_fmt)327{328 unsigned int height = pix_fmt->height;329 unsigned int width = pix_fmt->width;330 unsigned int bytesperline;331 unsigned int sizeimage;332 333 width = clamp(width, DEINTERLACE_MIN_WIDTH,334 DEINTERLACE_MAX_WIDTH);335 height = clamp(height, DEINTERLACE_MIN_HEIGHT,336 DEINTERLACE_MAX_HEIGHT);337 338 bytesperline = ALIGN(width, 2);339 /* luma */340 sizeimage = bytesperline * height;341 /* chroma */342 sizeimage += bytesperline * height / 2;343 344 pix_fmt->width = width;345 pix_fmt->height = height;346 pix_fmt->bytesperline = bytesperline;347 pix_fmt->sizeimage = sizeimage;348}349 350static int deinterlace_querycap(struct file *file, void *priv,351 struct v4l2_capability *cap)352{353 strscpy(cap->driver, DEINTERLACE_NAME, sizeof(cap->driver));354 strscpy(cap->card, DEINTERLACE_NAME, sizeof(cap->card));355 snprintf(cap->bus_info, sizeof(cap->bus_info),356 "platform:%s", DEINTERLACE_NAME);357 358 return 0;359}360 361static int deinterlace_enum_fmt(struct file *file, void *priv,362 struct v4l2_fmtdesc *f)363{364 if (f->index < ARRAY_SIZE(deinterlace_formats)) {365 f->pixelformat = deinterlace_formats[f->index];366 367 return 0;368 }369 370 return -EINVAL;371}372 373static int deinterlace_enum_framesizes(struct file *file, void *priv,374 struct v4l2_frmsizeenum *fsize)375{376 if (fsize->index != 0)377 return -EINVAL;378 379 if (!deinterlace_check_format(fsize->pixel_format))380 return -EINVAL;381 382 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;383 fsize->stepwise.min_width = DEINTERLACE_MIN_WIDTH;384 fsize->stepwise.min_height = DEINTERLACE_MIN_HEIGHT;385 fsize->stepwise.max_width = DEINTERLACE_MAX_WIDTH;386 fsize->stepwise.max_height = DEINTERLACE_MAX_HEIGHT;387 fsize->stepwise.step_width = 2;388 fsize->stepwise.step_height = 1;389 390 return 0;391}392 393static int deinterlace_g_fmt_vid_cap(struct file *file, void *priv,394 struct v4l2_format *f)395{396 struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);397 398 f->fmt.pix = ctx->dst_fmt;399 400 return 0;401}402 403static int deinterlace_g_fmt_vid_out(struct file *file, void *priv,404 struct v4l2_format *f)405{406 struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);407 408 f->fmt.pix = ctx->src_fmt;409 410 return 0;411}412 413static int deinterlace_try_fmt_vid_cap(struct file *file, void *priv,414 struct v4l2_format *f)415{416 if (!deinterlace_check_format(f->fmt.pix.pixelformat))417 f->fmt.pix.pixelformat = deinterlace_formats[0];418 419 if (f->fmt.pix.field != V4L2_FIELD_NONE)420 f->fmt.pix.field = V4L2_FIELD_NONE;421 422 deinterlace_prepare_format(&f->fmt.pix);423 424 return 0;425}426 427static int deinterlace_try_fmt_vid_out(struct file *file, void *priv,428 struct v4l2_format *f)429{430 if (!deinterlace_check_format(f->fmt.pix.pixelformat))431 f->fmt.pix.pixelformat = deinterlace_formats[0];432 433 if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB &&434 f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT &&435 f->fmt.pix.field != V4L2_FIELD_INTERLACED)436 f->fmt.pix.field = V4L2_FIELD_INTERLACED;437 438 deinterlace_prepare_format(&f->fmt.pix);439 440 return 0;441}442 443static int deinterlace_s_fmt_vid_cap(struct file *file, void *priv,444 struct v4l2_format *f)445{446 struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);447 struct vb2_queue *vq;448 int ret;449 450 ret = deinterlace_try_fmt_vid_cap(file, priv, f);451 if (ret)452 return ret;453 454 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);455 if (vb2_is_busy(vq))456 return -EBUSY;457 458 ctx->dst_fmt = f->fmt.pix;459 460 return 0;461}462 463static int deinterlace_s_fmt_vid_out(struct file *file, void *priv,464 struct v4l2_format *f)465{466 struct deinterlace_ctx *ctx = deinterlace_file2ctx(file);467 struct vb2_queue *vq;468 int ret;469 470 ret = deinterlace_try_fmt_vid_out(file, priv, f);471 if (ret)472 return ret;473 474 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);475 if (vb2_is_busy(vq))476 return -EBUSY;477 478 ctx->src_fmt = f->fmt.pix;479 480 /* Propagate colorspace information to capture. */481 ctx->dst_fmt.colorspace = f->fmt.pix.colorspace;482 ctx->dst_fmt.xfer_func = f->fmt.pix.xfer_func;483 ctx->dst_fmt.ycbcr_enc = f->fmt.pix.ycbcr_enc;484 ctx->dst_fmt.quantization = f->fmt.pix.quantization;485 486 return 0;487}488 489static const struct v4l2_ioctl_ops deinterlace_ioctl_ops = {490 .vidioc_querycap = deinterlace_querycap,491 492 .vidioc_enum_framesizes = deinterlace_enum_framesizes,493 494 .vidioc_enum_fmt_vid_cap = deinterlace_enum_fmt,495 .vidioc_g_fmt_vid_cap = deinterlace_g_fmt_vid_cap,496 .vidioc_try_fmt_vid_cap = deinterlace_try_fmt_vid_cap,497 .vidioc_s_fmt_vid_cap = deinterlace_s_fmt_vid_cap,498 499 .vidioc_enum_fmt_vid_out = deinterlace_enum_fmt,500 .vidioc_g_fmt_vid_out = deinterlace_g_fmt_vid_out,501 .vidioc_try_fmt_vid_out = deinterlace_try_fmt_vid_out,502 .vidioc_s_fmt_vid_out = deinterlace_s_fmt_vid_out,503 504 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,505 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,506 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,507 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,508 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,509 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,510 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,511 512 .vidioc_streamon = v4l2_m2m_ioctl_streamon,513 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,514};515 516static int deinterlace_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,517 unsigned int *nplanes, unsigned int sizes[],518 struct device *alloc_devs[])519{520 struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);521 struct v4l2_pix_format *pix_fmt;522 523 if (V4L2_TYPE_IS_OUTPUT(vq->type))524 pix_fmt = &ctx->src_fmt;525 else526 pix_fmt = &ctx->dst_fmt;527 528 if (*nplanes) {529 if (sizes[0] < pix_fmt->sizeimage)530 return -EINVAL;531 } else {532 sizes[0] = pix_fmt->sizeimage;533 *nplanes = 1;534 }535 536 return 0;537}538 539static int deinterlace_buf_prepare(struct vb2_buffer *vb)540{541 struct vb2_queue *vq = vb->vb2_queue;542 struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);543 struct v4l2_pix_format *pix_fmt;544 545 if (V4L2_TYPE_IS_OUTPUT(vq->type))546 pix_fmt = &ctx->src_fmt;547 else548 pix_fmt = &ctx->dst_fmt;549 550 if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage)551 return -EINVAL;552 553 vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage);554 555 return 0;556}557 558static void deinterlace_buf_queue(struct vb2_buffer *vb)559{560 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);561 struct deinterlace_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);562 563 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);564}565 566static void deinterlace_queue_cleanup(struct vb2_queue *vq, u32 state)567{568 struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);569 struct vb2_v4l2_buffer *vbuf;570 571 do {572 if (V4L2_TYPE_IS_OUTPUT(vq->type))573 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);574 else575 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);576 577 if (vbuf)578 v4l2_m2m_buf_done(vbuf, state);579 } while (vbuf);580 581 if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev)582 v4l2_m2m_buf_done(ctx->prev, state);583}584 585static int deinterlace_start_streaming(struct vb2_queue *vq, unsigned int count)586{587 struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);588 struct device *dev = ctx->dev->dev;589 int ret;590 591 if (V4L2_TYPE_IS_OUTPUT(vq->type)) {592 ret = pm_runtime_resume_and_get(dev);593 if (ret < 0) {594 dev_err(dev, "Failed to enable module\n");595 596 goto err_runtime_get;597 }598 599 ctx->first_field =600 ctx->src_fmt.field == V4L2_FIELD_INTERLACED_BT;601 ctx->field = ctx->first_field;602 603 ctx->prev = NULL;604 ctx->aborting = 0;605 606 ctx->flag1_buf = dma_alloc_coherent(dev, FLAG_SIZE,607 &ctx->flag1_buf_dma,608 GFP_KERNEL);609 if (!ctx->flag1_buf) {610 ret = -ENOMEM;611 612 goto err_no_mem1;613 }614 615 ctx->flag2_buf = dma_alloc_coherent(dev, FLAG_SIZE,616 &ctx->flag2_buf_dma,617 GFP_KERNEL);618 if (!ctx->flag2_buf) {619 ret = -ENOMEM;620 621 goto err_no_mem2;622 }623 }624 625 return 0;626 627err_no_mem2:628 dma_free_coherent(dev, FLAG_SIZE, ctx->flag1_buf,629 ctx->flag1_buf_dma);630err_no_mem1:631 pm_runtime_put(dev);632err_runtime_get:633 deinterlace_queue_cleanup(vq, VB2_BUF_STATE_QUEUED);634 635 return ret;636}637 638static void deinterlace_stop_streaming(struct vb2_queue *vq)639{640 struct deinterlace_ctx *ctx = vb2_get_drv_priv(vq);641 642 if (V4L2_TYPE_IS_OUTPUT(vq->type)) {643 struct device *dev = ctx->dev->dev;644 645 dma_free_coherent(dev, FLAG_SIZE, ctx->flag1_buf,646 ctx->flag1_buf_dma);647 dma_free_coherent(dev, FLAG_SIZE, ctx->flag2_buf,648 ctx->flag2_buf_dma);649 650 pm_runtime_put(dev);651 }652 653 deinterlace_queue_cleanup(vq, VB2_BUF_STATE_ERROR);654}655 656static const struct vb2_ops deinterlace_qops = {657 .queue_setup = deinterlace_queue_setup,658 .buf_prepare = deinterlace_buf_prepare,659 .buf_queue = deinterlace_buf_queue,660 .start_streaming = deinterlace_start_streaming,661 .stop_streaming = deinterlace_stop_streaming,662 .wait_prepare = vb2_ops_wait_prepare,663 .wait_finish = vb2_ops_wait_finish,664};665 666static int deinterlace_queue_init(void *priv, struct vb2_queue *src_vq,667 struct vb2_queue *dst_vq)668{669 struct deinterlace_ctx *ctx = priv;670 int ret;671 672 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;673 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;674 src_vq->drv_priv = ctx;675 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);676 src_vq->min_queued_buffers = 1;677 src_vq->ops = &deinterlace_qops;678 src_vq->mem_ops = &vb2_dma_contig_memops;679 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;680 src_vq->lock = &ctx->dev->dev_mutex;681 src_vq->dev = ctx->dev->dev;682 683 ret = vb2_queue_init(src_vq);684 if (ret)685 return ret;686 687 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;688 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;689 dst_vq->drv_priv = ctx;690 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);691 dst_vq->min_queued_buffers = 2;692 dst_vq->ops = &deinterlace_qops;693 dst_vq->mem_ops = &vb2_dma_contig_memops;694 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;695 dst_vq->lock = &ctx->dev->dev_mutex;696 dst_vq->dev = ctx->dev->dev;697 698 ret = vb2_queue_init(dst_vq);699 if (ret)700 return ret;701 702 return 0;703}704 705static int deinterlace_open(struct file *file)706{707 struct deinterlace_dev *dev = video_drvdata(file);708 struct deinterlace_ctx *ctx = NULL;709 int ret;710 711 if (mutex_lock_interruptible(&dev->dev_mutex))712 return -ERESTARTSYS;713 714 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);715 if (!ctx) {716 mutex_unlock(&dev->dev_mutex);717 return -ENOMEM;718 }719 720 /* default output format */721 ctx->src_fmt.pixelformat = deinterlace_formats[0];722 ctx->src_fmt.field = V4L2_FIELD_INTERLACED;723 ctx->src_fmt.width = 640;724 ctx->src_fmt.height = 480;725 deinterlace_prepare_format(&ctx->src_fmt);726 727 /* default capture format */728 ctx->dst_fmt.pixelformat = deinterlace_formats[0];729 ctx->dst_fmt.field = V4L2_FIELD_NONE;730 ctx->dst_fmt.width = 640;731 ctx->dst_fmt.height = 480;732 deinterlace_prepare_format(&ctx->dst_fmt);733 734 v4l2_fh_init(&ctx->fh, video_devdata(file));735 file->private_data = &ctx->fh;736 ctx->dev = dev;737 738 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,739 &deinterlace_queue_init);740 if (IS_ERR(ctx->fh.m2m_ctx)) {741 ret = PTR_ERR(ctx->fh.m2m_ctx);742 goto err_free;743 }744 745 v4l2_fh_add(&ctx->fh);746 747 mutex_unlock(&dev->dev_mutex);748 749 return 0;750 751err_free:752 kfree(ctx);753 mutex_unlock(&dev->dev_mutex);754 755 return ret;756}757 758static int deinterlace_release(struct file *file)759{760 struct deinterlace_dev *dev = video_drvdata(file);761 struct deinterlace_ctx *ctx = container_of(file->private_data,762 struct deinterlace_ctx, fh);763 764 mutex_lock(&dev->dev_mutex);765 766 v4l2_fh_del(&ctx->fh);767 v4l2_fh_exit(&ctx->fh);768 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);769 770 kfree(ctx);771 772 mutex_unlock(&dev->dev_mutex);773 774 return 0;775}776 777static const struct v4l2_file_operations deinterlace_fops = {778 .owner = THIS_MODULE,779 .open = deinterlace_open,780 .release = deinterlace_release,781 .poll = v4l2_m2m_fop_poll,782 .unlocked_ioctl = video_ioctl2,783 .mmap = v4l2_m2m_fop_mmap,784};785 786static const struct video_device deinterlace_video_device = {787 .name = DEINTERLACE_NAME,788 .vfl_dir = VFL_DIR_M2M,789 .fops = &deinterlace_fops,790 .ioctl_ops = &deinterlace_ioctl_ops,791 .minor = -1,792 .release = video_device_release_empty,793 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,794};795 796static const struct v4l2_m2m_ops deinterlace_m2m_ops = {797 .device_run = deinterlace_device_run,798 .job_ready = deinterlace_job_ready,799 .job_abort = deinterlace_job_abort,800};801 802static int deinterlace_probe(struct platform_device *pdev)803{804 struct deinterlace_dev *dev;805 struct video_device *vfd;806 int irq, ret;807 808 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);809 if (!dev)810 return -ENOMEM;811 812 dev->vfd = deinterlace_video_device;813 dev->dev = &pdev->dev;814 815 irq = platform_get_irq(pdev, 0);816 if (irq <= 0)817 return irq;818 819 ret = devm_request_irq(dev->dev, irq, deinterlace_irq,820 0, dev_name(dev->dev), dev);821 if (ret) {822 dev_err(dev->dev, "Failed to request IRQ\n");823 824 return ret;825 }826 827 dev->base = devm_platform_ioremap_resource(pdev, 0);828 if (IS_ERR(dev->base))829 return PTR_ERR(dev->base);830 831 dev->bus_clk = devm_clk_get(dev->dev, "bus");832 if (IS_ERR(dev->bus_clk)) {833 dev_err(dev->dev, "Failed to get bus clock\n");834 835 return PTR_ERR(dev->bus_clk);836 }837 838 dev->mod_clk = devm_clk_get(dev->dev, "mod");839 if (IS_ERR(dev->mod_clk)) {840 dev_err(dev->dev, "Failed to get mod clock\n");841 842 return PTR_ERR(dev->mod_clk);843 }844 845 dev->ram_clk = devm_clk_get(dev->dev, "ram");846 if (IS_ERR(dev->ram_clk)) {847 dev_err(dev->dev, "Failed to get ram clock\n");848 849 return PTR_ERR(dev->ram_clk);850 }851 852 dev->rstc = devm_reset_control_get(dev->dev, NULL);853 if (IS_ERR(dev->rstc)) {854 dev_err(dev->dev, "Failed to get reset control\n");855 856 return PTR_ERR(dev->rstc);857 }858 859 mutex_init(&dev->dev_mutex);860 861 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);862 if (ret) {863 dev_err(dev->dev, "Failed to register V4L2 device\n");864 865 return ret;866 }867 868 vfd = &dev->vfd;869 vfd->lock = &dev->dev_mutex;870 vfd->v4l2_dev = &dev->v4l2_dev;871 872 snprintf(vfd->name, sizeof(vfd->name), "%s",873 deinterlace_video_device.name);874 video_set_drvdata(vfd, dev);875 876 ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);877 if (ret) {878 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");879 880 goto err_v4l2;881 }882 883 v4l2_info(&dev->v4l2_dev,884 "Device registered as /dev/video%d\n", vfd->num);885 886 dev->m2m_dev = v4l2_m2m_init(&deinterlace_m2m_ops);887 if (IS_ERR(dev->m2m_dev)) {888 v4l2_err(&dev->v4l2_dev,889 "Failed to initialize V4L2 M2M device\n");890 ret = PTR_ERR(dev->m2m_dev);891 892 goto err_video;893 }894 895 platform_set_drvdata(pdev, dev);896 897 pm_runtime_enable(dev->dev);898 899 return 0;900 901err_video:902 video_unregister_device(&dev->vfd);903err_v4l2:904 v4l2_device_unregister(&dev->v4l2_dev);905 906 return ret;907}908 909static void deinterlace_remove(struct platform_device *pdev)910{911 struct deinterlace_dev *dev = platform_get_drvdata(pdev);912 913 v4l2_m2m_release(dev->m2m_dev);914 video_unregister_device(&dev->vfd);915 v4l2_device_unregister(&dev->v4l2_dev);916 917 pm_runtime_force_suspend(&pdev->dev);918}919 920static int deinterlace_runtime_resume(struct device *device)921{922 struct deinterlace_dev *dev = dev_get_drvdata(device);923 int ret;924 925 ret = clk_set_rate_exclusive(dev->mod_clk, 300000000);926 if (ret) {927 dev_err(dev->dev, "Failed to set exclusive mod clock rate\n");928 929 return ret;930 }931 932 ret = reset_control_deassert(dev->rstc);933 if (ret) {934 dev_err(dev->dev, "Failed to apply reset\n");935 936 goto err_exclusive_rate;937 }938 939 ret = clk_prepare_enable(dev->bus_clk);940 if (ret) {941 dev_err(dev->dev, "Failed to enable bus clock\n");942 943 goto err_rst;944 }945 946 ret = clk_prepare_enable(dev->mod_clk);947 if (ret) {948 dev_err(dev->dev, "Failed to enable mod clock\n");949 950 goto err_bus_clk;951 }952 953 ret = clk_prepare_enable(dev->ram_clk);954 if (ret) {955 dev_err(dev->dev, "Failed to enable ram clock\n");956 957 goto err_mod_clk;958 }959 960 deinterlace_init(dev);961 962 return 0;963 964err_mod_clk:965 clk_disable_unprepare(dev->mod_clk);966err_bus_clk:967 clk_disable_unprepare(dev->bus_clk);968err_rst:969 reset_control_assert(dev->rstc);970err_exclusive_rate:971 clk_rate_exclusive_put(dev->mod_clk);972 973 return ret;974}975 976static int deinterlace_runtime_suspend(struct device *device)977{978 struct deinterlace_dev *dev = dev_get_drvdata(device);979 980 clk_disable_unprepare(dev->ram_clk);981 clk_disable_unprepare(dev->mod_clk);982 clk_disable_unprepare(dev->bus_clk);983 984 reset_control_assert(dev->rstc);985 986 clk_rate_exclusive_put(dev->mod_clk);987 988 return 0;989}990 991static const struct of_device_id deinterlace_dt_match[] = {992 { .compatible = "allwinner,sun8i-h3-deinterlace" },993 { /* sentinel */ }994};995MODULE_DEVICE_TABLE(of, deinterlace_dt_match);996 997static const struct dev_pm_ops deinterlace_pm_ops = {998 .runtime_resume = deinterlace_runtime_resume,999 .runtime_suspend = deinterlace_runtime_suspend,1000};1001 1002static struct platform_driver deinterlace_driver = {1003 .probe = deinterlace_probe,1004 .remove_new = deinterlace_remove,1005 .driver = {1006 .name = DEINTERLACE_NAME,1007 .of_match_table = deinterlace_dt_match,1008 .pm = &deinterlace_pm_ops,1009 },1010};1011module_platform_driver(deinterlace_driver);1012 1013MODULE_LICENSE("GPL v2");1014MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");1015MODULE_DESCRIPTION("Allwinner Deinterlace driver");1016