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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * TI AM437x Image Sensor Interface Registers4 *5 * Copyright (C) 2013 - 2014 Texas Instruments, Inc.6 *7 * Benoit Parrot <bparrot@ti.com>8 * Lad, Prabhakar <prabhakar.csengg@gmail.com>9 */10 11#ifndef AM437X_VPFE_REGS_H12#define AM437X_VPFE_REGS_H13 14/* VPFE module register offset */15#define VPFE_REVISION 0x016#define VPFE_PCR 0x417#define VPFE_SYNMODE 0x818#define VPFE_HD_VD_WID 0xc19#define VPFE_PIX_LINES 0x1020#define VPFE_HORZ_INFO 0x1421#define VPFE_VERT_START 0x1822#define VPFE_VERT_LINES 0x1c23#define VPFE_CULLING 0x2024#define VPFE_HSIZE_OFF 0x2425#define VPFE_SDOFST 0x2826#define VPFE_SDR_ADDR 0x2c27#define VPFE_CLAMP 0x3028#define VPFE_DCSUB 0x3429#define VPFE_COLPTN 0x3830#define VPFE_BLKCMP 0x3c31#define VPFE_VDINT 0x4832#define VPFE_ALAW 0x4c33#define VPFE_REC656IF 0x5034#define VPFE_CCDCFG 0x5435#define VPFE_DMA_CNTL 0x9836#define VPFE_SYSCONFIG 0x10437#define VPFE_CONFIG 0x10838#define VPFE_IRQ_EOI 0x11039#define VPFE_IRQ_STS_RAW 0x11440#define VPFE_IRQ_STS 0x11841#define VPFE_IRQ_EN_SET 0x11c42#define VPFE_IRQ_EN_CLR 0x12043#define VPFE_REG_END 0x12444 45/* Define bit fields within selected registers */46#define VPFE_FID_POL_MASK 147#define VPFE_FID_POL_SHIFT 448#define VPFE_HD_POL_MASK 149#define VPFE_HD_POL_SHIFT 350#define VPFE_VD_POL_MASK 151#define VPFE_VD_POL_SHIFT 252#define VPFE_HSIZE_OFF_MASK 0xffffffe053#define VPFE_32BYTE_ALIGN_VAL 3154#define VPFE_FRM_FMT_MASK 0x155#define VPFE_FRM_FMT_SHIFT 756#define VPFE_DATA_SZ_MASK 757#define VPFE_DATA_SZ_SHIFT 858#define VPFE_PIX_FMT_MASK 359#define VPFE_PIX_FMT_SHIFT 1260#define VPFE_VP2SDR_DISABLE 0xfffbffff61#define VPFE_WEN_ENABLE BIT(17)62#define VPFE_SDR2RSZ_DISABLE 0xfff7ffff63#define VPFE_VDHDEN_ENABLE BIT(16)64#define VPFE_LPF_ENABLE BIT(14)65#define VPFE_ALAW_ENABLE BIT(3)66#define VPFE_ALAW_GAMMA_WD_MASK 767#define VPFE_BLK_CLAMP_ENABLE BIT(31)68#define VPFE_BLK_SGAIN_MASK 0x1f69#define VPFE_BLK_ST_PXL_MASK 0x7fff70#define VPFE_BLK_ST_PXL_SHIFT 1071#define VPFE_BLK_SAMPLE_LN_MASK 772#define VPFE_BLK_SAMPLE_LN_SHIFT 2873#define VPFE_BLK_SAMPLE_LINE_MASK 774#define VPFE_BLK_SAMPLE_LINE_SHIFT 2575#define VPFE_BLK_DC_SUB_MASK 0x03fff76#define VPFE_BLK_COMP_MASK 0xff77#define VPFE_BLK_COMP_GB_COMP_SHIFT 878#define VPFE_BLK_COMP_GR_COMP_SHIFT 1679#define VPFE_BLK_COMP_R_COMP_SHIFT 2480#define VPFE_LATCH_ON_VSYNC_DISABLE BIT(15)81#define VPFE_DATA_PACK_ENABLE BIT(11)82#define VPFE_HORZ_INFO_SPH_SHIFT 1683#define VPFE_VERT_START_SLV0_SHIFT 1684#define VPFE_VDINT_VDINT0_SHIFT 1685#define VPFE_VDINT_VDINT1_MASK 0xffff86#define VPFE_PPC_RAW 187#define VPFE_DCSUB_DEFAULT_VAL 088#define VPFE_CLAMP_DEFAULT_VAL 089#define VPFE_COLPTN_VAL 0xbb11bb1190#define VPFE_TWO_BYTES_PER_PIXEL 291#define VPFE_INTERLACED_IMAGE_INVERT 0x4b6d92#define VPFE_INTERLACED_NO_IMAGE_INVERT 0x024993#define VPFE_PROGRESSIVE_IMAGE_INVERT 0x400094#define VPFE_PROGRESSIVE_NO_IMAGE_INVERT 095#define VPFE_INTERLACED_HEIGHT_SHIFT 196#define VPFE_SYN_MODE_INPMOD_SHIFT 1297#define VPFE_SYN_MODE_INPMOD_MASK 398#define VPFE_SYN_MODE_8BITS (7 << 8)99#define VPFE_SYN_MODE_10BITS (6 << 8)100#define VPFE_SYN_MODE_11BITS (5 << 8)101#define VPFE_SYN_MODE_12BITS (4 << 8)102#define VPFE_SYN_MODE_13BITS (3 << 8)103#define VPFE_SYN_MODE_14BITS (2 << 8)104#define VPFE_SYN_MODE_15BITS (1 << 8)105#define VPFE_SYN_MODE_16BITS (0 << 8)106#define VPFE_SYN_FLDMODE_MASK 1107#define VPFE_SYN_FLDMODE_SHIFT 7108#define VPFE_REC656IF_BT656_EN 3109#define VPFE_SYN_MODE_VD_POL_NEGATIVE BIT(2)110#define VPFE_CCDCFG_Y8POS_SHIFT 11111#define VPFE_CCDCFG_BW656_10BIT BIT(5)112#define VPFE_SDOFST_FIELD_INTERLEAVED 0x249113#define VPFE_NO_CULLING 0xffff00ff114#define VPFE_VDINT0 BIT(0)115#define VPFE_VDINT1 BIT(1)116#define VPFE_VDINT2 BIT(2)117#define VPFE_DMA_CNTL_OVERFLOW BIT(31)118 119#define VPFE_CONFIG_PCLK_INV_SHIFT 0120#define VPFE_CONFIG_PCLK_INV_MASK 1121#define VPFE_CONFIG_PCLK_INV_NOT_INV 0122#define VPFE_CONFIG_PCLK_INV_INV 1123#define VPFE_CONFIG_EN_SHIFT 1124#define VPFE_CONFIG_EN_MASK 2125#define VPFE_CONFIG_EN_DISABLE 0126#define VPFE_CONFIG_EN_ENABLE 1127#define VPFE_CONFIG_ST_SHIFT 2128#define VPFE_CONFIG_ST_MASK 4129#define VPFE_CONFIG_ST_OCP_ACTIVE 0130#define VPFE_CONFIG_ST_OCP_STANDBY 1131 132#endif /* AM437X_VPFE_REGS_H */133