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1/*2 * vpif - Video Port Interface driver3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)4 * that receiving video byte stream and two channels(2, 3) for video output.5 * The hardware supports SDTV, HDTV formats, raw data capture.6 * Currently, the driver supports NTSC and PAL standards.7 *8 * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/9 *10 * This program is free software; you can redistribute it and/or11 * modify it under the terms of the GNU General Public License as12 * published by the Free Software Foundation version 2.13 *14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any15 * kind, whether express or implied; without even the implied warranty16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the17 * GNU General Public License for more details.18 */19 20#include <linux/err.h>21#include <linux/init.h>22#include <linux/io.h>23#include <linux/irq.h>24#include <linux/kernel.h>25#include <linux/module.h>26#include <linux/of.h>27#include <linux/platform_device.h>28#include <linux/pm_runtime.h>29#include <linux/spinlock.h>30#include <linux/v4l2-dv-timings.h>31#include <linux/of_graph.h>32 33#include "vpif.h"34 35MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");36MODULE_LICENSE("GPL");37 38#define VPIF_DRIVER_NAME "vpif"39MODULE_ALIAS("platform:" VPIF_DRIVER_NAME);40 41#define VPIF_CH0_MAX_MODES 2242#define VPIF_CH1_MAX_MODES 243#define VPIF_CH2_MAX_MODES 1544#define VPIF_CH3_MAX_MODES 245 46struct vpif_data {47 struct platform_device *capture;48 struct platform_device *display;49};50 51DEFINE_SPINLOCK(vpif_lock);52EXPORT_SYMBOL_GPL(vpif_lock);53 54void __iomem *vpif_base;55EXPORT_SYMBOL_GPL(vpif_base);56 57/*58 * vpif_ch_params: video standard configuration parameters for vpif59 *60 * The table must include all presets from supported subdevices.61 */62const struct vpif_channel_config_params vpif_ch_params[] = {63 /* HDTV formats */64 {65 .name = "480p59_94",66 .width = 720,67 .height = 480,68 .frm_fmt = 1,69 .ycmux_mode = 0,70 .eav2sav = 138-8,71 .sav2eav = 720,72 .l1 = 1,73 .l3 = 43,74 .l5 = 523,75 .vsize = 525,76 .capture_format = 0,77 .vbi_supported = 0,78 .hd_sd = 1,79 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,80 },81 {82 .name = "576p50",83 .width = 720,84 .height = 576,85 .frm_fmt = 1,86 .ycmux_mode = 0,87 .eav2sav = 144-8,88 .sav2eav = 720,89 .l1 = 1,90 .l3 = 45,91 .l5 = 621,92 .vsize = 625,93 .capture_format = 0,94 .vbi_supported = 0,95 .hd_sd = 1,96 .dv_timings = V4L2_DV_BT_CEA_720X576P50,97 },98 {99 .name = "720p50",100 .width = 1280,101 .height = 720,102 .frm_fmt = 1,103 .ycmux_mode = 0,104 .eav2sav = 700-8,105 .sav2eav = 1280,106 .l1 = 1,107 .l3 = 26,108 .l5 = 746,109 .vsize = 750,110 .capture_format = 0,111 .vbi_supported = 0,112 .hd_sd = 1,113 .dv_timings = V4L2_DV_BT_CEA_1280X720P50,114 },115 {116 .name = "720p60",117 .width = 1280,118 .height = 720,119 .frm_fmt = 1,120 .ycmux_mode = 0,121 .eav2sav = 370 - 8,122 .sav2eav = 1280,123 .l1 = 1,124 .l3 = 26,125 .l5 = 746,126 .vsize = 750,127 .capture_format = 0,128 .vbi_supported = 0,129 .hd_sd = 1,130 .dv_timings = V4L2_DV_BT_CEA_1280X720P60,131 },132 {133 .name = "1080I50",134 .width = 1920,135 .height = 1080,136 .frm_fmt = 0,137 .ycmux_mode = 0,138 .eav2sav = 720 - 8,139 .sav2eav = 1920,140 .l1 = 1,141 .l3 = 21,142 .l5 = 561,143 .l7 = 563,144 .l9 = 584,145 .l11 = 1124,146 .vsize = 1125,147 .capture_format = 0,148 .vbi_supported = 0,149 .hd_sd = 1,150 .dv_timings = V4L2_DV_BT_CEA_1920X1080I50,151 },152 {153 .name = "1080I60",154 .width = 1920,155 .height = 1080,156 .frm_fmt = 0,157 .ycmux_mode = 0,158 .eav2sav = 280 - 8,159 .sav2eav = 1920,160 .l1 = 1,161 .l3 = 21,162 .l5 = 561,163 .l7 = 563,164 .l9 = 584,165 .l11 = 1124,166 .vsize = 1125,167 .capture_format = 0,168 .vbi_supported = 0,169 .hd_sd = 1,170 .dv_timings = V4L2_DV_BT_CEA_1920X1080I60,171 },172 {173 .name = "1080p60",174 .width = 1920,175 .height = 1080,176 .frm_fmt = 1,177 .ycmux_mode = 0,178 .eav2sav = 280 - 8,179 .sav2eav = 1920,180 .l1 = 1,181 .l3 = 42,182 .l5 = 1122,183 .vsize = 1125,184 .capture_format = 0,185 .vbi_supported = 0,186 .hd_sd = 1,187 .dv_timings = V4L2_DV_BT_CEA_1920X1080P60,188 },189 190 /* SDTV formats */191 {192 .name = "NTSC_M",193 .width = 720,194 .height = 480,195 .frm_fmt = 0,196 .ycmux_mode = 1,197 .eav2sav = 268,198 .sav2eav = 1440,199 .l1 = 1,200 .l3 = 23,201 .l5 = 263,202 .l7 = 266,203 .l9 = 286,204 .l11 = 525,205 .vsize = 525,206 .capture_format = 0,207 .vbi_supported = 1,208 .hd_sd = 0,209 .stdid = V4L2_STD_525_60,210 },211 {212 .name = "PAL_BDGHIK",213 .width = 720,214 .height = 576,215 .frm_fmt = 0,216 .ycmux_mode = 1,217 .eav2sav = 280,218 .sav2eav = 1440,219 .l1 = 1,220 .l3 = 23,221 .l5 = 311,222 .l7 = 313,223 .l9 = 336,224 .l11 = 624,225 .vsize = 625,226 .capture_format = 0,227 .vbi_supported = 1,228 .hd_sd = 0,229 .stdid = V4L2_STD_625_50,230 },231};232EXPORT_SYMBOL_GPL(vpif_ch_params);233 234const unsigned int vpif_ch_params_count = ARRAY_SIZE(vpif_ch_params);235EXPORT_SYMBOL_GPL(vpif_ch_params_count);236 237static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)238{239 if (val)240 vpif_set_bit(reg, bit);241 else242 vpif_clr_bit(reg, bit);243}244 245/* This structure is used to keep track of VPIF size register's offsets */246struct vpif_registers {247 u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;248 u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;249 u32 vanc1_size, width_mask, len_mask;250 u8 max_modes;251};252 253static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {254 /* Channel0 */255 {256 VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,257 VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,258 VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,259 VPIF_CH0_MAX_MODES,260 },261 /* Channel1 */262 {263 VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,264 VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,265 VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,266 VPIF_CH1_MAX_MODES,267 },268 /* Channel2 */269 {270 VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,271 VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,272 VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,273 VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,274 VPIF_CH2_MAX_MODES275 },276 /* Channel3 */277 {278 VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,279 VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,280 VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,281 VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,282 VPIF_CH3_MAX_MODES283 },284};285 286/* vpif_set_mode_info:287 * This function is used to set horizontal and vertical config parameters288 * As per the standard in the channel, configure the values of L1, L3,289 * L5, L7 L9, L11 in VPIF Register , also write width and height290 */291static void vpif_set_mode_info(const struct vpif_channel_config_params *config,292 u8 channel_id, u8 config_channel_id)293{294 u32 value;295 296 value = (config->eav2sav & vpifregs[config_channel_id].width_mask);297 value <<= VPIF_CH_LEN_SHIFT;298 value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);299 regw(value, vpifregs[channel_id].h_cfg);300 301 value = (config->l1 & vpifregs[config_channel_id].len_mask);302 value <<= VPIF_CH_LEN_SHIFT;303 value |= (config->l3 & vpifregs[config_channel_id].len_mask);304 regw(value, vpifregs[channel_id].v_cfg_00);305 306 value = (config->l5 & vpifregs[config_channel_id].len_mask);307 value <<= VPIF_CH_LEN_SHIFT;308 value |= (config->l7 & vpifregs[config_channel_id].len_mask);309 regw(value, vpifregs[channel_id].v_cfg_01);310 311 value = (config->l9 & vpifregs[config_channel_id].len_mask);312 value <<= VPIF_CH_LEN_SHIFT;313 value |= (config->l11 & vpifregs[config_channel_id].len_mask);314 regw(value, vpifregs[channel_id].v_cfg_02);315 316 value = (config->vsize & vpifregs[config_channel_id].len_mask);317 regw(value, vpifregs[channel_id].v_cfg);318}319 320/* config_vpif_params321 * Function to set the parameters of a channel322 * Mainly modifies the channel ciontrol register323 * It sets frame format, yc mux mode324 */325static void config_vpif_params(struct vpif_params *vpifparams,326 u8 channel_id, u8 found)327{328 const struct vpif_channel_config_params *config = &vpifparams->std_info;329 u32 value, ch_nip, reg;330 u8 start, end;331 int i;332 333 start = channel_id;334 end = channel_id + found;335 336 for (i = start; i < end; i++) {337 reg = vpifregs[i].ch_ctrl;338 if (channel_id < 2)339 ch_nip = VPIF_CAPTURE_CH_NIP;340 else341 ch_nip = VPIF_DISPLAY_CH_NIP;342 343 vpif_wr_bit(reg, ch_nip, config->frm_fmt);344 vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);345 vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,346 vpifparams->video_params.storage_mode);347 348 /* Set raster scanning SDR Format */349 vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);350 vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);351 352 if (channel_id > 1) /* Set the Pixel enable bit */353 vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);354 else if (config->capture_format) {355 /* Set the polarity of various pins */356 vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,357 vpifparams->iface.fid_pol);358 vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,359 vpifparams->iface.vd_pol);360 vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,361 vpifparams->iface.hd_pol);362 363 value = regr(reg);364 /* Set data width */365 value &= ~(0x3u <<366 VPIF_CH_DATA_WIDTH_BIT);367 value |= ((vpifparams->params.data_sz) <<368 VPIF_CH_DATA_WIDTH_BIT);369 regw(value, reg);370 }371 372 /* Write the pitch in the driver */373 regw((vpifparams->video_params.hpitch),374 vpifregs[i].line_offset);375 }376}377 378/* vpif_set_video_params379 * This function is used to set video parameters in VPIF register380 */381int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)382{383 const struct vpif_channel_config_params *config = &vpifparams->std_info;384 int found = 1;385 386 vpif_set_mode_info(config, channel_id, channel_id);387 if (!config->ycmux_mode) {388 /* YC are on separate channels (HDTV formats) */389 vpif_set_mode_info(config, channel_id + 1, channel_id);390 found = 2;391 }392 393 config_vpif_params(vpifparams, channel_id, found);394 395 regw(0x80, VPIF_REQ_SIZE);396 regw(0x01, VPIF_EMULATION_CTRL);397 398 return found;399}400EXPORT_SYMBOL(vpif_set_video_params);401 402void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,403 u8 channel_id)404{405 u32 value;406 407 value = 0x3F8 & (vbiparams->hstart0);408 value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);409 regw(value, vpifregs[channel_id].vanc0_strt);410 411 value = 0x3F8 & (vbiparams->hstart1);412 value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);413 regw(value, vpifregs[channel_id].vanc1_strt);414 415 value = 0x3F8 & (vbiparams->hsize0);416 value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);417 regw(value, vpifregs[channel_id].vanc0_size);418 419 value = 0x3F8 & (vbiparams->hsize1);420 value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);421 regw(value, vpifregs[channel_id].vanc1_size);422 423}424EXPORT_SYMBOL(vpif_set_vbi_display_params);425 426int vpif_channel_getfid(u8 channel_id)427{428 return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)429 >> VPIF_CH_FID_SHIFT;430}431EXPORT_SYMBOL(vpif_channel_getfid);432 433static void vpif_pdev_release(struct device *dev)434{435 struct platform_device *pdev = to_platform_device(dev);436 437 kfree(pdev);438}439 440static int vpif_probe(struct platform_device *pdev)441{442 static struct resource res_irq;443 struct platform_device *pdev_capture, *pdev_display;444 struct device_node *endpoint = NULL;445 struct vpif_data *data;446 int ret;447 int irq;448 449 vpif_base = devm_platform_ioremap_resource(pdev, 0);450 if (IS_ERR(vpif_base))451 return PTR_ERR(vpif_base);452 453 data = kzalloc(sizeof(*data), GFP_KERNEL);454 if (!data)455 return -ENOMEM;456 457 platform_set_drvdata(pdev, data);458 459 pm_runtime_enable(&pdev->dev);460 pm_runtime_get(&pdev->dev);461 462 /*463 * If VPIF Node has endpoints, assume "new" DT support,464 * where capture and display drivers don't have DT nodes465 * so their devices need to be registered manually here466 * for their legacy platform_drivers to work.467 */468 endpoint = of_graph_get_endpoint_by_regs(pdev->dev.of_node, 0, -1);469 if (!endpoint)470 return 0;471 of_node_put(endpoint);472 473 /*474 * For DT platforms, manually create platform_devices for475 * capture/display drivers.476 */477 irq = platform_get_irq(pdev, 0);478 if (irq < 0) {479 ret = irq;480 goto err_put_rpm;481 }482 res_irq = DEFINE_RES_IRQ_NAMED(irq, of_node_full_name(pdev->dev.of_node));483 res_irq.flags |= irq_get_trigger_type(irq);484 485 pdev_capture = kzalloc(sizeof(*pdev_capture), GFP_KERNEL);486 if (!pdev_capture) {487 ret = -ENOMEM;488 goto err_put_rpm;489 }490 491 pdev_capture->name = "vpif_capture";492 pdev_capture->id = -1;493 pdev_capture->resource = &res_irq;494 pdev_capture->num_resources = 1;495 pdev_capture->dev.dma_mask = pdev->dev.dma_mask;496 pdev_capture->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;497 pdev_capture->dev.parent = &pdev->dev;498 pdev_capture->dev.release = vpif_pdev_release;499 500 ret = platform_device_register(pdev_capture);501 if (ret)502 goto err_put_pdev_capture;503 504 pdev_display = kzalloc(sizeof(*pdev_display), GFP_KERNEL);505 if (!pdev_display) {506 ret = -ENOMEM;507 goto err_put_pdev_capture;508 }509 510 pdev_display->name = "vpif_display";511 pdev_display->id = -1;512 pdev_display->resource = &res_irq;513 pdev_display->num_resources = 1;514 pdev_display->dev.dma_mask = pdev->dev.dma_mask;515 pdev_display->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask;516 pdev_display->dev.parent = &pdev->dev;517 pdev_display->dev.release = vpif_pdev_release;518 519 ret = platform_device_register(pdev_display);520 if (ret)521 goto err_put_pdev_display;522 523 data->capture = pdev_capture;524 data->display = pdev_display;525 526 return 0;527 528err_put_pdev_display:529 platform_device_put(pdev_display);530err_put_pdev_capture:531 platform_device_put(pdev_capture);532err_put_rpm:533 pm_runtime_put(&pdev->dev);534 pm_runtime_disable(&pdev->dev);535 kfree(data);536 537 return ret;538}539 540static void vpif_remove(struct platform_device *pdev)541{542 struct vpif_data *data = platform_get_drvdata(pdev);543 544 if (data->capture)545 platform_device_unregister(data->capture);546 if (data->display)547 platform_device_unregister(data->display);548 549 pm_runtime_put(&pdev->dev);550 pm_runtime_disable(&pdev->dev);551 552 kfree(data);553}554 555#ifdef CONFIG_PM556static int vpif_suspend(struct device *dev)557{558 pm_runtime_put(dev);559 return 0;560}561 562static int vpif_resume(struct device *dev)563{564 pm_runtime_get(dev);565 return 0;566}567 568static const struct dev_pm_ops vpif_pm = {569 .suspend = vpif_suspend,570 .resume = vpif_resume,571};572 573#define vpif_pm_ops (&vpif_pm)574#else575#define vpif_pm_ops NULL576#endif577 578#if IS_ENABLED(CONFIG_OF)579static const struct of_device_id vpif_of_match[] = {580 { .compatible = "ti,da850-vpif", },581 { /* sentinel */ },582};583MODULE_DEVICE_TABLE(of, vpif_of_match);584#endif585 586static struct platform_driver vpif_driver = {587 .driver = {588 .of_match_table = of_match_ptr(vpif_of_match),589 .name = VPIF_DRIVER_NAME,590 .pm = vpif_pm_ops,591 },592 .remove_new = vpif_remove,593 .probe = vpif_probe,594};595 596static void vpif_exit(void)597{598 platform_driver_unregister(&vpif_driver);599}600 601static int __init vpif_init(void)602{603 return platform_driver_register(&vpif_driver);604}605subsys_initcall(vpif_init);606module_exit(vpif_exit);607 608