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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2013 Texas Instruments Inc.4 *5 * David Griego, <dagriego@biglakesoftware.com>6 * Dale Farnsworth, <dale@farnsworth.org>7 * Archit Taneja, <archit@ti.com>8 */9#ifndef TI_SC_H10#define TI_SC_H11 12/* Scaler regs */13#define CFG_SC0 0x014#define CFG_INTERLACE_O (1 << 0)15#define CFG_LINEAR (1 << 1)16#define CFG_SC_BYPASS (1 << 2)17#define CFG_INVT_FID (1 << 3)18#define CFG_USE_RAV (1 << 4)19#define CFG_ENABLE_EV (1 << 5)20#define CFG_AUTO_HS (1 << 6)21#define CFG_DCM_2X (1 << 7)22#define CFG_DCM_4X (1 << 8)23#define CFG_HP_BYPASS (1 << 9)24#define CFG_INTERLACE_I (1 << 10)25#define CFG_ENABLE_SIN2_VER_INTP (1 << 11)26#define CFG_Y_PK_EN (1 << 14)27#define CFG_TRIM (1 << 15)28#define CFG_SELFGEN_FID (1 << 16)29 30#define CFG_SC1 0x431#define CFG_ROW_ACC_INC_MASK 0x07ffffff32#define CFG_ROW_ACC_INC_SHIFT 033 34#define CFG_SC2 0x0835#define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff36#define CFG_ROW_ACC_OFFSET_SHIFT 037 38#define CFG_SC3 0x0c39#define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff40#define CFG_ROW_ACC_OFFSET_B_SHIFT 041 42#define CFG_SC4 0x1043#define CFG_TAR_H_MASK 0x07ff44#define CFG_TAR_H_SHIFT 045#define CFG_TAR_W_MASK 0x07ff46#define CFG_TAR_W_SHIFT 1247#define CFG_LIN_ACC_INC_U_MASK 0x0748#define CFG_LIN_ACC_INC_U_SHIFT 2449#define CFG_NLIN_ACC_INIT_U_MASK 0x0750#define CFG_NLIN_ACC_INIT_U_SHIFT 2851 52#define CFG_SC5 0x1453#define CFG_SRC_H_MASK 0x07ff54#define CFG_SRC_H_SHIFT 055#define CFG_SRC_W_MASK 0x07ff56#define CFG_SRC_W_SHIFT 1257#define CFG_NLIN_ACC_INC_U_MASK 0x0758#define CFG_NLIN_ACC_INC_U_SHIFT 2459 60#define CFG_SC6 0x1861#define CFG_ROW_ACC_INIT_RAV_MASK 0x03ff62#define CFG_ROW_ACC_INIT_RAV_SHIFT 063#define CFG_ROW_ACC_INIT_RAV_B_MASK 0x03ff64#define CFG_ROW_ACC_INIT_RAV_B_SHIFT 1065 66#define CFG_SC8 0x2067#define CFG_NLIN_LEFT_MASK 0x07ff68#define CFG_NLIN_LEFT_SHIFT 069#define CFG_NLIN_RIGHT_MASK 0x07ff70#define CFG_NLIN_RIGHT_SHIFT 1271 72#define CFG_SC9 0x2473#define CFG_LIN_ACC_INC CFG_SC974 75#define CFG_SC10 0x2876#define CFG_NLIN_ACC_INIT CFG_SC1077 78#define CFG_SC11 0x2c79#define CFG_NLIN_ACC_INC CFG_SC1180 81#define CFG_SC12 0x3082#define CFG_COL_ACC_OFFSET_MASK 0x01ffffff83#define CFG_COL_ACC_OFFSET_SHIFT 084 85#define CFG_SC13 0x3486#define CFG_SC_FACTOR_RAV_MASK 0xff87#define CFG_SC_FACTOR_RAV_SHIFT 088#define CFG_CHROMA_INTP_THR_MASK 0x03ff89#define CFG_CHROMA_INTP_THR_SHIFT 1290#define CFG_DELTA_CHROMA_THR_MASK 0x0f91#define CFG_DELTA_CHROMA_THR_SHIFT 2492 93#define CFG_SC17 0x4494#define CFG_EV_THR_MASK 0x03ff95#define CFG_EV_THR_SHIFT 1296#define CFG_DELTA_LUMA_THR_MASK 0x0f97#define CFG_DELTA_LUMA_THR_SHIFT 2498#define CFG_DELTA_EV_THR_MASK 0x0f99#define CFG_DELTA_EV_THR_SHIFT 28100 101#define CFG_SC18 0x48102#define CFG_HS_FACTOR_MASK 0x03ff103#define CFG_HS_FACTOR_SHIFT 0104#define CFG_CONF_DEFAULT_MASK 0x01ff105#define CFG_CONF_DEFAULT_SHIFT 16106 107#define CFG_SC19 0x4c108#define CFG_HPF_COEFF0_MASK 0xff109#define CFG_HPF_COEFF0_SHIFT 0110#define CFG_HPF_COEFF1_MASK 0xff111#define CFG_HPF_COEFF1_SHIFT 8112#define CFG_HPF_COEFF2_MASK 0xff113#define CFG_HPF_COEFF2_SHIFT 16114#define CFG_HPF_COEFF3_MASK 0xff115#define CFG_HPF_COEFF3_SHIFT 23116 117#define CFG_SC20 0x50118#define CFG_HPF_COEFF4_MASK 0xff119#define CFG_HPF_COEFF4_SHIFT 0120#define CFG_HPF_COEFF5_MASK 0xff121#define CFG_HPF_COEFF5_SHIFT 8122#define CFG_HPF_NORM_SHIFT_MASK 0x07123#define CFG_HPF_NORM_SHIFT_SHIFT 16124#define CFG_NL_LIMIT_MASK 0x1ff125#define CFG_NL_LIMIT_SHIFT 20126 127#define CFG_SC21 0x54128#define CFG_NL_LO_THR_MASK 0x01ff129#define CFG_NL_LO_THR_SHIFT 0130#define CFG_NL_LO_SLOPE_MASK 0xff131#define CFG_NL_LO_SLOPE_SHIFT 16132 133#define CFG_SC22 0x58134#define CFG_NL_HI_THR_MASK 0x01ff135#define CFG_NL_HI_THR_SHIFT 0136#define CFG_NL_HI_SLOPE_SH_MASK 0x07137#define CFG_NL_HI_SLOPE_SH_SHIFT 16138 139#define CFG_SC23 0x5c140#define CFG_GRADIENT_THR_MASK 0x07ff141#define CFG_GRADIENT_THR_SHIFT 0142#define CFG_GRADIENT_THR_RANGE_MASK 0x0f143#define CFG_GRADIENT_THR_RANGE_SHIFT 12144#define CFG_MIN_GY_THR_MASK 0xff145#define CFG_MIN_GY_THR_SHIFT 16146#define CFG_MIN_GY_THR_RANGE_MASK 0x0f147#define CFG_MIN_GY_THR_RANGE_SHIFT 28148 149#define CFG_SC24 0x60150#define CFG_ORG_H_MASK 0x07ff151#define CFG_ORG_H_SHIFT 0152#define CFG_ORG_W_MASK 0x07ff153#define CFG_ORG_W_SHIFT 16154 155#define CFG_SC25 0x64156#define CFG_OFF_H_MASK 0x07ff157#define CFG_OFF_H_SHIFT 0158#define CFG_OFF_W_MASK 0x07ff159#define CFG_OFF_W_SHIFT 16160 161/* number of phases supported by the polyphase scalers */162#define SC_NUM_PHASES 32163 164/* number of taps used by horizontal polyphase scaler */165#define SC_H_NUM_TAPS 7166 167/* number of taps used by vertical polyphase scaler */168#define SC_V_NUM_TAPS 5169 170/* number of taps expected by the scaler in it's coefficient memory */171#define SC_NUM_TAPS_MEM_ALIGN 8172 173/* Maximum frame width the scaler can handle (in pixels) */174#define SC_MAX_PIXEL_WIDTH 2047175 176/* Maximum frame height the scaler can handle (in lines) */177#define SC_MAX_PIXEL_HEIGHT 2047178 179/*180 * coefficient memory size in bytes:181 * num phases x num sets(luma and chroma) x num taps(aligned) x coeff size182 */183#define SC_COEF_SRAM_SIZE (SC_NUM_PHASES * 2 * SC_NUM_TAPS_MEM_ALIGN * 2)184 185struct sc_data {186 void __iomem *base;187 struct resource *res;188 189 dma_addr_t loaded_coeff_h; /* loaded h coeffs in SC */190 dma_addr_t loaded_coeff_v; /* loaded v coeffs in SC */191 192 bool load_coeff_h; /* have new h SC coeffs */193 bool load_coeff_v; /* have new v SC coeffs */194 195 struct platform_device *pdev;196};197 198void sc_dump_regs(struct sc_data *sc);199void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,200 unsigned int dst_w);201void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,202 unsigned int dst_h);203void sc_config_scaler(struct sc_data *sc, u32 *sc_reg0, u32 *sc_reg8,204 u32 *sc_reg17, unsigned int src_w, unsigned int src_h,205 unsigned int dst_w, unsigned int dst_h);206struct sc_data *sc_create(struct platform_device *pdev, const char *res_name);207 208#endif209