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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2013 Texas Instruments Inc.4 *5 * David Griego, <dagriego@biglakesoftware.com>6 * Dale Farnsworth, <dale@farnsworth.org>7 * Archit Taneja, <archit@ti.com>8 */9 10#ifndef _TI_VPDMA_PRIV_H_11#define _TI_VPDMA_PRIV_H_12 13/*14 * VPDMA Register offsets15 */16 17/* Top level */18#define VPDMA_PID 0x0019#define VPDMA_LIST_ADDR 0x0420#define VPDMA_LIST_ATTR 0x0821#define VPDMA_LIST_STAT_SYNC 0x0c22#define VPDMA_BG_RGB 0x1823#define VPDMA_BG_YUV 0x1c24#define VPDMA_SETUP 0x3025#define VPDMA_MAX_SIZE1 0x3426#define VPDMA_MAX_SIZE2 0x3827#define VPDMA_MAX_SIZE3 0x3c28#define VPDMA_MAX_SIZE_WIDTH_MASK 0xffff29#define VPDMA_MAX_SIZE_WIDTH_SHFT 1630#define VPDMA_MAX_SIZE_HEIGHT_MASK 0xffff31#define VPDMA_MAX_SIZE_HEIGHT_SHFT 032 33/* Interrupts */34#define VPDMA_INT_CHAN_STAT(grp) (0x40 + grp * 8)35#define VPDMA_INT_CHAN_MASK(grp) (VPDMA_INT_CHAN_STAT(grp) + 4)36#define VPDMA_INT_CLIENT0_STAT 0x7837#define VPDMA_INT_CLIENT0_MASK 0x7c38#define VPDMA_INT_CLIENT1_STAT 0x8039#define VPDMA_INT_CLIENT1_MASK 0x8440#define VPDMA_INT_LIST0_STAT 0x8841#define VPDMA_INT_LIST0_MASK 0x8c42 43#define VPDMA_INTX_OFFSET 0x5044 45#define VPDMA_PERFMON(i) (0x200 + i * 4)46 47/* VIP/VPE client registers */48#define VPDMA_DEI_CHROMA1_CSTAT 0x030049#define VPDMA_DEI_LUMA1_CSTAT 0x030450#define VPDMA_DEI_LUMA2_CSTAT 0x030851#define VPDMA_DEI_CHROMA2_CSTAT 0x030c52#define VPDMA_DEI_LUMA3_CSTAT 0x031053#define VPDMA_DEI_CHROMA3_CSTAT 0x031454#define VPDMA_DEI_MV_IN_CSTAT 0x033055#define VPDMA_DEI_MV_OUT_CSTAT 0x033c56#define VPDMA_VIP_LO_Y_CSTAT 0x038857#define VPDMA_VIP_LO_UV_CSTAT 0x038c58#define VPDMA_VIP_UP_Y_CSTAT 0x039059#define VPDMA_VIP_UP_UV_CSTAT 0x039460#define VPDMA_VPI_CTL_CSTAT 0x03d061 62/* Reg field info for VPDMA_CLIENT_CSTAT registers */63#define VPDMA_CSTAT_LINE_MODE_MASK 0x0364#define VPDMA_CSTAT_LINE_MODE_SHIFT 865#define VPDMA_CSTAT_FRAME_START_MASK 0xf66#define VPDMA_CSTAT_FRAME_START_SHIFT 1067 68#define VPDMA_LIST_NUM_MASK 0x0769#define VPDMA_LIST_NUM_SHFT 2470#define VPDMA_LIST_STOP_SHFT 2071#define VPDMA_LIST_RDY_MASK 0x0172#define VPDMA_LIST_RDY_SHFT 1973#define VPDMA_LIST_TYPE_MASK 0x0374#define VPDMA_LIST_TYPE_SHFT 1675#define VPDMA_LIST_SIZE_MASK 0xffff76 77/*78 * The YUV data type definition below are taken from79 * both the TRM and i839 Errata information.80 * Use the correct data type considering byte81 * reordering of components.82 *83 * Also since the single use of "C" in the 422 case84 * to mean "Cr" (i.e. V component). It was decided85 * to explicitly label them CR to remove any confusion.86 * Bear in mind that the type label refer to the memory87 * packed order (LSB - MSB).88 */89#define DATA_TYPE_Y444 0x090#define DATA_TYPE_Y422 0x191#define DATA_TYPE_Y420 0x292#define DATA_TYPE_C444 0x493#define DATA_TYPE_C422 0x594#define DATA_TYPE_C420 0x695#define DATA_TYPE_CB420 0x1696#define DATA_TYPE_YC444 0x897#define DATA_TYPE_YCB422 0x798#define DATA_TYPE_YCR422 0x1799#define DATA_TYPE_CBY422 0x27100#define DATA_TYPE_CRY422 0x37101 102/*103 * The RGB data type definition below are defined104 * to follow Errata i819.105 * The initial values were taken from:106 * VPDMA_data_type_mapping_v0.2vayu_c.pdf107 * But some of the ARGB definition appeared to be wrong108 * in the document also. As they would yield RGBA instead.109 * They have been corrected based on experimentation.110 */111#define DATA_TYPE_RGB16_565 0x10112#define DATA_TYPE_ARGB_1555 0x13113#define DATA_TYPE_ARGB_4444 0x14114#define DATA_TYPE_RGBA_5551 0x11115#define DATA_TYPE_RGBA_4444 0x12116#define DATA_TYPE_ARGB24_6666 0x18117#define DATA_TYPE_RGB24_888 0x16118#define DATA_TYPE_ARGB32_8888 0x17119#define DATA_TYPE_RGBA24_6666 0x15120#define DATA_TYPE_RGBA32_8888 0x19121#define DATA_TYPE_BGR16_565 0x0122#define DATA_TYPE_ABGR_1555 0x3123#define DATA_TYPE_ABGR_4444 0x4124#define DATA_TYPE_BGRA_5551 0x1125#define DATA_TYPE_BGRA_4444 0x2126#define DATA_TYPE_ABGR24_6666 0x8127#define DATA_TYPE_BGR24_888 0x6128#define DATA_TYPE_ABGR32_8888 0x7129#define DATA_TYPE_BGRA24_6666 0x5130#define DATA_TYPE_BGRA32_8888 0x9131 132#define DATA_TYPE_MV 0x3133 134/* VPDMA channel numbers, some are common between VIP/VPE and appear twice */135#define VPE_CHAN_NUM_LUMA1_IN 0136#define VPE_CHAN_NUM_CHROMA1_IN 1137#define VPE_CHAN_NUM_LUMA2_IN 2138#define VPE_CHAN_NUM_CHROMA2_IN 3139#define VPE_CHAN_NUM_LUMA3_IN 4140#define VPE_CHAN_NUM_CHROMA3_IN 5141#define VPE_CHAN_NUM_MV_IN 12142#define VPE_CHAN_NUM_MV_OUT 15143#define VIP1_CHAN_NUM_MULT_PORT_A_SRC0 38144#define VIP1_CHAN_NUM_MULT_ANC_A_SRC0 70145#define VPE_CHAN_NUM_LUMA_OUT 102146#define VPE_CHAN_NUM_CHROMA_OUT 103147#define VIP1_CHAN_NUM_PORT_A_LUMA 102148#define VIP1_CHAN_NUM_PORT_A_CHROMA 103149#define VPE_CHAN_NUM_RGB_OUT 106150#define VIP1_CHAN_NUM_PORT_A_RGB 106151#define VIP1_CHAN_NUM_PORT_B_RGB 107152/*153 * a VPDMA address data block payload for a configuration descriptor needs to154 * have each sub block length as a multiple of 16 bytes. Therefore, the overall155 * size of the payload also needs to be a multiple of 16 bytes. The sub block156 * lengths should be ensured to be aligned by the VPDMA user.157 */158#define VPDMA_ADB_SIZE_ALIGN 0x0f159 160/*161 * data transfer descriptor162 */163struct vpdma_dtd {164 u32 type_ctl_stride;165 union {166 u32 xfer_length_height;167 u32 w1;168 };169 u32 start_addr;170 u32 pkt_ctl;171 union {172 u32 frame_width_height; /* inbound */173 u32 desc_write_addr; /* outbound */174 };175 union {176 u32 start_h_v; /* inbound */177 u32 max_width_height; /* outbound */178 };179 u32 client_attr0;180 u32 client_attr1;181};182 183/* Data Transfer Descriptor specifics */184#define DTD_NO_NOTIFY 0185#define DTD_NOTIFY 1186 187#define DTD_PKT_TYPE 0xa188#define DTD_DIR_IN 0189#define DTD_DIR_OUT 1190 191/* type_ctl_stride */192#define DTD_DATA_TYPE_MASK 0x3f193#define DTD_DATA_TYPE_SHFT 26194#define DTD_NOTIFY_MASK 0x01195#define DTD_NOTIFY_SHFT 25196#define DTD_FIELD_MASK 0x01197#define DTD_FIELD_SHFT 24198#define DTD_1D_MASK 0x01199#define DTD_1D_SHFT 23200#define DTD_EVEN_LINE_SKIP_MASK 0x01201#define DTD_EVEN_LINE_SKIP_SHFT 20202#define DTD_ODD_LINE_SKIP_MASK 0x01203#define DTD_ODD_LINE_SKIP_SHFT 16204#define DTD_LINE_STRIDE_MASK 0xffff205#define DTD_LINE_STRIDE_SHFT 0206 207/* xfer_length_height */208#define DTD_LINE_LENGTH_MASK 0xffff209#define DTD_LINE_LENGTH_SHFT 16210#define DTD_XFER_HEIGHT_MASK 0xffff211#define DTD_XFER_HEIGHT_SHFT 0212 213/* pkt_ctl */214#define DTD_PKT_TYPE_MASK 0x1f215#define DTD_PKT_TYPE_SHFT 27216#define DTD_MODE_MASK 0x01217#define DTD_MODE_SHFT 26218#define DTD_DIR_MASK 0x01219#define DTD_DIR_SHFT 25220#define DTD_CHAN_MASK 0x01ff221#define DTD_CHAN_SHFT 16222#define DTD_PRI_MASK 0x0f223#define DTD_PRI_SHFT 9224#define DTD_NEXT_CHAN_MASK 0x01ff225#define DTD_NEXT_CHAN_SHFT 0226 227/* frame_width_height */228#define DTD_FRAME_WIDTH_MASK 0xffff229#define DTD_FRAME_WIDTH_SHFT 16230#define DTD_FRAME_HEIGHT_MASK 0xffff231#define DTD_FRAME_HEIGHT_SHFT 0232 233/* start_h_v */234#define DTD_H_START_MASK 0xffff235#define DTD_H_START_SHFT 16236#define DTD_V_START_MASK 0xffff237#define DTD_V_START_SHFT 0238 239#define DTD_DESC_START_MASK 0xffffffe0240#define DTD_DESC_START_SHIFT 5241#define DTD_WRITE_DESC_MASK 0x01242#define DTD_WRITE_DESC_SHIFT 2243#define DTD_DROP_DATA_MASK 0x01244#define DTD_DROP_DATA_SHIFT 1245#define DTD_USE_DESC_MASK 0x01246#define DTD_USE_DESC_SHIFT 0247 248/* max_width_height */249#define DTD_MAX_WIDTH_MASK 0x07250#define DTD_MAX_WIDTH_SHFT 4251#define DTD_MAX_HEIGHT_MASK 0x07252#define DTD_MAX_HEIGHT_SHFT 0253 254static inline u32 dtd_type_ctl_stride(int type, bool notify, int field,255 bool one_d, bool even_line_skip, bool odd_line_skip,256 int line_stride)257{258 return (type << DTD_DATA_TYPE_SHFT) | (notify << DTD_NOTIFY_SHFT) |259 (field << DTD_FIELD_SHFT) | (one_d << DTD_1D_SHFT) |260 (even_line_skip << DTD_EVEN_LINE_SKIP_SHFT) |261 (odd_line_skip << DTD_ODD_LINE_SKIP_SHFT) |262 line_stride;263}264 265static inline u32 dtd_xfer_length_height(int line_length, int xfer_height)266{267 return (line_length << DTD_LINE_LENGTH_SHFT) | xfer_height;268}269 270static inline u32 dtd_pkt_ctl(bool mode, bool dir, int chan, int pri,271 int next_chan)272{273 return (DTD_PKT_TYPE << DTD_PKT_TYPE_SHFT) | (mode << DTD_MODE_SHFT) |274 (dir << DTD_DIR_SHFT) | (chan << DTD_CHAN_SHFT) |275 (pri << DTD_PRI_SHFT) | next_chan;276}277 278static inline u32 dtd_frame_width_height(int width, int height)279{280 return (width << DTD_FRAME_WIDTH_SHFT) | height;281}282 283static inline u32 dtd_desc_write_addr(unsigned int addr, bool write_desc,284 bool drop_data, bool use_desc)285{286 return (addr & DTD_DESC_START_MASK) |287 (write_desc << DTD_WRITE_DESC_SHIFT) |288 (drop_data << DTD_DROP_DATA_SHIFT) |289 use_desc;290}291 292static inline u32 dtd_start_h_v(int h_start, int v_start)293{294 return (h_start << DTD_H_START_SHFT) | v_start;295}296 297static inline u32 dtd_max_width_height(int max_width, int max_height)298{299 return (max_width << DTD_MAX_WIDTH_SHFT) | max_height;300}301 302static inline int dtd_get_data_type(struct vpdma_dtd *dtd)303{304 return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT;305}306 307static inline bool dtd_get_notify(struct vpdma_dtd *dtd)308{309 return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK;310}311 312static inline int dtd_get_field(struct vpdma_dtd *dtd)313{314 return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK;315}316 317static inline bool dtd_get_1d(struct vpdma_dtd *dtd)318{319 return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK;320}321 322static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd)323{324 return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT)325 & DTD_EVEN_LINE_SKIP_MASK;326}327 328static inline bool dtd_get_odd_line_skip(struct vpdma_dtd *dtd)329{330 return (dtd->type_ctl_stride >> DTD_ODD_LINE_SKIP_SHFT)331 & DTD_ODD_LINE_SKIP_MASK;332}333 334static inline int dtd_get_line_stride(struct vpdma_dtd *dtd)335{336 return dtd->type_ctl_stride & DTD_LINE_STRIDE_MASK;337}338 339static inline int dtd_get_line_length(struct vpdma_dtd *dtd)340{341 return dtd->xfer_length_height >> DTD_LINE_LENGTH_SHFT;342}343 344static inline int dtd_get_xfer_height(struct vpdma_dtd *dtd)345{346 return dtd->xfer_length_height & DTD_XFER_HEIGHT_MASK;347}348 349static inline int dtd_get_pkt_type(struct vpdma_dtd *dtd)350{351 return dtd->pkt_ctl >> DTD_PKT_TYPE_SHFT;352}353 354static inline bool dtd_get_mode(struct vpdma_dtd *dtd)355{356 return (dtd->pkt_ctl >> DTD_MODE_SHFT) & DTD_MODE_MASK;357}358 359static inline bool dtd_get_dir(struct vpdma_dtd *dtd)360{361 return (dtd->pkt_ctl >> DTD_DIR_SHFT) & DTD_DIR_MASK;362}363 364static inline int dtd_get_chan(struct vpdma_dtd *dtd)365{366 return (dtd->pkt_ctl >> DTD_CHAN_SHFT) & DTD_CHAN_MASK;367}368 369static inline int dtd_get_priority(struct vpdma_dtd *dtd)370{371 return (dtd->pkt_ctl >> DTD_PRI_SHFT) & DTD_PRI_MASK;372}373 374static inline int dtd_get_next_chan(struct vpdma_dtd *dtd)375{376 return (dtd->pkt_ctl >> DTD_NEXT_CHAN_SHFT) & DTD_NEXT_CHAN_MASK;377}378 379static inline int dtd_get_frame_width(struct vpdma_dtd *dtd)380{381 return dtd->frame_width_height >> DTD_FRAME_WIDTH_SHFT;382}383 384static inline int dtd_get_frame_height(struct vpdma_dtd *dtd)385{386 return dtd->frame_width_height & DTD_FRAME_HEIGHT_MASK;387}388 389static inline int dtd_get_desc_write_addr(struct vpdma_dtd *dtd)390{391 return dtd->desc_write_addr & DTD_DESC_START_MASK;392}393 394static inline bool dtd_get_write_desc(struct vpdma_dtd *dtd)395{396 return (dtd->desc_write_addr >> DTD_WRITE_DESC_SHIFT) &397 DTD_WRITE_DESC_MASK;398}399 400static inline bool dtd_get_drop_data(struct vpdma_dtd *dtd)401{402 return (dtd->desc_write_addr >> DTD_DROP_DATA_SHIFT) &403 DTD_DROP_DATA_MASK;404}405 406static inline bool dtd_get_use_desc(struct vpdma_dtd *dtd)407{408 return dtd->desc_write_addr & DTD_USE_DESC_MASK;409}410 411static inline int dtd_get_h_start(struct vpdma_dtd *dtd)412{413 return dtd->start_h_v >> DTD_H_START_SHFT;414}415 416static inline int dtd_get_v_start(struct vpdma_dtd *dtd)417{418 return dtd->start_h_v & DTD_V_START_MASK;419}420 421static inline int dtd_get_max_width(struct vpdma_dtd *dtd)422{423 return (dtd->max_width_height >> DTD_MAX_WIDTH_SHFT) &424 DTD_MAX_WIDTH_MASK;425}426 427static inline int dtd_get_max_height(struct vpdma_dtd *dtd)428{429 return (dtd->max_width_height >> DTD_MAX_HEIGHT_SHFT) &430 DTD_MAX_HEIGHT_MASK;431}432 433/*434 * configuration descriptor435 */436struct vpdma_cfd {437 union {438 u32 dest_addr_offset;439 u32 w0;440 };441 union {442 u32 block_len; /* in words */443 u32 w1;444 };445 u32 payload_addr;446 u32 ctl_payload_len; /* in words */447};448 449/* Configuration descriptor specifics */450 451#define CFD_PKT_TYPE 0xb452 453#define CFD_DIRECT 1454#define CFD_INDIRECT 0455#define CFD_CLS_ADB 0456#define CFD_CLS_BLOCK 1457 458/* block_len */459#define CFD__BLOCK_LEN_MASK 0xffff460#define CFD__BLOCK_LEN_SHFT 0461 462/* ctl_payload_len */463#define CFD_PKT_TYPE_MASK 0x1f464#define CFD_PKT_TYPE_SHFT 27465#define CFD_DIRECT_MASK 0x01466#define CFD_DIRECT_SHFT 26467#define CFD_CLASS_MASK 0x03468#define CFD_CLASS_SHFT 24469#define CFD_DEST_MASK 0xff470#define CFD_DEST_SHFT 16471#define CFD_PAYLOAD_LEN_MASK 0xffff472#define CFD_PAYLOAD_LEN_SHFT 0473 474static inline u32 cfd_pkt_payload_len(bool direct, int cls, int dest,475 int payload_len)476{477 return (CFD_PKT_TYPE << CFD_PKT_TYPE_SHFT) |478 (direct << CFD_DIRECT_SHFT) |479 (cls << CFD_CLASS_SHFT) |480 (dest << CFD_DEST_SHFT) |481 payload_len;482}483 484static inline int cfd_get_pkt_type(struct vpdma_cfd *cfd)485{486 return cfd->ctl_payload_len >> CFD_PKT_TYPE_SHFT;487}488 489static inline bool cfd_get_direct(struct vpdma_cfd *cfd)490{491 return (cfd->ctl_payload_len >> CFD_DIRECT_SHFT) & CFD_DIRECT_MASK;492}493 494static inline bool cfd_get_class(struct vpdma_cfd *cfd)495{496 return (cfd->ctl_payload_len >> CFD_CLASS_SHFT) & CFD_CLASS_MASK;497}498 499static inline int cfd_get_dest(struct vpdma_cfd *cfd)500{501 return (cfd->ctl_payload_len >> CFD_DEST_SHFT) & CFD_DEST_MASK;502}503 504static inline int cfd_get_payload_len(struct vpdma_cfd *cfd)505{506 return cfd->ctl_payload_len & CFD_PAYLOAD_LEN_MASK;507}508 509/*510 * control descriptor511 */512struct vpdma_ctd {513 union {514 u32 timer_value;515 u32 list_addr;516 u32 w0;517 };518 union {519 u32 pixel_line_count;520 u32 list_size;521 u32 w1;522 };523 union {524 u32 event;525 u32 fid_ctl;526 u32 w2;527 };528 u32 type_source_ctl;529};530 531/* control descriptor types */532#define CTD_TYPE_SYNC_ON_CLIENT 0533#define CTD_TYPE_SYNC_ON_LIST 1534#define CTD_TYPE_SYNC_ON_EXT 2535#define CTD_TYPE_SYNC_ON_LM_TIMER 3536#define CTD_TYPE_SYNC_ON_CHANNEL 4537#define CTD_TYPE_CHNG_CLIENT_IRQ 5538#define CTD_TYPE_SEND_IRQ 6539#define CTD_TYPE_RELOAD_LIST 7540#define CTD_TYPE_ABORT_CHANNEL 8541 542#define CTD_PKT_TYPE 0xc543 544/* timer_value */545#define CTD_TIMER_VALUE_MASK 0xffff546#define CTD_TIMER_VALUE_SHFT 0547 548/* pixel_line_count */549#define CTD_PIXEL_COUNT_MASK 0xffff550#define CTD_PIXEL_COUNT_SHFT 16551#define CTD_LINE_COUNT_MASK 0xffff552#define CTD_LINE_COUNT_SHFT 0553 554/* list_size */555#define CTD_LIST_SIZE_MASK 0xffff556#define CTD_LIST_SIZE_SHFT 0557 558/* event */559#define CTD_EVENT_MASK 0x0f560#define CTD_EVENT_SHFT 0561 562/* fid_ctl */563#define CTD_FID2_MASK 0x03564#define CTD_FID2_SHFT 4565#define CTD_FID1_MASK 0x03566#define CTD_FID1_SHFT 2567#define CTD_FID0_MASK 0x03568#define CTD_FID0_SHFT 0569 570/* type_source_ctl */571#define CTD_PKT_TYPE_MASK 0x1f572#define CTD_PKT_TYPE_SHFT 27573#define CTD_SOURCE_MASK 0xff574#define CTD_SOURCE_SHFT 16575#define CTD_CONTROL_MASK 0x0f576#define CTD_CONTROL_SHFT 0577 578static inline u32 ctd_pixel_line_count(int pixel_count, int line_count)579{580 return (pixel_count << CTD_PIXEL_COUNT_SHFT) | line_count;581}582 583static inline u32 ctd_set_fid_ctl(int fid0, int fid1, int fid2)584{585 return (fid2 << CTD_FID2_SHFT) | (fid1 << CTD_FID1_SHFT) | fid0;586}587 588static inline u32 ctd_type_source_ctl(int source, int control)589{590 return (CTD_PKT_TYPE << CTD_PKT_TYPE_SHFT) |591 (source << CTD_SOURCE_SHFT) | control;592}593 594static inline u32 ctd_get_pixel_count(struct vpdma_ctd *ctd)595{596 return ctd->pixel_line_count >> CTD_PIXEL_COUNT_SHFT;597}598 599static inline int ctd_get_line_count(struct vpdma_ctd *ctd)600{601 return ctd->pixel_line_count & CTD_LINE_COUNT_MASK;602}603 604static inline int ctd_get_event(struct vpdma_ctd *ctd)605{606 return ctd->event & CTD_EVENT_MASK;607}608 609static inline int ctd_get_fid2_ctl(struct vpdma_ctd *ctd)610{611 return (ctd->fid_ctl >> CTD_FID2_SHFT) & CTD_FID2_MASK;612}613 614static inline int ctd_get_fid1_ctl(struct vpdma_ctd *ctd)615{616 return (ctd->fid_ctl >> CTD_FID1_SHFT) & CTD_FID1_MASK;617}618 619static inline int ctd_get_fid0_ctl(struct vpdma_ctd *ctd)620{621 return ctd->fid_ctl & CTD_FID2_MASK;622}623 624static inline int ctd_get_pkt_type(struct vpdma_ctd *ctd)625{626 return ctd->type_source_ctl >> CTD_PKT_TYPE_SHFT;627}628 629static inline int ctd_get_source(struct vpdma_ctd *ctd)630{631 return (ctd->type_source_ctl >> CTD_SOURCE_SHFT) & CTD_SOURCE_MASK;632}633 634static inline int ctd_get_ctl(struct vpdma_ctd *ctd)635{636 return ctd->type_source_ctl & CTD_CONTROL_MASK;637}638 639#endif640