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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2013 Texas Instruments Inc.4 *5 * David Griego, <dagriego@biglakesoftware.com>6 * Dale Farnsworth, <dale@farnsworth.org>7 * Archit Taneja, <archit@ti.com>8 */9 10#ifndef __TI_VPE_REGS_H11#define __TI_VPE_REGS_H12 13/* VPE register offsets and field selectors */14 15/* VPE top level regs */16#define VPE_PID 0x000017#define VPE_PID_MINOR_MASK 0x3f18#define VPE_PID_MINOR_SHIFT 019#define VPE_PID_CUSTOM_MASK 0x0320#define VPE_PID_CUSTOM_SHIFT 621#define VPE_PID_MAJOR_MASK 0x0722#define VPE_PID_MAJOR_SHIFT 823#define VPE_PID_RTL_MASK 0x1f24#define VPE_PID_RTL_SHIFT 1125#define VPE_PID_FUNC_MASK 0xfff26#define VPE_PID_FUNC_SHIFT 1627#define VPE_PID_SCHEME_MASK 0x0328#define VPE_PID_SCHEME_SHIFT 3029 30#define VPE_SYSCONFIG 0x001031#define VPE_SYSCONFIG_IDLE_MASK 0x0332#define VPE_SYSCONFIG_IDLE_SHIFT 233#define VPE_SYSCONFIG_STANDBY_MASK 0x0334#define VPE_SYSCONFIG_STANDBY_SHIFT 435#define VPE_FORCE_IDLE_MODE 036#define VPE_NO_IDLE_MODE 137#define VPE_SMART_IDLE_MODE 238#define VPE_SMART_IDLE_WAKEUP_MODE 339#define VPE_FORCE_STANDBY_MODE 040#define VPE_NO_STANDBY_MODE 141#define VPE_SMART_STANDBY_MODE 242#define VPE_SMART_STANDBY_WAKEUP_MODE 343 44#define VPE_INT0_STATUS0_RAW_SET 0x002045#define VPE_INT0_STATUS0_RAW VPE_INT0_STATUS0_RAW_SET46#define VPE_INT0_STATUS0_CLR 0x002847#define VPE_INT0_STATUS0 VPE_INT0_STATUS0_CLR48#define VPE_INT0_ENABLE0_SET 0x003049#define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET50#define VPE_INT0_ENABLE0_CLR 0x003851#define VPE_INT0_LIST0_COMPLETE BIT(0)52#define VPE_INT0_LIST0_NOTIFY BIT(1)53#define VPE_INT0_LIST1_COMPLETE BIT(2)54#define VPE_INT0_LIST1_NOTIFY BIT(3)55#define VPE_INT0_LIST2_COMPLETE BIT(4)56#define VPE_INT0_LIST2_NOTIFY BIT(5)57#define VPE_INT0_LIST3_COMPLETE BIT(6)58#define VPE_INT0_LIST3_NOTIFY BIT(7)59#define VPE_INT0_LIST4_COMPLETE BIT(8)60#define VPE_INT0_LIST4_NOTIFY BIT(9)61#define VPE_INT0_LIST5_COMPLETE BIT(10)62#define VPE_INT0_LIST5_NOTIFY BIT(11)63#define VPE_INT0_LIST6_COMPLETE BIT(12)64#define VPE_INT0_LIST6_NOTIFY BIT(13)65#define VPE_INT0_LIST7_COMPLETE BIT(14)66#define VPE_INT0_LIST7_NOTIFY BIT(15)67#define VPE_INT0_DESCRIPTOR BIT(16)68#define VPE_DEI_FMD_INT BIT(18)69 70#define VPE_INT0_STATUS1_RAW_SET 0x002471#define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET72#define VPE_INT0_STATUS1_CLR 0x002c73#define VPE_INT0_STATUS1 VPE_INT0_STATUS1_CLR74#define VPE_INT0_ENABLE1_SET 0x003475#define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET76#define VPE_INT0_ENABLE1_CLR 0x003c77#define VPE_INT0_CHANNEL_GROUP0 BIT(0)78#define VPE_INT0_CHANNEL_GROUP1 BIT(1)79#define VPE_INT0_CHANNEL_GROUP2 BIT(2)80#define VPE_INT0_CHANNEL_GROUP3 BIT(3)81#define VPE_INT0_CHANNEL_GROUP4 BIT(4)82#define VPE_INT0_CHANNEL_GROUP5 BIT(5)83#define VPE_INT0_CLIENT BIT(7)84#define VPE_DEI_ERROR_INT BIT(16)85#define VPE_DS1_UV_ERROR_INT BIT(22)86 87#define VPE_INTC_EOI 0x00a088 89#define VPE_CLK_ENABLE 0x010090#define VPE_VPEDMA_CLK_ENABLE BIT(0)91#define VPE_DATA_PATH_CLK_ENABLE BIT(1)92 93#define VPE_CLK_RESET 0x010494#define VPE_VPDMA_CLK_RESET_MASK 0x195#define VPE_VPDMA_CLK_RESET_SHIFT 096#define VPE_DATA_PATH_CLK_RESET_MASK 0x197#define VPE_DATA_PATH_CLK_RESET_SHIFT 198#define VPE_MAIN_RESET_MASK 0x199#define VPE_MAIN_RESET_SHIFT 31100 101#define VPE_CLK_FORMAT_SELECT 0x010c102#define VPE_CSC_SRC_SELECT_MASK 0x03103#define VPE_CSC_SRC_SELECT_SHIFT 0104#define VPE_RGB_OUT_SELECT BIT(8)105#define VPE_DS_SRC_SELECT_MASK 0x07106#define VPE_DS_SRC_SELECT_SHIFT 9107#define VPE_DS_BYPASS BIT(16)108#define VPE_COLOR_SEPARATE_422 BIT(18)109 110#define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT)111#define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT)112 113#define VPE_CLK_RANGE_MAP 0x011c114#define VPE_RANGE_RANGE_MAP_Y_MASK 0x07115#define VPE_RANGE_RANGE_MAP_Y_SHIFT 0116#define VPE_RANGE_RANGE_MAP_UV_MASK 0x07117#define VPE_RANGE_RANGE_MAP_UV_SHIFT 3118#define VPE_RANGE_MAP_ON BIT(6)119#define VPE_RANGE_REDUCTION_ON BIT(28)120 121/* VPE chrominance upsampler regs */122#define VPE_US1_R0 0x0304123#define VPE_US2_R0 0x0404124#define VPE_US3_R0 0x0504125#define VPE_US_C1_MASK 0x3fff126#define VPE_US_C1_SHIFT 2127#define VPE_US_C0_MASK 0x3fff128#define VPE_US_C0_SHIFT 18129#define VPE_US_MODE_MASK 0x03130#define VPE_US_MODE_SHIFT 16131#define VPE_ANCHOR_FID0_C1_MASK 0x3fff132#define VPE_ANCHOR_FID0_C1_SHIFT 2133#define VPE_ANCHOR_FID0_C0_MASK 0x3fff134#define VPE_ANCHOR_FID0_C0_SHIFT 18135 136#define VPE_US1_R1 0x0308137#define VPE_US2_R1 0x0408138#define VPE_US3_R1 0x0508139#define VPE_ANCHOR_FID0_C3_MASK 0x3fff140#define VPE_ANCHOR_FID0_C3_SHIFT 2141#define VPE_ANCHOR_FID0_C2_MASK 0x3fff142#define VPE_ANCHOR_FID0_C2_SHIFT 18143 144#define VPE_US1_R2 0x030c145#define VPE_US2_R2 0x040c146#define VPE_US3_R2 0x050c147#define VPE_INTERP_FID0_C1_MASK 0x3fff148#define VPE_INTERP_FID0_C1_SHIFT 2149#define VPE_INTERP_FID0_C0_MASK 0x3fff150#define VPE_INTERP_FID0_C0_SHIFT 18151 152#define VPE_US1_R3 0x0310153#define VPE_US2_R3 0x0410154#define VPE_US3_R3 0x0510155#define VPE_INTERP_FID0_C3_MASK 0x3fff156#define VPE_INTERP_FID0_C3_SHIFT 2157#define VPE_INTERP_FID0_C2_MASK 0x3fff158#define VPE_INTERP_FID0_C2_SHIFT 18159 160#define VPE_US1_R4 0x0314161#define VPE_US2_R4 0x0414162#define VPE_US3_R4 0x0514163#define VPE_ANCHOR_FID1_C1_MASK 0x3fff164#define VPE_ANCHOR_FID1_C1_SHIFT 2165#define VPE_ANCHOR_FID1_C0_MASK 0x3fff166#define VPE_ANCHOR_FID1_C0_SHIFT 18167 168#define VPE_US1_R5 0x0318169#define VPE_US2_R5 0x0418170#define VPE_US3_R5 0x0518171#define VPE_ANCHOR_FID1_C3_MASK 0x3fff172#define VPE_ANCHOR_FID1_C3_SHIFT 2173#define VPE_ANCHOR_FID1_C2_MASK 0x3fff174#define VPE_ANCHOR_FID1_C2_SHIFT 18175 176#define VPE_US1_R6 0x031c177#define VPE_US2_R6 0x041c178#define VPE_US3_R6 0x051c179#define VPE_INTERP_FID1_C1_MASK 0x3fff180#define VPE_INTERP_FID1_C1_SHIFT 2181#define VPE_INTERP_FID1_C0_MASK 0x3fff182#define VPE_INTERP_FID1_C0_SHIFT 18183 184#define VPE_US1_R7 0x0320185#define VPE_US2_R7 0x0420186#define VPE_US3_R7 0x0520187#define VPE_INTERP_FID0_C3_MASK 0x3fff188#define VPE_INTERP_FID0_C3_SHIFT 2189#define VPE_INTERP_FID0_C2_MASK 0x3fff190#define VPE_INTERP_FID0_C2_SHIFT 18191 192/* VPE de-interlacer regs */193#define VPE_DEI_FRAME_SIZE 0x0600194#define VPE_DEI_WIDTH_MASK 0x07ff195#define VPE_DEI_WIDTH_SHIFT 0196#define VPE_DEI_HEIGHT_MASK 0x07ff197#define VPE_DEI_HEIGHT_SHIFT 16198#define VPE_DEI_INTERLACE_BYPASS BIT(29)199#define VPE_DEI_FIELD_FLUSH BIT(30)200#define VPE_DEI_PROGRESSIVE BIT(31)201 202#define VPE_MDT_BYPASS 0x0604203#define VPE_MDT_TEMPMAX_BYPASS BIT(0)204#define VPE_MDT_SPATMAX_BYPASS BIT(1)205 206#define VPE_MDT_SF_THRESHOLD 0x0608207#define VPE_MDT_SF_SC_THR1_MASK 0xff208#define VPE_MDT_SF_SC_THR1_SHIFT 0209#define VPE_MDT_SF_SC_THR2_MASK 0xff210#define VPE_MDT_SF_SC_THR2_SHIFT 0211#define VPE_MDT_SF_SC_THR3_MASK 0xff212#define VPE_MDT_SF_SC_THR3_SHIFT 0213 214#define VPE_EDI_CONFIG 0x060c215#define VPE_EDI_INP_MODE_MASK 0x03216#define VPE_EDI_INP_MODE_SHIFT 0217#define VPE_EDI_ENABLE_3D BIT(2)218#define VPE_EDI_ENABLE_CHROMA_3D BIT(3)219#define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff220#define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8221#define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff222#define VPE_EDI_DIR_COR_LOWER_THR_SHIFT 16223#define VPE_EDI_COR_SCALE_FACTOR_MASK 0xff224#define VPE_EDI_COR_SCALE_FACTOR_SHIFT 23225 226#define VPE_DEI_EDI_LUT_R0 0x0610227#define VPE_EDI_LUT0_MASK 0x1f228#define VPE_EDI_LUT0_SHIFT 0229#define VPE_EDI_LUT1_MASK 0x1f230#define VPE_EDI_LUT1_SHIFT 8231#define VPE_EDI_LUT2_MASK 0x1f232#define VPE_EDI_LUT2_SHIFT 16233#define VPE_EDI_LUT3_MASK 0x1f234#define VPE_EDI_LUT3_SHIFT 24235 236#define VPE_DEI_EDI_LUT_R1 0x0614237#define VPE_EDI_LUT0_MASK 0x1f238#define VPE_EDI_LUT0_SHIFT 0239#define VPE_EDI_LUT1_MASK 0x1f240#define VPE_EDI_LUT1_SHIFT 8241#define VPE_EDI_LUT2_MASK 0x1f242#define VPE_EDI_LUT2_SHIFT 16243#define VPE_EDI_LUT3_MASK 0x1f244#define VPE_EDI_LUT3_SHIFT 24245 246#define VPE_DEI_EDI_LUT_R2 0x0618247#define VPE_EDI_LUT4_MASK 0x1f248#define VPE_EDI_LUT4_SHIFT 0249#define VPE_EDI_LUT5_MASK 0x1f250#define VPE_EDI_LUT5_SHIFT 8251#define VPE_EDI_LUT6_MASK 0x1f252#define VPE_EDI_LUT6_SHIFT 16253#define VPE_EDI_LUT7_MASK 0x1f254#define VPE_EDI_LUT7_SHIFT 24255 256#define VPE_DEI_EDI_LUT_R3 0x061c257#define VPE_EDI_LUT8_MASK 0x1f258#define VPE_EDI_LUT8_SHIFT 0259#define VPE_EDI_LUT9_MASK 0x1f260#define VPE_EDI_LUT9_SHIFT 8261#define VPE_EDI_LUT10_MASK 0x1f262#define VPE_EDI_LUT10_SHIFT 16263#define VPE_EDI_LUT11_MASK 0x1f264#define VPE_EDI_LUT11_SHIFT 24265 266#define VPE_DEI_FMD_WINDOW_R0 0x0620267#define VPE_FMD_WINDOW_MINX_MASK 0x07ff268#define VPE_FMD_WINDOW_MINX_SHIFT 0269#define VPE_FMD_WINDOW_MAXX_MASK 0x07ff270#define VPE_FMD_WINDOW_MAXX_SHIFT 16271#define VPE_FMD_WINDOW_ENABLE BIT(31)272 273#define VPE_DEI_FMD_WINDOW_R1 0x0624274#define VPE_FMD_WINDOW_MINY_MASK 0x07ff275#define VPE_FMD_WINDOW_MINY_SHIFT 0276#define VPE_FMD_WINDOW_MAXY_MASK 0x07ff277#define VPE_FMD_WINDOW_MAXY_SHIFT 16278 279#define VPE_DEI_FMD_CONTROL_R0 0x0628280#define VPE_FMD_ENABLE BIT(0)281#define VPE_FMD_LOCK BIT(1)282#define VPE_FMD_JAM_DIR BIT(2)283#define VPE_FMD_BED_ENABLE BIT(3)284#define VPE_FMD_CAF_FIELD_THR_MASK 0xff285#define VPE_FMD_CAF_FIELD_THR_SHIFT 16286#define VPE_FMD_CAF_LINE_THR_MASK 0xff287#define VPE_FMD_CAF_LINE_THR_SHIFT 24288 289#define VPE_DEI_FMD_CONTROL_R1 0x062c290#define VPE_FMD_CAF_THR_MASK 0x000fffff291#define VPE_FMD_CAF_THR_SHIFT 0292 293#define VPE_DEI_FMD_STATUS_R0 0x0630294#define VPE_FMD_CAF_MASK 0x000fffff295#define VPE_FMD_CAF_SHIFT 0296#define VPE_FMD_RESET BIT(24)297 298#define VPE_DEI_FMD_STATUS_R1 0x0634299#define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff300#define VPE_FMD_FIELD_DIFF_SHIFT 0301 302#define VPE_DEI_FMD_STATUS_R2 0x0638303#define VPE_FMD_FRAME_DIFF_MASK 0x000fffff304#define VPE_FMD_FRAME_DIFF_SHIFT 0305 306#endif307