235 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Xilinx Video IP Core4 *5 * Copyright (C) 2013-2015 Ideas on Board6 * Copyright (C) 2013-2015 Xilinx, Inc.7 *8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>10 */11 12#ifndef __XILINX_VIP_H__13#define __XILINX_VIP_H__14 15#include <linux/bitops.h>16#include <linux/io.h>17#include <media/v4l2-subdev.h>18 19struct clk;20 21/*22 * Minimum and maximum width and height common to most video IP cores. IP23 * cores with different requirements must define their own values.24 */25#define XVIP_MIN_WIDTH 3226#define XVIP_MAX_WIDTH 768027#define XVIP_MIN_HEIGHT 3228#define XVIP_MAX_HEIGHT 768029 30/*31 * Pad IDs. IP cores with multiple inputs or outputs should define their own32 * values.33 */34#define XVIP_PAD_SINK 035#define XVIP_PAD_SOURCE 136 37/* Xilinx Video IP Control Registers */38#define XVIP_CTRL_CONTROL 0x000039#define XVIP_CTRL_CONTROL_SW_ENABLE BIT(0)40#define XVIP_CTRL_CONTROL_REG_UPDATE BIT(1)41#define XVIP_CTRL_CONTROL_BYPASS BIT(4)42#define XVIP_CTRL_CONTROL_TEST_PATTERN BIT(5)43#define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30)44#define XVIP_CTRL_CONTROL_SW_RESET BIT(31)45#define XVIP_CTRL_STATUS 0x000446#define XVIP_CTRL_STATUS_PROC_STARTED BIT(0)47#define XVIP_CTRL_STATUS_EOF BIT(1)48#define XVIP_CTRL_ERROR 0x000849#define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY BIT(0)50#define XVIP_CTRL_ERROR_SLAVE_EOL_LATE BIT(1)51#define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY BIT(2)52#define XVIP_CTRL_ERROR_SLAVE_SOF_LATE BIT(3)53#define XVIP_CTRL_IRQ_ENABLE 0x000c54#define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED BIT(0)55#define XVIP_CTRL_IRQ_EOF BIT(1)56#define XVIP_CTRL_VERSION 0x001057#define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24)58#define XVIP_CTRL_VERSION_MAJOR_SHIFT 2459#define XVIP_CTRL_VERSION_MINOR_MASK (0xff << 16)60#define XVIP_CTRL_VERSION_MINOR_SHIFT 1661#define XVIP_CTRL_VERSION_REVISION_MASK (0xf << 12)62#define XVIP_CTRL_VERSION_REVISION_SHIFT 1263#define XVIP_CTRL_VERSION_PATCH_MASK (0xf << 8)64#define XVIP_CTRL_VERSION_PATCH_SHIFT 865#define XVIP_CTRL_VERSION_INTERNAL_MASK (0xff << 0)66#define XVIP_CTRL_VERSION_INTERNAL_SHIFT 067 68/* Xilinx Video IP Timing Registers */69#define XVIP_ACTIVE_SIZE 0x002070#define XVIP_ACTIVE_VSIZE_MASK (0x7ff << 16)71#define XVIP_ACTIVE_VSIZE_SHIFT 1672#define XVIP_ACTIVE_HSIZE_MASK (0x7ff << 0)73#define XVIP_ACTIVE_HSIZE_SHIFT 074#define XVIP_ENCODING 0x002875#define XVIP_ENCODING_NBITS_8 (0 << 4)76#define XVIP_ENCODING_NBITS_10 (1 << 4)77#define XVIP_ENCODING_NBITS_12 (2 << 4)78#define XVIP_ENCODING_NBITS_16 (3 << 4)79#define XVIP_ENCODING_NBITS_MASK (3 << 4)80#define XVIP_ENCODING_NBITS_SHIFT 481#define XVIP_ENCODING_VIDEO_FORMAT_YUV422 (0 << 0)82#define XVIP_ENCODING_VIDEO_FORMAT_YUV444 (1 << 0)83#define XVIP_ENCODING_VIDEO_FORMAT_RGB (2 << 0)84#define XVIP_ENCODING_VIDEO_FORMAT_YUV420 (3 << 0)85#define XVIP_ENCODING_VIDEO_FORMAT_MASK (3 << 0)86#define XVIP_ENCODING_VIDEO_FORMAT_SHIFT 087 88/**89 * struct xvip_device - Xilinx Video IP device structure90 * @subdev: V4L2 subdevice91 * @dev: (OF) device92 * @iomem: device I/O register space remapped to kernel virtual memory93 * @clk: video core clock94 * @saved_ctrl: saved control register for resume / suspend95 */96struct xvip_device {97 struct v4l2_subdev subdev;98 struct device *dev;99 void __iomem *iomem;100 struct clk *clk;101 u32 saved_ctrl;102};103 104/**105 * struct xvip_video_format - Xilinx Video IP video format description106 * @vf_code: AXI4 video format code107 * @width: AXI4 format width in bits per component108 * @pattern: CFA pattern for Mono/Sensor formats109 * @code: media bus format code110 * @bpp: bytes per pixel (when stored in memory)111 * @fourcc: V4L2 pixel format FCC identifier112 */113struct xvip_video_format {114 unsigned int vf_code;115 unsigned int width;116 const char *pattern;117 unsigned int code;118 unsigned int bpp;119 u32 fourcc;120};121 122const struct xvip_video_format *xvip_get_format_by_code(unsigned int code);123const struct xvip_video_format *xvip_get_format_by_fourcc(u32 fourcc);124const struct xvip_video_format *xvip_of_get_format(struct device_node *node);125void xvip_set_format_size(struct v4l2_mbus_framefmt *format,126 const struct v4l2_subdev_format *fmt);127int xvip_enum_mbus_code(struct v4l2_subdev *subdev,128 struct v4l2_subdev_state *sd_state,129 struct v4l2_subdev_mbus_code_enum *code);130int xvip_enum_frame_size(struct v4l2_subdev *subdev,131 struct v4l2_subdev_state *sd_state,132 struct v4l2_subdev_frame_size_enum *fse);133 134static inline u32 xvip_read(struct xvip_device *xvip, u32 addr)135{136 return ioread32(xvip->iomem + addr);137}138 139static inline void xvip_write(struct xvip_device *xvip, u32 addr, u32 value)140{141 iowrite32(value, xvip->iomem + addr);142}143 144static inline void xvip_clr(struct xvip_device *xvip, u32 addr, u32 clr)145{146 xvip_write(xvip, addr, xvip_read(xvip, addr) & ~clr);147}148 149static inline void xvip_set(struct xvip_device *xvip, u32 addr, u32 set)150{151 xvip_write(xvip, addr, xvip_read(xvip, addr) | set);152}153 154void xvip_clr_or_set(struct xvip_device *xvip, u32 addr, u32 mask, bool set);155void xvip_clr_and_set(struct xvip_device *xvip, u32 addr, u32 clr, u32 set);156 157int xvip_init_resources(struct xvip_device *xvip);158void xvip_cleanup_resources(struct xvip_device *xvip);159 160static inline void xvip_reset(struct xvip_device *xvip)161{162 xvip_write(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_SW_RESET);163}164 165static inline void xvip_start(struct xvip_device *xvip)166{167 xvip_set(xvip, XVIP_CTRL_CONTROL,168 XVIP_CTRL_CONTROL_SW_ENABLE | XVIP_CTRL_CONTROL_REG_UPDATE);169}170 171static inline void xvip_stop(struct xvip_device *xvip)172{173 xvip_clr(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_SW_ENABLE);174}175 176static inline void xvip_resume(struct xvip_device *xvip)177{178 xvip_write(xvip, XVIP_CTRL_CONTROL,179 xvip->saved_ctrl | XVIP_CTRL_CONTROL_SW_ENABLE);180}181 182static inline void xvip_suspend(struct xvip_device *xvip)183{184 xvip->saved_ctrl = xvip_read(xvip, XVIP_CTRL_CONTROL);185 xvip_write(xvip, XVIP_CTRL_CONTROL,186 xvip->saved_ctrl & ~XVIP_CTRL_CONTROL_SW_ENABLE);187}188 189static inline void xvip_set_frame_size(struct xvip_device *xvip,190 const struct v4l2_mbus_framefmt *format)191{192 xvip_write(xvip, XVIP_ACTIVE_SIZE,193 (format->height << XVIP_ACTIVE_VSIZE_SHIFT) |194 (format->width << XVIP_ACTIVE_HSIZE_SHIFT));195}196 197static inline void xvip_get_frame_size(struct xvip_device *xvip,198 struct v4l2_mbus_framefmt *format)199{200 u32 reg;201 202 reg = xvip_read(xvip, XVIP_ACTIVE_SIZE);203 format->width = (reg & XVIP_ACTIVE_HSIZE_MASK) >>204 XVIP_ACTIVE_HSIZE_SHIFT;205 format->height = (reg & XVIP_ACTIVE_VSIZE_MASK) >>206 XVIP_ACTIVE_VSIZE_SHIFT;207}208 209static inline void xvip_enable_reg_update(struct xvip_device *xvip)210{211 xvip_set(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_REG_UPDATE);212}213 214static inline void xvip_disable_reg_update(struct xvip_device *xvip)215{216 xvip_clr(xvip, XVIP_CTRL_CONTROL, XVIP_CTRL_CONTROL_REG_UPDATE);217}218 219static inline void xvip_print_version(struct xvip_device *xvip)220{221 u32 version;222 223 version = xvip_read(xvip, XVIP_CTRL_VERSION);224 225 dev_info(xvip->dev, "device found, version %u.%02x%x\n",226 ((version & XVIP_CTRL_VERSION_MAJOR_MASK) >>227 XVIP_CTRL_VERSION_MAJOR_SHIFT),228 ((version & XVIP_CTRL_VERSION_MINOR_MASK) >>229 XVIP_CTRL_VERSION_MINOR_SHIFT),230 ((version & XVIP_CTRL_VERSION_REVISION_MASK) >>231 XVIP_CTRL_VERSION_REVISION_SHIFT));232}233 234#endif /* __XILINX_VIP_H__ */235