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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * ImgTec IR Decoder found in PowerDown Controller.4 *5 * Copyright 2010-2014 Imagination Technologies Ltd.6 */7 8#ifndef _IMG_IR_H_9#define _IMG_IR_H_10 11#include <linux/io.h>12#include <linux/spinlock.h>13 14#include "img-ir-raw.h"15#include "img-ir-hw.h"16 17/* registers */18 19/* relative to the start of the IR block of registers */20#define IMG_IR_CONTROL 0x0021#define IMG_IR_STATUS 0x0422#define IMG_IR_DATA_LW 0x0823#define IMG_IR_DATA_UP 0x0c24#define IMG_IR_LEAD_SYMB_TIMING 0x1025#define IMG_IR_S00_SYMB_TIMING 0x1426#define IMG_IR_S01_SYMB_TIMING 0x1827#define IMG_IR_S10_SYMB_TIMING 0x1c28#define IMG_IR_S11_SYMB_TIMING 0x2029#define IMG_IR_FREE_SYMB_TIMING 0x2430#define IMG_IR_POW_MOD_PARAMS 0x2831#define IMG_IR_POW_MOD_ENABLE 0x2c32#define IMG_IR_IRQ_MSG_DATA_LW 0x3033#define IMG_IR_IRQ_MSG_DATA_UP 0x3434#define IMG_IR_IRQ_MSG_MASK_LW 0x3835#define IMG_IR_IRQ_MSG_MASK_UP 0x3c36#define IMG_IR_IRQ_ENABLE 0x4037#define IMG_IR_IRQ_STATUS 0x4438#define IMG_IR_IRQ_CLEAR 0x4839#define IMG_IR_IRCORE_ID 0xf040#define IMG_IR_CORE_REV 0xf441#define IMG_IR_CORE_DES1 0xf842#define IMG_IR_CORE_DES2 0xfc43 44 45/* field masks */46 47/* IMG_IR_CONTROL */48#define IMG_IR_DECODEN 0x4000000049#define IMG_IR_CODETYPE 0x3000000050#define IMG_IR_CODETYPE_SHIFT 2851#define IMG_IR_HDRTOG 0x0800000052#define IMG_IR_LDRDEC 0x0400000053#define IMG_IR_DECODINPOL 0x02000000 /* active high */54#define IMG_IR_BITORIEN 0x01000000 /* MSB first */55#define IMG_IR_D1VALIDSEL 0x0000800056#define IMG_IR_BITINV 0x00000040 /* don't invert */57#define IMG_IR_DECODEND2 0x0000001058#define IMG_IR_BITORIEND2 0x00000002 /* MSB first */59#define IMG_IR_BITINVD2 0x00000001 /* don't invert */60 61/* IMG_IR_STATUS */62#define IMG_IR_RXDVALD2 0x0000100063#define IMG_IR_IRRXD 0x0000040064#define IMG_IR_TOGSTATE 0x0000020065#define IMG_IR_RXDVAL 0x0000004066#define IMG_IR_RXDLEN 0x0000003f67#define IMG_IR_RXDLEN_SHIFT 068 69/* IMG_IR_LEAD_SYMB_TIMING, IMG_IR_Sxx_SYMB_TIMING */70#define IMG_IR_PD_MAX 0xff00000071#define IMG_IR_PD_MAX_SHIFT 2472#define IMG_IR_PD_MIN 0x00ff000073#define IMG_IR_PD_MIN_SHIFT 1674#define IMG_IR_W_MAX 0x0000ff0075#define IMG_IR_W_MAX_SHIFT 876#define IMG_IR_W_MIN 0x000000ff77#define IMG_IR_W_MIN_SHIFT 078 79/* IMG_IR_FREE_SYMB_TIMING */80#define IMG_IR_MAXLEN 0x0007e00081#define IMG_IR_MAXLEN_SHIFT 1382#define IMG_IR_MINLEN 0x00001f0083#define IMG_IR_MINLEN_SHIFT 884#define IMG_IR_FT_MIN 0x000000ff85#define IMG_IR_FT_MIN_SHIFT 086 87/* IMG_IR_POW_MOD_PARAMS */88#define IMG_IR_PERIOD_LEN 0x3f00000089#define IMG_IR_PERIOD_LEN_SHIFT 2490#define IMG_IR_PERIOD_DUTY 0x003f000091#define IMG_IR_PERIOD_DUTY_SHIFT 1692#define IMG_IR_STABLE_STOP 0x00003f0093#define IMG_IR_STABLE_STOP_SHIFT 894#define IMG_IR_STABLE_START 0x0000003f95#define IMG_IR_STABLE_START_SHIFT 096 97/* IMG_IR_POW_MOD_ENABLE */98#define IMG_IR_POWER_OUT_EN 0x0000000299#define IMG_IR_POWER_MOD_EN 0x00000001100 101/* IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_STATUS, IMG_IR_IRQ_CLEAR */102#define IMG_IR_IRQ_DEC2_ERR 0x00000080103#define IMG_IR_IRQ_DEC_ERR 0x00000040104#define IMG_IR_IRQ_ACT_LEVEL 0x00000020105#define IMG_IR_IRQ_FALL_EDGE 0x00000010106#define IMG_IR_IRQ_RISE_EDGE 0x00000008107#define IMG_IR_IRQ_DATA_MATCH 0x00000004108#define IMG_IR_IRQ_DATA2_VALID 0x00000002109#define IMG_IR_IRQ_DATA_VALID 0x00000001110#define IMG_IR_IRQ_ALL 0x000000ff111#define IMG_IR_IRQ_EDGE (IMG_IR_IRQ_FALL_EDGE | IMG_IR_IRQ_RISE_EDGE)112 113/* IMG_IR_CORE_ID */114#define IMG_IR_CORE_ID 0x00ff0000115#define IMG_IR_CORE_ID_SHIFT 16116#define IMG_IR_CORE_CONFIG 0x0000ffff117#define IMG_IR_CORE_CONFIG_SHIFT 0118 119/* IMG_IR_CORE_REV */120#define IMG_IR_DESIGNER 0xff000000121#define IMG_IR_DESIGNER_SHIFT 24122#define IMG_IR_MAJOR_REV 0x00ff0000123#define IMG_IR_MAJOR_REV_SHIFT 16124#define IMG_IR_MINOR_REV 0x0000ff00125#define IMG_IR_MINOR_REV_SHIFT 8126#define IMG_IR_MAINT_REV 0x000000ff127#define IMG_IR_MAINT_REV_SHIFT 0128 129struct device;130struct clk;131 132/**133 * struct img_ir_priv - Private driver data.134 * @dev: Platform device.135 * @irq: IRQ number.136 * @clk: Input clock.137 * @sys_clk: System clock.138 * @reg_base: Iomem base address of IR register block.139 * @lock: Protects IR registers and variables in this struct.140 * @raw: Driver data for raw decoder.141 * @hw: Driver data for hardware decoder.142 */143struct img_ir_priv {144 struct device *dev;145 int irq;146 struct clk *clk;147 struct clk *sys_clk;148 void __iomem *reg_base;149 spinlock_t lock;150 151 struct img_ir_priv_raw raw;152 struct img_ir_priv_hw hw;153};154 155/* Hardware access */156 157static inline void img_ir_write(struct img_ir_priv *priv,158 unsigned int reg_offs, unsigned int data)159{160 iowrite32(data, priv->reg_base + reg_offs);161}162 163static inline unsigned int img_ir_read(struct img_ir_priv *priv,164 unsigned int reg_offs)165{166 return ioread32(priv->reg_base + reg_offs);167}168 169#endif /* _IMG_IR_H_ */170