430 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Driver for Allwinner sunXi IR controller4 *5 * Copyright (C) 2014 Alexsey Shestacov <wingrime@linux-sunxi.org>6 * Copyright (C) 2014 Alexander Bersenev <bay@hackerdom.ru>7 *8 * Based on sun5i-ir.c:9 * Copyright (C) 2007-2012 Daniel Wang10 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>11 */12 13#include <linux/clk.h>14#include <linux/interrupt.h>15#include <linux/io.h>16#include <linux/module.h>17#include <linux/of.h>18#include <linux/platform_device.h>19#include <linux/reset.h>20#include <media/rc-core.h>21 22#define SUNXI_IR_DEV "sunxi-ir"23 24/* Registers */25/* IR Control */26#define SUNXI_IR_CTL_REG 0x0027/* Global Enable */28#define REG_CTL_GEN BIT(0)29/* RX block enable */30#define REG_CTL_RXEN BIT(1)31/* CIR mode */32#define REG_CTL_MD (BIT(4) | BIT(5))33 34/* Rx Config */35#define SUNXI_IR_RXCTL_REG 0x1036/* Pulse Polarity Invert flag */37#define REG_RXCTL_RPPI BIT(2)38 39/* Rx Data */40#define SUNXI_IR_RXFIFO_REG 0x2041 42/* Rx Interrupt Enable */43#define SUNXI_IR_RXINT_REG 0x2C44/* Rx FIFO Overflow Interrupt Enable */45#define REG_RXINT_ROI_EN BIT(0)46/* Rx Packet End Interrupt Enable */47#define REG_RXINT_RPEI_EN BIT(1)48/* Rx FIFO Data Available Interrupt Enable */49#define REG_RXINT_RAI_EN BIT(4)50 51/* Rx FIFO available byte level */52#define REG_RXINT_RAL(val) ((val) << 8)53 54/* Rx Interrupt Status */55#define SUNXI_IR_RXSTA_REG 0x3056/* Rx FIFO Overflow */57#define REG_RXSTA_ROI REG_RXINT_ROI_EN58/* Rx Packet End */59#define REG_RXSTA_RPE REG_RXINT_RPEI_EN60/* Rx FIFO Data Available */61#define REG_RXSTA_RA REG_RXINT_RAI_EN62/* RX FIFO Get Available Counter */63#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))64/* Clear all interrupt status value */65#define REG_RXSTA_CLEARALL 0xff66 67/* IR Sample Config */68#define SUNXI_IR_CIR_REG 0x3469/* CIR_REG register noise threshold */70#define REG_CIR_NTHR(val) (((val) << 2) & (GENMASK(7, 2)))71/* CIR_REG register idle threshold */72#define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8)))73 74/* Required frequency for IR0 or IR1 clock in CIR mode (default) */75#define SUNXI_IR_BASE_CLK 800000076/* Noise threshold in samples */77#define SUNXI_IR_RXNOISE 178 79/**80 * struct sunxi_ir_quirks - Differences between SoC variants.81 *82 * @has_reset: SoC needs reset deasserted.83 * @fifo_size: size of the fifo.84 */85struct sunxi_ir_quirks {86 bool has_reset;87 int fifo_size;88};89 90struct sunxi_ir {91 struct rc_dev *rc;92 void __iomem *base;93 int irq;94 int fifo_size;95 struct clk *clk;96 struct clk *apb_clk;97 struct reset_control *rst;98 const char *map_name;99};100 101static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)102{103 unsigned long status;104 unsigned char dt;105 unsigned int cnt, rc;106 struct sunxi_ir *ir = dev_id;107 struct ir_raw_event rawir = {};108 109 status = readl(ir->base + SUNXI_IR_RXSTA_REG);110 111 /* clean all pending statuses */112 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);113 114 if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) {115 /* How many messages in fifo */116 rc = REG_RXSTA_GET_AC(status);117 /* Sanity check */118 rc = rc > ir->fifo_size ? ir->fifo_size : rc;119 /* If we have data */120 for (cnt = 0; cnt < rc; cnt++) {121 /* for each bit in fifo */122 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);123 rawir.pulse = (dt & 0x80) != 0;124 rawir.duration = ((dt & 0x7f) + 1) *125 ir->rc->rx_resolution;126 ir_raw_event_store_with_filter(ir->rc, &rawir);127 }128 }129 130 if (status & REG_RXSTA_ROI) {131 ir_raw_event_overflow(ir->rc);132 } else if (status & REG_RXSTA_RPE) {133 ir_raw_event_set_idle(ir->rc, true);134 ir_raw_event_handle(ir->rc);135 } else {136 ir_raw_event_handle(ir->rc);137 }138 139 return IRQ_HANDLED;140}141 142/* Convert idle threshold to usec */143static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr)144{145 return DIV_ROUND_CLOSEST(USEC_PER_SEC * (ithr + 1),146 base_clk / (128 * 64));147}148 149/* Convert usec to idle threshold */150static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec)151{152 /* make sure we don't end up with a timeout less than requested */153 return DIV_ROUND_UP((base_clk / (128 * 64)) * usec, USEC_PER_SEC) - 1;154}155 156static int sunxi_ir_set_timeout(struct rc_dev *rc_dev, unsigned int timeout)157{158 struct sunxi_ir *ir = rc_dev->priv;159 unsigned int base_clk = clk_get_rate(ir->clk);160 161 unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout);162 163 dev_dbg(rc_dev->dev.parent, "setting idle threshold to %u\n", ithr);164 165 /* Set noise threshold and idle threshold */166 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE) | REG_CIR_ITHR(ithr),167 ir->base + SUNXI_IR_CIR_REG);168 169 rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr);170 171 return 0;172}173 174static int sunxi_ir_hw_init(struct device *dev)175{176 struct sunxi_ir *ir = dev_get_drvdata(dev);177 u32 tmp;178 int ret;179 180 ret = reset_control_deassert(ir->rst);181 if (ret)182 return ret;183 184 ret = clk_prepare_enable(ir->apb_clk);185 if (ret) {186 dev_err(dev, "failed to enable apb clk\n");187 goto exit_assert_reset;188 }189 190 ret = clk_prepare_enable(ir->clk);191 if (ret) {192 dev_err(dev, "failed to enable ir clk\n");193 goto exit_disable_apb_clk;194 }195 196 /* Enable CIR Mode */197 writel(REG_CTL_MD, ir->base + SUNXI_IR_CTL_REG);198 199 /* Set noise threshold and idle threshold */200 sunxi_ir_set_timeout(ir->rc, ir->rc->timeout);201 202 /* Invert Input Signal */203 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG);204 205 /* Clear All Rx Interrupt Status */206 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);207 208 /*209 * Enable IRQ on overflow, packet end, FIFO available with trigger210 * level211 */212 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN |213 REG_RXINT_RAI_EN | REG_RXINT_RAL(ir->fifo_size / 2 - 1),214 ir->base + SUNXI_IR_RXINT_REG);215 216 /* Enable IR Module */217 tmp = readl(ir->base + SUNXI_IR_CTL_REG);218 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG);219 220 return 0;221 222exit_disable_apb_clk:223 clk_disable_unprepare(ir->apb_clk);224exit_assert_reset:225 reset_control_assert(ir->rst);226 227 return ret;228}229 230static void sunxi_ir_hw_exit(struct device *dev)231{232 struct sunxi_ir *ir = dev_get_drvdata(dev);233 234 clk_disable_unprepare(ir->clk);235 clk_disable_unprepare(ir->apb_clk);236 reset_control_assert(ir->rst);237}238 239static int __maybe_unused sunxi_ir_suspend(struct device *dev)240{241 sunxi_ir_hw_exit(dev);242 243 return 0;244}245 246static int __maybe_unused sunxi_ir_resume(struct device *dev)247{248 return sunxi_ir_hw_init(dev);249}250 251static SIMPLE_DEV_PM_OPS(sunxi_ir_pm_ops, sunxi_ir_suspend, sunxi_ir_resume);252 253static int sunxi_ir_probe(struct platform_device *pdev)254{255 int ret = 0;256 257 struct device *dev = &pdev->dev;258 struct device_node *dn = dev->of_node;259 const struct sunxi_ir_quirks *quirks;260 struct sunxi_ir *ir;261 u32 b_clk_freq = SUNXI_IR_BASE_CLK;262 263 ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);264 if (!ir)265 return -ENOMEM;266 267 quirks = of_device_get_match_data(&pdev->dev);268 if (!quirks) {269 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");270 return -ENODEV;271 }272 273 ir->fifo_size = quirks->fifo_size;274 275 /* Clock */276 ir->apb_clk = devm_clk_get(dev, "apb");277 if (IS_ERR(ir->apb_clk)) {278 dev_err(dev, "failed to get a apb clock.\n");279 return PTR_ERR(ir->apb_clk);280 }281 ir->clk = devm_clk_get(dev, "ir");282 if (IS_ERR(ir->clk)) {283 dev_err(dev, "failed to get a ir clock.\n");284 return PTR_ERR(ir->clk);285 }286 287 /* Base clock frequency (optional) */288 of_property_read_u32(dn, "clock-frequency", &b_clk_freq);289 290 /* Reset */291 if (quirks->has_reset) {292 ir->rst = devm_reset_control_get_exclusive(dev, NULL);293 if (IS_ERR(ir->rst))294 return PTR_ERR(ir->rst);295 }296 297 ret = clk_set_rate(ir->clk, b_clk_freq);298 if (ret) {299 dev_err(dev, "set ir base clock failed!\n");300 return ret;301 }302 dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);303 304 /* IO */305 ir->base = devm_platform_ioremap_resource(pdev, 0);306 if (IS_ERR(ir->base)) {307 return PTR_ERR(ir->base);308 }309 310 ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);311 if (!ir->rc) {312 dev_err(dev, "failed to allocate device\n");313 return -ENOMEM;314 }315 316 ir->rc->priv = ir;317 ir->rc->device_name = SUNXI_IR_DEV;318 ir->rc->input_phys = "sunxi-ir/input0";319 ir->rc->input_id.bustype = BUS_HOST;320 ir->rc->input_id.vendor = 0x0001;321 ir->rc->input_id.product = 0x0001;322 ir->rc->input_id.version = 0x0100;323 ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);324 ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;325 ir->rc->dev.parent = dev;326 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;327 /* Frequency after IR internal divider with sample period in us */328 ir->rc->rx_resolution = (USEC_PER_SEC / (b_clk_freq / 64));329 ir->rc->timeout = IR_DEFAULT_TIMEOUT;330 ir->rc->min_timeout = sunxi_ithr_to_usec(b_clk_freq, 0);331 ir->rc->max_timeout = sunxi_ithr_to_usec(b_clk_freq, 255);332 ir->rc->s_timeout = sunxi_ir_set_timeout;333 ir->rc->driver_name = SUNXI_IR_DEV;334 335 ret = rc_register_device(ir->rc);336 if (ret) {337 dev_err(dev, "failed to register rc device\n");338 goto exit_free_dev;339 }340 341 platform_set_drvdata(pdev, ir);342 343 /* IRQ */344 ir->irq = platform_get_irq(pdev, 0);345 if (ir->irq < 0) {346 ret = ir->irq;347 goto exit_free_dev;348 }349 350 ret = devm_request_irq(dev, ir->irq, sunxi_ir_irq, 0, SUNXI_IR_DEV, ir);351 if (ret) {352 dev_err(dev, "failed request irq\n");353 goto exit_free_dev;354 }355 356 ret = sunxi_ir_hw_init(dev);357 if (ret)358 goto exit_free_dev;359 360 dev_info(dev, "initialized sunXi IR driver\n");361 return 0;362 363exit_free_dev:364 rc_free_device(ir->rc);365 366 return ret;367}368 369static void sunxi_ir_remove(struct platform_device *pdev)370{371 struct sunxi_ir *ir = platform_get_drvdata(pdev);372 373 rc_unregister_device(ir->rc);374 sunxi_ir_hw_exit(&pdev->dev);375}376 377static void sunxi_ir_shutdown(struct platform_device *pdev)378{379 sunxi_ir_hw_exit(&pdev->dev);380}381 382static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = {383 .has_reset = false,384 .fifo_size = 16,385};386 387static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = {388 .has_reset = false,389 .fifo_size = 64,390};391 392static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = {393 .has_reset = true,394 .fifo_size = 64,395};396 397static const struct of_device_id sunxi_ir_match[] = {398 {399 .compatible = "allwinner,sun4i-a10-ir",400 .data = &sun4i_a10_ir_quirks,401 },402 {403 .compatible = "allwinner,sun5i-a13-ir",404 .data = &sun5i_a13_ir_quirks,405 },406 {407 .compatible = "allwinner,sun6i-a31-ir",408 .data = &sun6i_a31_ir_quirks,409 },410 {}411};412MODULE_DEVICE_TABLE(of, sunxi_ir_match);413 414static struct platform_driver sunxi_ir_driver = {415 .probe = sunxi_ir_probe,416 .remove_new = sunxi_ir_remove,417 .shutdown = sunxi_ir_shutdown,418 .driver = {419 .name = SUNXI_IR_DEV,420 .of_match_table = sunxi_ir_match,421 .pm = &sunxi_ir_pm_ops,422 },423};424 425module_platform_driver(sunxi_ir_driver);426 427MODULE_DESCRIPTION("Allwinner sunXi IR controller driver");428MODULE_AUTHOR("Alexsey Shestacov <wingrime@linux-sunxi.org>");429MODULE_LICENSE("GPL");430