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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * GS1662 device registration.4 *5 * Copyright (C) 2015-2016 Nexvision6 * Author: Charles-Antoine Couret <charles-antoine.couret@nexvision.fr>7 */8 9#include <linux/kernel.h>10#include <linux/init.h>11#include <linux/spi/spi.h>12#include <linux/platform_device.h>13#include <linux/ctype.h>14#include <linux/err.h>15#include <linux/device.h>16#include <linux/module.h>17 18#include <linux/videodev2.h>19#include <media/v4l2-common.h>20#include <media/v4l2-ctrls.h>21#include <media/v4l2-device.h>22#include <media/v4l2-subdev.h>23#include <media/v4l2-dv-timings.h>24#include <linux/v4l2-dv-timings.h>25 26#define REG_STATUS 0x0427#define REG_FORCE_FMT 0x0628#define REG_LINES_PER_FRAME 0x1229#define REG_WORDS_PER_LINE 0x1330#define REG_WORDS_PER_ACT_LINE 0x1431#define REG_ACT_LINES_PER_FRAME 0x1532 33#define MASK_H_LOCK 0x00134#define MASK_V_LOCK 0x00235#define MASK_STD_LOCK 0x00436#define MASK_FORCE_STD 0x02037#define MASK_STD_STATUS 0x3E038 39#define GS_WIDTH_MIN 72040#define GS_WIDTH_MAX 204841#define GS_HEIGHT_MIN 48742#define GS_HEIGHT_MAX 108043#define GS_PIXELCLOCK_MIN 1051920044#define GS_PIXELCLOCK_MAX 7425000045 46struct gs {47 struct spi_device *pdev;48 struct v4l2_subdev sd;49 struct v4l2_dv_timings current_timings;50 int enabled;51};52 53struct gs_reg_fmt {54 u16 reg_value;55 struct v4l2_dv_timings format;56};57 58static const struct spi_device_id gs_id[] = {59 { "gs1662", 0 },60 { }61};62MODULE_DEVICE_TABLE(spi, gs_id);63 64static const struct v4l2_dv_timings fmt_cap[] = {65 V4L2_DV_BT_SDI_720X487I60,66 V4L2_DV_BT_CEA_720X576P50,67 V4L2_DV_BT_CEA_1280X720P24,68 V4L2_DV_BT_CEA_1280X720P25,69 V4L2_DV_BT_CEA_1280X720P30,70 V4L2_DV_BT_CEA_1280X720P50,71 V4L2_DV_BT_CEA_1280X720P60,72 V4L2_DV_BT_CEA_1920X1080P24,73 V4L2_DV_BT_CEA_1920X1080P25,74 V4L2_DV_BT_CEA_1920X1080P30,75 V4L2_DV_BT_CEA_1920X1080I50,76 V4L2_DV_BT_CEA_1920X1080I60,77};78 79static const struct gs_reg_fmt reg_fmt[] = {80 { 0x00, V4L2_DV_BT_CEA_1280X720P60 },81 { 0x01, V4L2_DV_BT_CEA_1280X720P60 },82 { 0x02, V4L2_DV_BT_CEA_1280X720P30 },83 { 0x03, V4L2_DV_BT_CEA_1280X720P30 },84 { 0x04, V4L2_DV_BT_CEA_1280X720P50 },85 { 0x05, V4L2_DV_BT_CEA_1280X720P50 },86 { 0x06, V4L2_DV_BT_CEA_1280X720P25 },87 { 0x07, V4L2_DV_BT_CEA_1280X720P25 },88 { 0x08, V4L2_DV_BT_CEA_1280X720P24 },89 { 0x09, V4L2_DV_BT_CEA_1280X720P24 },90 { 0x0A, V4L2_DV_BT_CEA_1920X1080I60 },91 { 0x0B, V4L2_DV_BT_CEA_1920X1080P30 },92 93 /* Default value: keep this field before 0xC */94 { 0x14, V4L2_DV_BT_CEA_1920X1080I50 },95 { 0x0C, V4L2_DV_BT_CEA_1920X1080I50 },96 { 0x0D, V4L2_DV_BT_CEA_1920X1080P25 },97 { 0x0E, V4L2_DV_BT_CEA_1920X1080P25 },98 { 0x10, V4L2_DV_BT_CEA_1920X1080P24 },99 { 0x12, V4L2_DV_BT_CEA_1920X1080P24 },100 { 0x16, V4L2_DV_BT_SDI_720X487I60 },101 { 0x19, V4L2_DV_BT_SDI_720X487I60 },102 { 0x18, V4L2_DV_BT_CEA_720X576P50 },103 { 0x1A, V4L2_DV_BT_CEA_720X576P50 },104 105 /* Implement following timings before enable it.106 * Because of we don't have access to these theoretical timings yet.107 * Workaround: use functions to get and set registers for these formats.108 */109#if 0110 { 0x0F, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */111 { 0x11, V4L2_DV_BT_XXX_1920X1080I24 }, /* SMPTE 274M */112 { 0x13, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */113 { 0x15, V4L2_DV_BT_XXX_1920X1035I60 }, /* SMPTE 260M */114 { 0x17, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */115 { 0x1B, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */116 { 0x1C, V4L2_DV_BT_XXX_2048X1080P25 }, /* SMPTE 428.1M */117#endif118};119 120static const struct v4l2_dv_timings_cap gs_timings_cap = {121 .type = V4L2_DV_BT_656_1120,122 /* keep this initialization for compatibility with GCC < 4.4.6 */123 .reserved = { 0 },124 V4L2_INIT_BT_TIMINGS(GS_WIDTH_MIN, GS_WIDTH_MAX, GS_HEIGHT_MIN,125 GS_HEIGHT_MAX, GS_PIXELCLOCK_MIN,126 GS_PIXELCLOCK_MAX,127 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI,128 V4L2_DV_BT_CAP_PROGRESSIVE129 | V4L2_DV_BT_CAP_INTERLACED)130};131 132static int gs_read_register(struct spi_device *spi, u16 addr, u16 *value)133{134 int ret;135 u16 buf_addr = (0x8000 | (0x0FFF & addr));136 u16 buf_value = 0;137 struct spi_message msg;138 struct spi_transfer tx[] = {139 {140 .tx_buf = &buf_addr,141 .len = 2,142 .delay = {143 .value = 1,144 .unit = SPI_DELAY_UNIT_USECS145 },146 }, {147 .rx_buf = &buf_value,148 .len = 2,149 .delay = {150 .value = 1,151 .unit = SPI_DELAY_UNIT_USECS152 },153 },154 };155 156 spi_message_init(&msg);157 spi_message_add_tail(&tx[0], &msg);158 spi_message_add_tail(&tx[1], &msg);159 ret = spi_sync(spi, &msg);160 161 *value = buf_value;162 163 return ret;164}165 166static int gs_write_register(struct spi_device *spi, u16 addr, u16 value)167{168 int ret;169 u16 buf_addr = addr;170 u16 buf_value = value;171 struct spi_message msg;172 struct spi_transfer tx[] = {173 {174 .tx_buf = &buf_addr,175 .len = 2,176 .delay = {177 .value = 1,178 .unit = SPI_DELAY_UNIT_USECS179 },180 }, {181 .tx_buf = &buf_value,182 .len = 2,183 .delay = {184 .value = 1,185 .unit = SPI_DELAY_UNIT_USECS186 },187 },188 };189 190 spi_message_init(&msg);191 spi_message_add_tail(&tx[0], &msg);192 spi_message_add_tail(&tx[1], &msg);193 ret = spi_sync(spi, &msg);194 195 return ret;196}197 198#ifdef CONFIG_VIDEO_ADV_DEBUG199static int gs_g_register(struct v4l2_subdev *sd,200 struct v4l2_dbg_register *reg)201{202 struct spi_device *spi = v4l2_get_subdevdata(sd);203 u16 val;204 int ret;205 206 ret = gs_read_register(spi, reg->reg & 0xFFFF, &val);207 reg->val = val;208 reg->size = 2;209 return ret;210}211 212static int gs_s_register(struct v4l2_subdev *sd,213 const struct v4l2_dbg_register *reg)214{215 struct spi_device *spi = v4l2_get_subdevdata(sd);216 217 return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF);218}219#endif220 221static int gs_status_format(u16 status, struct v4l2_dv_timings *timings)222{223 int std = (status & MASK_STD_STATUS) >> 5;224 int i;225 226 for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) {227 if (reg_fmt[i].reg_value == std) {228 *timings = reg_fmt[i].format;229 return 0;230 }231 }232 233 return -ERANGE;234}235 236static u16 get_register_timings(struct v4l2_dv_timings *timings)237{238 int i;239 240 for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) {241 if (v4l2_match_dv_timings(timings, ®_fmt[i].format, 0,242 false))243 return reg_fmt[i].reg_value | MASK_FORCE_STD;244 }245 246 return 0x0;247}248 249static inline struct gs *to_gs(struct v4l2_subdev *sd)250{251 return container_of(sd, struct gs, sd);252}253 254static int gs_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,255 struct v4l2_dv_timings *timings)256{257 struct gs *gs = to_gs(sd);258 int reg_value;259 260 if (pad != 0)261 return -EINVAL;262 263 reg_value = get_register_timings(timings);264 if (reg_value == 0x0)265 return -EINVAL;266 267 gs->current_timings = *timings;268 return 0;269}270 271static int gs_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,272 struct v4l2_dv_timings *timings)273{274 struct gs *gs = to_gs(sd);275 276 if (pad != 0)277 return -EINVAL;278 279 *timings = gs->current_timings;280 return 0;281}282 283static int gs_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,284 struct v4l2_dv_timings *timings)285{286 struct gs *gs = to_gs(sd);287 struct v4l2_dv_timings fmt;288 u16 reg_value, i;289 int ret;290 291 if (pad != 0)292 return -EINVAL;293 294 if (gs->enabled)295 return -EBUSY;296 297 /*298 * Check if the component detect a line, a frame or something else299 * which looks like a video signal activity.300 */301 for (i = 0; i < 4; i++) {302 gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, ®_value);303 if (reg_value)304 break;305 }306 307 /* If no register reports a video signal */308 if (i >= 4)309 return -ENOLINK;310 311 gs_read_register(gs->pdev, REG_STATUS, ®_value);312 if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK))313 return -ENOLCK;314 if (!(reg_value & MASK_STD_LOCK))315 return -ERANGE;316 317 ret = gs_status_format(reg_value, &fmt);318 319 if (ret < 0)320 return ret;321 322 *timings = fmt;323 return 0;324}325 326static int gs_enum_dv_timings(struct v4l2_subdev *sd,327 struct v4l2_enum_dv_timings *timings)328{329 if (timings->index >= ARRAY_SIZE(fmt_cap))330 return -EINVAL;331 332 if (timings->pad != 0)333 return -EINVAL;334 335 timings->timings = fmt_cap[timings->index];336 return 0;337}338 339static int gs_s_stream(struct v4l2_subdev *sd, int enable)340{341 struct gs *gs = to_gs(sd);342 int reg_value;343 344 if (gs->enabled == enable)345 return 0;346 347 gs->enabled = enable;348 349 if (enable) {350 /* To force the specific format */351 reg_value = get_register_timings(&gs->current_timings);352 return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value);353 }354 355 /* To renable auto-detection mode */356 return gs_write_register(gs->pdev, REG_FORCE_FMT, 0x0);357}358 359static int gs_g_input_status(struct v4l2_subdev *sd, u32 *status)360{361 struct gs *gs = to_gs(sd);362 u16 reg_value, i;363 int ret;364 365 /*366 * Check if the component detect a line, a frame or something else367 * which looks like a video signal activity.368 */369 for (i = 0; i < 4; i++) {370 ret = gs_read_register(gs->pdev,371 REG_LINES_PER_FRAME + i, ®_value);372 if (reg_value)373 break;374 if (ret) {375 *status = V4L2_IN_ST_NO_POWER;376 return ret;377 }378 }379 380 /* If no register reports a video signal */381 if (i >= 4)382 *status |= V4L2_IN_ST_NO_SIGNAL;383 384 ret = gs_read_register(gs->pdev, REG_STATUS, ®_value);385 if (!(reg_value & MASK_H_LOCK))386 *status |= V4L2_IN_ST_NO_H_LOCK;387 if (!(reg_value & MASK_V_LOCK))388 *status |= V4L2_IN_ST_NO_V_LOCK;389 if (!(reg_value & MASK_STD_LOCK))390 *status |= V4L2_IN_ST_NO_STD_LOCK;391 392 return ret;393}394 395static int gs_dv_timings_cap(struct v4l2_subdev *sd,396 struct v4l2_dv_timings_cap *cap)397{398 if (cap->pad != 0)399 return -EINVAL;400 401 *cap = gs_timings_cap;402 return 0;403}404 405/* V4L2 core operation handlers */406static const struct v4l2_subdev_core_ops gs_core_ops = {407#ifdef CONFIG_VIDEO_ADV_DEBUG408 .g_register = gs_g_register,409 .s_register = gs_s_register,410#endif411};412 413static const struct v4l2_subdev_video_ops gs_video_ops = {414 .s_stream = gs_s_stream,415 .g_input_status = gs_g_input_status,416};417 418static const struct v4l2_subdev_pad_ops gs_pad_ops = {419 .s_dv_timings = gs_s_dv_timings,420 .g_dv_timings = gs_g_dv_timings,421 .query_dv_timings = gs_query_dv_timings,422 .enum_dv_timings = gs_enum_dv_timings,423 .dv_timings_cap = gs_dv_timings_cap,424};425 426/* V4L2 top level operation handlers */427static const struct v4l2_subdev_ops gs_ops = {428 .core = &gs_core_ops,429 .video = &gs_video_ops,430 .pad = &gs_pad_ops,431};432 433static int gs_probe(struct spi_device *spi)434{435 int ret;436 struct gs *gs;437 struct v4l2_subdev *sd;438 439 gs = devm_kzalloc(&spi->dev, sizeof(struct gs), GFP_KERNEL);440 if (!gs)441 return -ENOMEM;442 443 gs->pdev = spi;444 sd = &gs->sd;445 446 spi->mode = SPI_MODE_0;447 spi->irq = -1;448 spi->max_speed_hz = 10000000;449 spi->bits_per_word = 16;450 ret = spi_setup(spi);451 v4l2_spi_subdev_init(sd, spi, &gs_ops);452 453 gs->current_timings = reg_fmt[0].format;454 gs->enabled = 0;455 456 /* Set H_CONFIG to SMPTE timings */457 gs_write_register(spi, 0x0, 0x300);458 459 return ret;460}461 462static void gs_remove(struct spi_device *spi)463{464 struct v4l2_subdev *sd = spi_get_drvdata(spi);465 466 v4l2_device_unregister_subdev(sd);467}468 469static struct spi_driver gs_driver = {470 .driver = {471 .name = "gs1662",472 },473 474 .probe = gs_probe,475 .remove = gs_remove,476 .id_table = gs_id,477};478 479module_spi_driver(gs_driver);480 481MODULE_LICENSE("GPL");482MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@nexvision.fr>");483MODULE_DESCRIPTION("Gennum GS1662 HD/SD-SDI Serializer driver");484