1553 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 cx231xx-reg.h - driver for Conexant Cx23100/101/1024 USB video capture devices5 6 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>7 8 */9 10#ifndef _CX231XX_REG_H11#define _CX231XX_REG_H12 13/*****************************************************************************14 * VBI codes *15*****************************************************************************/16 17#define SAV_ACTIVE_VIDEO_FIELD1 0x8018#define EAV_ACTIVE_VIDEO_FIELD1 0x9019 20#define SAV_ACTIVE_VIDEO_FIELD2 0xc021#define EAV_ACTIVE_VIDEO_FIELD2 0xd022 23#define SAV_VBLANK_FIELD1 0xa024#define EAV_VBLANK_FIELD1 0xb025 26#define SAV_VBLANK_FIELD2 0xe027#define EAV_VBLANK_FIELD2 0xf028 29#define SAV_VBI_FIELD1 0x2030#define EAV_VBI_FIELD1 0x3031 32#define SAV_VBI_FIELD2 0x6033#define EAV_VBI_FIELD2 0x7034 35/*****************************************************************************/36/* Audio ADC Registers */37#define CH_PWR_CTRL1 0x0000000e38#define CH_PWR_CTRL2 0x0000000f39/*****************************************************************************/40 41#define HOST_REG1 0x00042#define FLD_FORCE_CHIP_SEL 0x8043#define FLD_AUTO_INC_DIS 0x2044#define FLD_PREFETCH_EN 0x1045/* Reserved [2:3] */46#define FLD_DIGITAL_PWR_DN 0x0247#define FLD_SLEEP 0x0148 49/*****************************************************************************/50#define HOST_REG2 0x00151 52/*****************************************************************************/53#define HOST_REG3 0x00254 55/*****************************************************************************/56/* added for polaris */57#define GPIO_PIN_CTL0 0x358#define GPIO_PIN_CTL1 0x459#define GPIO_PIN_CTL2 0x560#define GPIO_PIN_CTL3 0x661#define TS1_PIN_CTL0 0x762#define TS1_PIN_CTL1 0x863/*****************************************************************************/64 65#define FLD_CLK_IN_EN 0x8066#define FLD_XTAL_CTRL 0x7067#define FLD_BB_CLK_MODE 0x0C68#define FLD_REF_DIV_PLL 0x0269#define FLD_REF_SEL_PLL1 0x0170 71/*****************************************************************************/72#define CHIP_CTRL 0x10073/* Reserved [27] */74/* Reserved [31:21] */75#define FLD_CHIP_ACFG_DIS 0x0010000076/* Reserved [19] */77#define FLD_DUAL_MODE_ADC2 0x0004000078#define FLD_SIF_EN 0x0002000079#define FLD_SOFT_RST 0x0001000080#define FLD_DEVICE_ID 0x0000ffff81 82/*****************************************************************************/83#define AFE_CTRL 0x10484#define AFE_CTRL_C2HH_SRC_CTRL 0x10485#define FLD_DIF_OUT_SEL 0xc000000086#define FLD_AUX_PLL_CLK_ALT_SEL 0x3c00000087#define FLD_UV_ORDER_MODE 0x0200000088#define FLD_FUNC_MODE 0x0180000089#define FLD_ROT1_PHASE_CTL 0x007f800090#define FLD_AUD_IN_SEL 0x0000400091#define FLD_LUMA_IN_SEL 0x0000200092#define FLD_CHROMA_IN_SEL 0x0000100093/* reserve [11:10] */94#define FLD_INV_SPEC_DIS 0x0000020095#define FLD_VGA_SEL_CH3 0x0000010096#define FLD_VGA_SEL_CH2 0x0000008097#define FLD_VGA_SEL_CH1 0x0000004098#define FLD_DCR_BYP_CH1 0x0000002099#define FLD_DCR_BYP_CH2 0x00000010100#define FLD_DCR_BYP_CH3 0x00000008101#define FLD_EN_12DB_CH3 0x00000004102#define FLD_EN_12DB_CH2 0x00000002103#define FLD_EN_12DB_CH1 0x00000001104 105/* redefine in Cx231xx */106/*****************************************************************************/107#define DC_CTRL1 0x108108/* reserve [31:30] */109#define FLD_CLAMP_LVL_CH1 0x3fff8000110#define FLD_CLAMP_LVL_CH2 0x00007fff111/*****************************************************************************/112 113/*****************************************************************************/114#define DC_CTRL2 0x10c115/* reserve [31:28] */116#define FLD_CLAMP_LVL_CH3 0x00fffe00117#define FLD_CLAMP_WIND_LENTH 0x000001e0118#define FLD_C2HH_SAT_MIN 0x0000001e119#define FLD_FLT_BYP_SEL 0x00000001120/*****************************************************************************/121 122/*****************************************************************************/123#define DC_CTRL3 0x110124/* reserve [31:16] */125#define FLD_ERR_GAIN_CTL 0x00070000126#define FLD_LPF_MIN 0x0000ffff127/*****************************************************************************/128 129/*****************************************************************************/130#define DC_CTRL4 0x114131/* reserve [31:31] */132#define FLD_INTG_CH1 0x7fffffff133/*****************************************************************************/134 135/*****************************************************************************/136#define DC_CTRL5 0x118137/* reserve [31:31] */138#define FLD_INTG_CH2 0x7fffffff139/*****************************************************************************/140 141/*****************************************************************************/142#define DC_CTRL6 0x11c143/* reserve [31:31] */144#define FLD_INTG_CH3 0x7fffffff145/*****************************************************************************/146 147/*****************************************************************************/148#define PIN_CTRL 0x120149#define FLD_OEF_AGC_RF 0x00000001150#define FLD_OEF_AGC_IFVGA 0x00000002151#define FLD_OEF_AGC_IF 0x00000004152#define FLD_REG_BO_PUD 0x80000000153#define FLD_IR_IRQ_STAT 0x40000000154#define FLD_AUD_IRQ_STAT 0x20000000155#define FLD_VID_IRQ_STAT 0x10000000156/* Reserved [27:26] */157#define FLD_IRQ_N_OUT_EN 0x02000000158#define FLD_IRQ_N_POLAR 0x01000000159/* Reserved [23:6] */160#define FLD_OE_AUX_PLL_CLK 0x00000020161#define FLD_OE_I2S_BCLK 0x00000010162#define FLD_OE_I2S_WCLK 0x00000008163#define FLD_OE_AGC_IF 0x00000004164#define FLD_OE_AGC_IFVGA 0x00000002165#define FLD_OE_AGC_RF 0x00000001166 167/*****************************************************************************/168#define AUD_IO_CTRL 0x124169/* Reserved [31:8] */170#define FLD_I2S_PORT_DIR 0x00000080171#define FLD_I2S_OUT_SRC 0x00000040172#define FLD_AUD_CHAN3_SRC 0x00000030173#define FLD_AUD_CHAN2_SRC 0x0000000c174#define FLD_AUD_CHAN1_SRC 0x00000003175 176/*****************************************************************************/177#define AUD_LOCK1 0x128178#define FLD_AUD_LOCK_KI_SHIFT 0xc0000000179#define FLD_AUD_LOCK_KD_SHIFT 0x30000000180/* Reserved [27:25] */181#define FLD_EN_AV_LOCK 0x01000000182#define FLD_VID_COUNT 0x00ffffff183 184/*****************************************************************************/185#define AUD_LOCK2 0x12c186#define FLD_AUD_LOCK_KI_MULT 0xf0000000187#define FLD_AUD_LOCK_KD_MULT 0x0F000000188/* Reserved [23:22] */189#define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000190#define FLD_AUD_COUNT 0x000fffff191 192/*****************************************************************************/193#define AFE_DIAG_CTRL1 0x134194/* Reserved [31:16] */195#define FLD_CUV_DLY_LENGTH 0x0000ff00196#define FLD_YC_DLY_LENGTH 0x000000ff197 198/*****************************************************************************/199/* Poalris redefine */200#define AFE_DIAG_CTRL3 0x138201/* Reserved [31:26] */202#define FLD_AUD_DUAL_FLAG_POL 0x02000000203#define FLD_VID_DUAL_FLAG_POL 0x01000000204/* Reserved [23:23] */205#define FLD_COL_CLAMP_DIS_CH1 0x00400000206#define FLD_COL_CLAMP_DIS_CH2 0x00200000207#define FLD_COL_CLAMP_DIS_CH3 0x00100000208 209#define TEST_CTRL1 0x144210/* Reserved [31:29] */211#define FLD_LBIST_EN 0x10000000212/* Reserved [27:10] */213#define FLD_FI_BIST_INTR_R 0x0000200214#define FLD_FI_BIST_INTR_L 0x0000100215#define FLD_BIST_FAIL_AUD_PLL 0x0000080216#define FLD_BIST_INTR_AUD_PLL 0x0000040217#define FLD_BIST_FAIL_VID_PLL 0x0000020218#define FLD_BIST_INTR_VID_PLL 0x0000010219/* Reserved [3:1] */220#define FLD_CIR_TEST_DIS 0x00000001221 222/*****************************************************************************/223#define TEST_CTRL2 0x148224#define FLD_TSXCLK_POL_CTL 0x80000000225#define FLD_ISO_CTL_SEL 0x40000000226#define FLD_ISO_CTL_EN 0x20000000227#define FLD_BIST_DEBUGZ 0x10000000228#define FLD_AUD_BIST_TEST_H 0x0f000000229/* Reserved [23:22] */230#define FLD_FLTRN_BIST_TEST_H 0x00020000231#define FLD_VID_BIST_TEST_H 0x00010000232/* Reserved [19:17] */233#define FLD_BIST_TEST_H 0x00010000234/* Reserved [15:13] */235#define FLD_TAB_EN 0x00001000236/* Reserved [11:0] */237 238/*****************************************************************************/239#define BIST_STAT 0x14c240#define FLD_AUD_BIST_FAIL_H 0xfff00000241#define FLD_FLTRN_BIST_FAIL_H 0x00180000242#define FLD_VID_BIST_FAIL_H 0x00070000243#define FLD_AUD_BIST_TST_DONE 0x0000fff0244#define FLD_FLTRN_BIST_TST_DONE 0x00000008245#define FLD_VID_BIST_TST_DONE 0x00000007246 247/*****************************************************************************/248/* DirectIF registers definition have been moved to DIF_reg.h */249/*****************************************************************************/250#define MODE_CTRL 0x400251#define FLD_AFD_PAL60_DIS 0x20000000252#define FLD_AFD_FORCE_SECAM 0x10000000253#define FLD_AFD_FORCE_PALNC 0x08000000254#define FLD_AFD_FORCE_PAL 0x04000000255#define FLD_AFD_PALM_SEL 0x03000000256#define FLD_CKILL_MODE 0x00300000257#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */258#define FLD_CLR_LOCK_STAT 0x00020000259#define FLD_FAST_LOCK_MD 0x00010000260#define FLD_WCEN 0x00008000261#define FLD_CAGCEN 0x00004000262#define FLD_CKILLEN 0x00002000263#define FLD_AUTO_SC_LOCK 0x00001000264#define FLD_MAN_SC_FAST_LOCK 0x00000800265#define FLD_INPUT_MODE 0x00000600266#define FLD_AFD_ACQUIRE 0x00000100267#define FLD_AFD_NTSC_SEL 0x00000080268#define FLD_AFD_PAL_SEL 0x00000040269#define FLD_ACFG_DIS 0x00000020270#define FLD_SQ_PIXEL 0x00000010271#define FLD_VID_FMT_SEL 0x0000000f272 273/*****************************************************************************/274#define OUT_CTRL1 0x404275#define FLD_POLAR 0x7f000000276/* Reserved [23] */277#define FLD_RND_MODE 0x00600000278#define FLD_VIPCLAMP_EN 0x00100000279#define FLD_VIPBLANK_EN 0x00080000280#define FLD_VIP_OPT_AL 0x00040000281#define FLD_IDID0_SOURCE 0x00020000282#define FLD_DCMODE 0x00010000283#define FLD_CLK_GATING 0x0000c000284#define FLD_CLK_INVERT 0x00002000285#define FLD_HSFMT 0x00001000286#define FLD_VALIDFMT 0x00000800287#define FLD_ACTFMT 0x00000400288#define FLD_SWAPRAW 0x00000200289#define FLD_CLAMPRAW_EN 0x00000100290#define FLD_BLUE_FIELD_EN 0x00000080291#define FLD_BLUE_FIELD_ACT 0x00000040292#define FLD_TASKBIT_VAL 0x00000020293#define FLD_ANC_DATA_EN 0x00000010294#define FLD_VBIHACTRAW_EN 0x00000008295#define FLD_MODE10B 0x00000004296#define FLD_OUT_MODE 0x00000003297 298/*****************************************************************************/299#define OUT_CTRL2 0x408300#define FLD_AUD_GRP 0xc0000000301#define FLD_SAMPLE_RATE 0x30000000302#define FLD_AUD_ANC_EN 0x08000000303#define FLD_EN_C 0x04000000304#define FLD_EN_B 0x02000000305#define FLD_EN_A 0x01000000306/* Reserved [23:20] */307#define FLD_IDID1_LSB 0x000c0000308#define FLD_IDID0_LSB 0x00030000309#define FLD_IDID1_MSB 0x0000ff00310#define FLD_IDID0_MSB 0x000000ff311 312/*****************************************************************************/313#define GEN_STAT 0x40c314#define FLD_VCR_DETECT 0x00800000315#define FLD_SPECIAL_PLAY_N 0x00400000316#define FLD_VPRES 0x00200000317#define FLD_AGC_LOCK 0x00100000318#define FLD_CSC_LOCK 0x00080000319#define FLD_VLOCK 0x00040000320#define FLD_SRC_LOCK 0x00020000321#define FLD_HLOCK 0x00010000322#define FLD_VSYNC_N 0x00008000323#define FLD_SRC_FIFO_UFLOW 0x00004000324#define FLD_SRC_FIFO_OFLOW 0x00002000325#define FLD_FIELD 0x00001000326#define FLD_AFD_FMT_STAT 0x00000f00327#define FLD_MV_TYPE2_PAIR 0x00000080328#define FLD_MV_T3CS 0x00000040329#define FLD_MV_CS 0x00000020330#define FLD_MV_PSP 0x00000010331/* Reserved [3] */332#define FLD_MV_CDAT 0x00000003333 334/*****************************************************************************/335#define INT_STAT_MASK 0x410336#define FLD_COMB_3D_FIFO_MSK 0x80000000337#define FLD_WSS_DAT_AVAIL_MSK 0x40000000338#define FLD_GS2_DAT_AVAIL_MSK 0x20000000339#define FLD_GS1_DAT_AVAIL_MSK 0x10000000340#define FLD_CC_DAT_AVAIL_MSK 0x08000000341#define FLD_VPRES_CHANGE_MSK 0x04000000342#define FLD_MV_CHANGE_MSK 0x02000000343#define FLD_END_VBI_EVEN_MSK 0x01000000344#define FLD_END_VBI_ODD_MSK 0x00800000345#define FLD_FMT_CHANGE_MSK 0x00400000346#define FLD_VSYNC_TRAIL_MSK 0x00200000347#define FLD_HLOCK_CHANGE_MSK 0x00100000348#define FLD_VLOCK_CHANGE_MSK 0x00080000349#define FLD_CSC_LOCK_CHANGE_MSK 0x00040000350#define FLD_SRC_FIFO_UFLOW_MSK 0x00020000351#define FLD_SRC_FIFO_OFLOW_MSK 0x00010000352#define FLD_COMB_3D_FIFO_STAT 0x00008000353#define FLD_WSS_DAT_AVAIL_STAT 0x00004000354#define FLD_GS2_DAT_AVAIL_STAT 0x00002000355#define FLD_GS1_DAT_AVAIL_STAT 0x00001000356#define FLD_CC_DAT_AVAIL_STAT 0x00000800357#define FLD_VPRES_CHANGE_STAT 0x00000400358#define FLD_MV_CHANGE_STAT 0x00000200359#define FLD_END_VBI_EVEN_STAT 0x00000100360#define FLD_END_VBI_ODD_STAT 0x00000080361#define FLD_FMT_CHANGE_STAT 0x00000040362#define FLD_VSYNC_TRAIL_STAT 0x00000020363#define FLD_HLOCK_CHANGE_STAT 0x00000010364#define FLD_VLOCK_CHANGE_STAT 0x00000008365#define FLD_CSC_LOCK_CHANGE_STAT 0x00000004366#define FLD_SRC_FIFO_UFLOW_STAT 0x00000002367#define FLD_SRC_FIFO_OFLOW_STAT 0x00000001368 369/*****************************************************************************/370#define LUMA_CTRL 0x414371#define BRIGHTNESS_CTRL_BYTE 0x414372#define CONTRAST_CTRL_BYTE 0x415373#define LUMA_CTRL_BYTE_3 0x416374#define FLD_LUMA_CORE_SEL 0x00c00000375#define FLD_RANGE 0x00300000376/* Reserved [19] */377#define FLD_PEAK_EN 0x00040000378#define FLD_PEAK_SEL 0x00030000379#define FLD_CNTRST 0x0000ff00380#define FLD_BRITE 0x000000ff381 382/*****************************************************************************/383#define HSCALE_CTRL 0x418384#define FLD_HFILT 0x03000000385#define FLD_HSCALE 0x00ffffff386 387/*****************************************************************************/388#define VSCALE_CTRL 0x41c389#define FLD_LINE_AVG_DIS 0x01000000390/* Reserved [23:20] */391#define FLD_VS_INTRLACE 0x00080000392#define FLD_VFILT 0x00070000393/* Reserved [15:13] */394#define FLD_VSCALE 0x00001fff395 396/*****************************************************************************/397#define CHROMA_CTRL 0x420398#define USAT_CTRL_BYTE 0x420399#define VSAT_CTRL_BYTE 0x421400#define HUE_CTRL_BYTE 0x422401#define FLD_C_LPF_EN 0x20000000402#define FLD_CHR_DELAY 0x1c000000403#define FLD_C_CORE_SEL 0x03000000404#define FLD_HUE 0x00ff0000405#define FLD_VSAT 0x0000ff00406#define FLD_USAT 0x000000ff407 408/*****************************************************************************/409#define VBI_LINE_CTRL1 0x424410#define FLD_VBI_MD_LINE4 0xff000000411#define FLD_VBI_MD_LINE3 0x00ff0000412#define FLD_VBI_MD_LINE2 0x0000ff00413#define FLD_VBI_MD_LINE1 0x000000ff414 415/*****************************************************************************/416#define VBI_LINE_CTRL2 0x428417#define FLD_VBI_MD_LINE8 0xff000000418#define FLD_VBI_MD_LINE7 0x00ff0000419#define FLD_VBI_MD_LINE6 0x0000ff00420#define FLD_VBI_MD_LINE5 0x000000ff421 422/*****************************************************************************/423#define VBI_LINE_CTRL3 0x42c424#define FLD_VBI_MD_LINE12 0xff000000425#define FLD_VBI_MD_LINE11 0x00ff0000426#define FLD_VBI_MD_LINE10 0x0000ff00427#define FLD_VBI_MD_LINE9 0x000000ff428 429/*****************************************************************************/430#define VBI_LINE_CTRL4 0x430431#define FLD_VBI_MD_LINE16 0xff000000432#define FLD_VBI_MD_LINE15 0x00ff0000433#define FLD_VBI_MD_LINE14 0x0000ff00434#define FLD_VBI_MD_LINE13 0x000000ff435 436/*****************************************************************************/437#define VBI_LINE_CTRL5 0x434438#define FLD_VBI_MD_LINE17 0x000000ff439 440/*****************************************************************************/441#define VBI_FC_CFG 0x438442#define FLD_FC_ALT2 0xff000000443#define FLD_FC_ALT1 0x00ff0000444#define FLD_FC_ALT2_TYPE 0x0000f000445#define FLD_FC_ALT1_TYPE 0x00000f00446/* Reserved [7:1] */447#define FLD_FC_SEARCH_MODE 0x00000001448 449/*****************************************************************************/450#define VBI_MISC_CFG1 0x43c451#define FLD_TTX_PKTADRU 0xfff00000452#define FLD_TTX_PKTADRL 0x000fff00453/* Reserved [7:6] */454#define FLD_MOJI_PACK_DIS 0x00000020455#define FLD_VPS_DEC_DIS 0x00000010456#define FLD_CRI_MARG_SCALE 0x0000000c457#define FLD_EDGE_RESYNC_EN 0x00000002458#define FLD_ADAPT_SLICE_DIS 0x00000001459 460/*****************************************************************************/461#define VBI_MISC_CFG2 0x440462#define FLD_HAMMING_TYPE 0x0f000000463/* Reserved [23:20] */464#define FLD_WSS_FIFO_RST 0x00080000465#define FLD_GS2_FIFO_RST 0x00040000466#define FLD_GS1_FIFO_RST 0x00020000467#define FLD_CC_FIFO_RST 0x00010000468/* Reserved [15:12] */469#define FLD_VBI3_SDID 0x00000f00470#define FLD_VBI2_SDID 0x000000f0471#define FLD_VBI1_SDID 0x0000000f472 473/*****************************************************************************/474#define VBI_PAY1 0x444475#define FLD_GS1_FIFO_DAT 0xFF000000476#define FLD_GS1_STAT 0x00FF0000477#define FLD_CC_FIFO_DAT 0x0000FF00478#define FLD_CC_STAT 0x000000FF479 480/*****************************************************************************/481#define VBI_PAY2 0x448482#define FLD_WSS_FIFO_DAT 0xff000000483#define FLD_WSS_STAT 0x00ff0000484#define FLD_GS2_FIFO_DAT 0x0000ff00485#define FLD_GS2_STAT 0x000000ff486 487/*****************************************************************************/488#define VBI_CUST1_CFG1 0x44c489/* Reserved [31] */490#define FLD_VBI1_CRIWIN 0x7f000000491#define FLD_VBI1_SLICE_DIST 0x00f00000492#define FLD_VBI1_BITINC 0x000fff00493#define FLD_VBI1_HDELAY 0x000000ff494 495/*****************************************************************************/496#define VBI_CUST1_CFG2 0x450497#define FLD_VBI1_FC_LENGTH 0x1f000000498#define FLD_VBI1_FRAME_CODE 0x00ffffff499 500/*****************************************************************************/501#define VBI_CUST1_CFG3 0x454502#define FLD_VBI1_HAM_EN 0x80000000503#define FLD_VBI1_FIFO_MODE 0x70000000504#define FLD_VBI1_FORMAT_TYPE 0x0f000000505#define FLD_VBI1_PAYLD_LENGTH 0x00ff0000506#define FLD_VBI1_CRI_LENGTH 0x0000f000507#define FLD_VBI1_CRI_MARGIN 0x00000f00508#define FLD_VBI1_CRI_TIME 0x000000ff509 510/*****************************************************************************/511#define VBI_CUST2_CFG1 0x458512/* Reserved [31] */513#define FLD_VBI2_CRIWIN 0x7f000000514#define FLD_VBI2_SLICE_DIST 0x00f00000515#define FLD_VBI2_BITINC 0x000fff00516#define FLD_VBI2_HDELAY 0x000000ff517 518/*****************************************************************************/519#define VBI_CUST2_CFG2 0x45c520#define FLD_VBI2_FC_LENGTH 0x1f000000521#define FLD_VBI2_FRAME_CODE 0x00ffffff522 523/*****************************************************************************/524#define VBI_CUST2_CFG3 0x460525#define FLD_VBI2_HAM_EN 0x80000000526#define FLD_VBI2_FIFO_MODE 0x70000000527#define FLD_VBI2_FORMAT_TYPE 0x0f000000528#define FLD_VBI2_PAYLD_LENGTH 0x00ff0000529#define FLD_VBI2_CRI_LENGTH 0x0000f000530#define FLD_VBI2_CRI_MARGIN 0x00000f00531#define FLD_VBI2_CRI_TIME 0x000000ff532 533/*****************************************************************************/534#define VBI_CUST3_CFG1 0x464535/* Reserved [31] */536#define FLD_VBI3_CRIWIN 0x7f000000537#define FLD_VBI3_SLICE_DIST 0x00f00000538#define FLD_VBI3_BITINC 0x000fff00539#define FLD_VBI3_HDELAY 0x000000ff540 541/*****************************************************************************/542#define VBI_CUST3_CFG2 0x468543#define FLD_VBI3_FC_LENGTH 0x1f000000544#define FLD_VBI3_FRAME_CODE 0x00ffffff545 546/*****************************************************************************/547#define VBI_CUST3_CFG3 0x46c548#define FLD_VBI3_HAM_EN 0x80000000549#define FLD_VBI3_FIFO_MODE 0x70000000550#define FLD_VBI3_FORMAT_TYPE 0x0f000000551#define FLD_VBI3_PAYLD_LENGTH 0x00ff0000552#define FLD_VBI3_CRI_LENGTH 0x0000f000553#define FLD_VBI3_CRI_MARGIN 0x00000f00554#define FLD_VBI3_CRI_TIME 0x000000ff555 556/*****************************************************************************/557#define HORIZ_TIM_CTRL 0x470558#define FLD_BGDEL_CNT 0xff000000559/* Reserved [23:22] */560#define FLD_HACTIVE_CNT 0x003ff000561/* Reserved [11:10] */562#define FLD_HBLANK_CNT 0x000003ff563 564/*****************************************************************************/565#define VERT_TIM_CTRL 0x474566#define FLD_V656BLANK_CNT 0xff000000567/* Reserved [23:22] */568#define FLD_VACTIVE_CNT 0x003ff000569/* Reserved [11:10] */570#define FLD_VBLANK_CNT 0x000003ff571 572/*****************************************************************************/573#define SRC_COMB_CFG 0x478574#define FLD_CCOMB_2LN_CHECK 0x80000000575#define FLD_CCOMB_3LN_EN 0x40000000576#define FLD_CCOMB_2LN_EN 0x20000000577#define FLD_CCOMB_3D_EN 0x10000000578/* Reserved [27] */579#define FLD_LCOMB_3LN_EN 0x04000000580#define FLD_LCOMB_2LN_EN 0x02000000581#define FLD_LCOMB_3D_EN 0x01000000582#define FLD_LUMA_LPF_SEL 0x00c00000583#define FLD_UV_LPF_SEL 0x00300000584#define FLD_BLEND_SLOPE 0x000f0000585#define FLD_CCOMB_REDUCE_EN 0x00008000586/* Reserved [14:10] */587#define FLD_SRC_DECIM_RATIO 0x000003ff588 589/*****************************************************************************/590#define CHROMA_VBIOFF_CFG 0x47c591#define FLD_VBI_VOFFSET 0x1f000000592/* Reserved [23:20] */593#define FLD_SC_STEP 0x000fffff594 595/*****************************************************************************/596#define FIELD_COUNT 0x480597#define FLD_FIELD_COUNT_FLD 0x000003ff598 599/*****************************************************************************/600#define MISC_TIM_CTRL 0x484601#define FLD_DEBOUNCE_COUNT 0xc0000000602#define FLD_VT_LINE_CNT_HYST 0x30000000603/* Reserved [27] */604#define FLD_AFD_STAT 0x07ff0000605#define FLD_VPRES_VERT_EN 0x00008000606/* Reserved [14:12] */607#define FLD_HR32 0x00000800608#define FLD_TDALGN 0x00000400609#define FLD_TDFIELD 0x00000200610/* Reserved [8:6] */611#define FLD_TEMPDEC 0x0000003f612 613/*****************************************************************************/614#define DFE_CTRL1 0x488615#define FLD_CLAMP_AUTO_EN 0x80000000616#define FLD_AGC_AUTO_EN 0x40000000617#define FLD_VGA_CRUSH_EN 0x20000000618#define FLD_VGA_AUTO_EN 0x10000000619#define FLD_VBI_GATE_EN 0x08000000620#define FLD_CLAMP_LEVEL 0x07000000621/* Reserved [23:22] */622#define FLD_CLAMP_SKIP_CNT 0x00300000623#define FLD_AGC_GAIN 0x000fff00624/* Reserved [7:6] */625#define FLD_VGA_GAIN 0x0000003f626 627/*****************************************************************************/628#define DFE_CTRL2 0x48c629#define FLD_VGA_ACQUIRE_RANGE 0x00ff0000630#define FLD_VGA_TRACK_RANGE 0x0000ff00631#define FLD_VGA_SYNC 0x000000ff632 633/*****************************************************************************/634#define DFE_CTRL3 0x490635#define FLD_BP_PERCENT 0xff000000636#define FLD_DFT_THRESHOLD 0x00ff0000637/* Reserved [15:12] */638#define FLD_SYNC_WIDTH_SEL 0x00000600639#define FLD_BP_LOOP_GAIN 0x00000300640#define FLD_SYNC_LOOP_GAIN 0x000000c0641/* Reserved [5:4] */642#define FLD_AGC_LOOP_GAIN 0x0000000c643#define FLD_DCC_LOOP_GAIN 0x00000003644 645/*****************************************************************************/646#define PLL_CTRL 0x494647#define FLD_PLL_KD 0xff000000648#define FLD_PLL_KI 0x00ff0000649#define FLD_PLL_MAX_OFFSET 0x0000ffff650 651/*****************************************************************************/652#define HTL_CTRL 0x498653/* Reserved [31:24] */654#define FLD_AUTO_LOCK_SPD 0x00080000655#define FLD_MAN_FAST_LOCK 0x00040000656#define FLD_HTL_15K_EN 0x00020000657#define FLD_HTL_500K_EN 0x00010000658#define FLD_HTL_KD 0x0000ff00659#define FLD_HTL_KI 0x000000ff660 661/*****************************************************************************/662#define COMB_CTRL 0x49c663#define FLD_COMB_PHASE_LIMIT 0xff000000664#define FLD_CCOMB_ERR_LIMIT 0x00ff0000665#define FLD_LUMA_THRESHOLD 0x0000ff00666#define FLD_LCOMB_ERR_LIMIT 0x000000ff667 668/*****************************************************************************/669#define CRUSH_CTRL 0x4a0670#define FLD_WTW_EN 0x00400000671#define FLD_CRUSH_FREQ 0x00200000672#define FLD_MAJ_SEL_EN 0x00100000673#define FLD_MAJ_SEL 0x000c0000674/* Reserved [17:15] */675#define FLD_SYNC_TIP_REDUCE 0x00007e00676/* Reserved [8:6] */677#define FLD_SYNC_TIP_INC 0x0000003f678 679/*****************************************************************************/680#define SOFT_RST_CTRL 0x4a4681#define FLD_VD_SOFT_RST 0x00008000682/* Reserved [14:12] */683#define FLD_REG_RST_MSK 0x00000800684#define FLD_VOF_RST_MSK 0x00000400685#define FLD_MVDET_RST_MSK 0x00000200686#define FLD_VBI_RST_MSK 0x00000100687#define FLD_SCALE_RST_MSK 0x00000080688#define FLD_CHROMA_RST_MSK 0x00000040689#define FLD_LUMA_RST_MSK 0x00000020690#define FLD_VTG_RST_MSK 0x00000010691#define FLD_YCSEP_RST_MSK 0x00000008692#define FLD_SRC_RST_MSK 0x00000004693#define FLD_DFE_RST_MSK 0x00000002694/* Reserved [0] */695 696/*****************************************************************************/697#define MV_DT_CTRL1 0x4a8698/* Reserved [31:29] */699#define FLD_PSP_STOP_LINE 0x1f000000700/* Reserved [23:21] */701#define FLD_PSP_STRT_LINE 0x001f0000702/* Reserved [15] */703#define FLD_PSP_LLIMW 0x00007f00704/* Reserved [7] */705#define FLD_PSP_ULIMW 0x0000007f706 707/*****************************************************************************/708#define MV_DT_CTRL2 0x4aC709#define FLD_CS_STOPWIN 0xff000000710#define FLD_CS_STRTWIN 0x00ff0000711#define FLD_CS_WIDTH 0x0000ff00712#define FLD_PSP_SPEC_VAL 0x000000ff713 714/*****************************************************************************/715#define MV_DT_CTRL3 0x4B0716#define FLD_AUTO_RATE_DIS 0x80000000717#define FLD_HLOCK_DIS 0x40000000718#define FLD_SEL_FIELD_CNT 0x20000000719#define FLD_CS_TYPE2_SEL 0x10000000720#define FLD_CS_LINE_THRSH_SEL 0x08000000721#define FLD_CS_ATHRESH_SEL 0x04000000722#define FLD_PSP_SPEC_SEL 0x02000000723#define FLD_PSP_LINES_SEL 0x01000000724#define FLD_FIELD_CNT 0x00f00000725#define FLD_CS_TYPE2_CNT 0x000fc000726#define FLD_CS_LINE_CNT 0x00003f00727#define FLD_CS_ATHRESH_LEV 0x000000ff728 729/*****************************************************************************/730#define CHIP_VERSION 0x4b4731/* Cx231xx redefine */732#define VERSION 0x4b4733#define FLD_REV_ID 0x000000ff734 735/*****************************************************************************/736#define MISC_DIAG_CTRL 0x4b8737/* Reserved [31:24] */738#define FLD_SC_CONVERGE_THRESH 0x00ff0000739#define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00740#define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff741 742/*****************************************************************************/743#define VBI_PASS_CTRL 0x4bc744#define FLD_VBI_PASS_MD 0x00200000745#define FLD_VBI_SETUP_DIS 0x00100000746#define FLD_PASS_LINE_CTRL 0x000fffff747 748/*****************************************************************************/749/* Cx231xx redefine */750#define VCR_DET_CTRL 0x4c0751#define FLD_EN_FIELD_PHASE_DET 0x80000000752#define FLD_EN_HEAD_SW_DET 0x40000000753#define FLD_FIELD_PHASE_LENGTH 0x01ff0000754/* Reserved [29:25] */755#define FLD_FIELD_PHASE_DELAY 0x0000ff00756#define FLD_FIELD_PHASE_LIMIT 0x000000f0757#define FLD_HEAD_SW_DET_LIMIT 0x0000000f758 759/*****************************************************************************/760#define DL_CTL 0x800761#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */762#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */763#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */764#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */765/* Reserved [31:5] */766#define FLD_START_8051 0x10000000767#define FLD_DL_ENABLE 0x08000000768#define FLD_DL_AUTO_INC 0x04000000769#define FLD_DL_MAP 0x03000000770 771/*****************************************************************************/772#define STD_DET_STATUS 0x804773#define FLD_SPARE_STATUS1 0xff000000774#define FLD_SPARE_STATUS0 0x00ff0000775#define FLD_MOD_DET_STATUS1 0x0000ff00776#define FLD_MOD_DET_STATUS0 0x000000ff777 778/*****************************************************************************/779#define AUD_BUILD_NUM 0x806780#define AUD_VER_NUM 0x807781#define STD_DET_CTL 0x808782#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */783#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */784#define FLD_SPARE_CTL0 0xff000000785#define FLD_DIS_DBX 0x00800000786#define FLD_DIS_BTSC 0x00400000787#define FLD_DIS_NICAM_A2 0x00200000788#define FLD_VIDEO_PRESENT 0x00100000789#define FLD_DW8051_VIDEO_FORMAT 0x000f0000790#define FLD_PREF_DEC_MODE 0x0000ff00791#define FLD_AUD_CONFIG 0x000000ff792 793/*****************************************************************************/794#define DW8051_INT 0x80c795#define FLD_VIDEO_PRESENT_CHANGE 0x80000000796#define FLD_VIDEO_CHANGE 0x40000000797#define FLD_RDS_READY 0x20000000798#define FLD_AC97_INT 0x10000000799#define FLD_NICAM_BIT_ERROR_TOO_HIGH 0x08000000800#define FLD_NICAM_LOCK 0x04000000801#define FLD_NICAM_UNLOCK 0x02000000802#define FLD_DFT4_TH_CMP 0x01000000803/* Reserved [23:22] */804#define FLD_LOCK_IND_INT 0x00200000805#define FLD_DFT3_TH_CMP 0x00100000806#define FLD_DFT2_TH_CMP 0x00080000807#define FLD_DFT1_TH_CMP 0x00040000808#define FLD_FM2_DFT_TH_CMP 0x00020000809#define FLD_FM1_DFT_TH_CMP 0x00010000810#define FLD_VIDEO_PRESENT_EN 0x00008000811#define FLD_VIDEO_CHANGE_EN 0x00004000812#define FLD_RDS_READY_EN 0x00002000813#define FLD_AC97_INT_EN 0x00001000814#define FLD_NICAM_BIT_ERROR_TOO_HIGH_EN 0x00000800815#define FLD_NICAM_LOCK_EN 0x00000400816#define FLD_NICAM_UNLOCK_EN 0x00000200817#define FLD_DFT4_TH_CMP_EN 0x00000100818/* Reserved [7] */819#define FLD_DW8051_INT6_CTL1 0x00000040820#define FLD_DW8051_INT5_CTL1 0x00000020821#define FLD_DW8051_INT4_CTL1 0x00000010822#define FLD_DW8051_INT3_CTL1 0x00000008823#define FLD_DW8051_INT2_CTL1 0x00000004824#define FLD_DW8051_INT1_CTL1 0x00000002825#define FLD_DW8051_INT0_CTL1 0x00000001826 827/*****************************************************************************/828#define GENERAL_CTL 0x810829#define FLD_RDS_INT 0x80000000830#define FLD_NBER_INT 0x40000000831#define FLD_NLL_INT 0x20000000832#define FLD_IFL_INT 0x10000000833#define FLD_FDL_INT 0x08000000834#define FLD_AFC_INT 0x04000000835#define FLD_AMC_INT 0x02000000836#define FLD_AC97_INT_CTL 0x01000000837#define FLD_RDS_INT_DIS 0x00800000838#define FLD_NBER_INT_DIS 0x00400000839#define FLD_NLL_INT_DIS 0x00200000840#define FLD_IFL_INT_DIS 0x00100000841#define FLD_FDL_INT_DIS 0x00080000842#define FLD_FC_INT_DIS 0x00040000843#define FLD_AMC_INT_DIS 0x00020000844#define FLD_AC97_INT_DIS 0x00010000845#define FLD_REV_NUM 0x0000ff00846/* Reserved [7:5] */847#define FLD_DBX_SOFT_RESET_REG 0x00000010848#define FLD_AD_SOFT_RESET_REG 0x00000008849#define FLD_SRC_SOFT_RESET_REG 0x00000004850#define FLD_CDMOD_SOFT_RESET 0x00000002851#define FLD_8051_SOFT_RESET 0x00000001852 853/*****************************************************************************/854#define AAGC_CTL 0x814855#define FLD_AFE_12DB_EN 0x80000000856#define FLD_AAGC_DEFAULT_EN 0x40000000857#define FLD_AAGC_DEFAULT 0x3f000000858/* Reserved [23] */859#define FLD_AAGC_GAIN 0x00600000860#define FLD_AAGC_TH 0x001f0000861/* Reserved [15:14] */862#define FLD_AAGC_HYST2 0x00003f00863/* Reserved [7:6] */864#define FLD_AAGC_HYST1 0x0000003f865 866/*****************************************************************************/867#define IF_SRC_CTL 0x818868#define FLD_DBX_BYPASS 0x80000000869/* Reserved [30:25] */870#define FLD_IF_SRC_MODE 0x01000000871/* Reserved [23:18] */872#define FLD_IF_SRC_PHASE_INC 0x0001ffff873 874/*****************************************************************************/875#define ANALOG_DEMOD_CTL 0x81c876#define FLD_ROT1_PHACC_PROG 0xffff0000877/* Reserved [15] */878#define FLD_FM1_DELAY_FIX 0x00007000879#define FLD_PDF4_SHIFT 0x00000c00880#define FLD_PDF3_SHIFT 0x00000300881#define FLD_PDF2_SHIFT 0x000000c0882#define FLD_PDF1_SHIFT 0x00000030883#define FLD_FMBYPASS_MODE2 0x00000008884#define FLD_FMBYPASS_MODE1 0x00000004885#define FLD_NICAM_MODE 0x00000002886#define FLD_BTSC_FMRADIO_MODE 0x00000001887 888/*****************************************************************************/889#define ROT_FREQ_CTL 0x820890#define FLD_ROT3_PHACC_PROG 0xffff0000891#define FLD_ROT2_PHACC_PROG 0x0000ffff892 893/*****************************************************************************/894#define FM_CTL 0x824895#define FLD_FM2_DC_FB_SHIFT 0xf0000000896#define FLD_FM2_DC_INT_SHIFT 0x0f000000897#define FLD_FM2_AFC_RESET 0x00800000898#define FLD_FM2_DC_PASS_IN 0x00400000899#define FLD_FM2_DAGC_SHIFT 0x00380000900#define FLD_FM2_CORDIC_SHIFT 0x00070000901#define FLD_FM1_DC_FB_SHIFT 0x0000f000902#define FLD_FM1_DC_INT_SHIFT 0x00000f00903#define FLD_FM1_AFC_RESET 0x00000080904#define FLD_FM1_DC_PASS_IN 0x00000040905#define FLD_FM1_DAGC_SHIFT 0x00000038906#define FLD_FM1_CORDIC_SHIFT 0x00000007907 908/*****************************************************************************/909#define LPF_PDF_CTL 0x828910/* Reserved [31:30] */911#define FLD_LPF32_SHIFT1 0x30000000912#define FLD_LPF32_SHIFT2 0x0c000000913#define FLD_LPF160_SHIFTA 0x03000000914#define FLD_LPF160_SHIFTB 0x00c00000915#define FLD_LPF160_SHIFTC 0x00300000916#define FLD_LPF32_COEF_SEL2 0x000c0000917#define FLD_LPF32_COEF_SEL1 0x00030000918#define FLD_LPF160_COEF_SELC 0x0000c000919#define FLD_LPF160_COEF_SELB 0x00003000920#define FLD_LPF160_COEF_SELA 0x00000c00921#define FLD_LPF160_IN_EN_REG 0x00000300922#define FLD_PDF4_PDF_SEL 0x000000c0923#define FLD_PDF3_PDF_SEL 0x00000030924#define FLD_PDF2_PDF_SEL 0x0000000c925#define FLD_PDF1_PDF_SEL 0x00000003926 927/*****************************************************************************/928#define DFT1_CTL1 0x82c929#define FLD_DFT1_DWELL 0xffff0000930#define FLD_DFT1_FREQ 0x0000ffff931 932/*****************************************************************************/933#define DFT1_CTL2 0x830934#define FLD_DFT1_THRESHOLD 0xffffff00935#define FLD_DFT1_CMP_CTL 0x00000080936#define FLD_DFT1_AVG 0x00000070937/* Reserved [3:1] */938#define FLD_DFT1_START 0x00000001939 940/*****************************************************************************/941#define DFT1_STATUS 0x834942#define FLD_DFT1_DONE 0x80000000943#define FLD_DFT1_TH_CMP_STAT 0x40000000944#define FLD_DFT1_RESULT 0x3fffffff945 946/*****************************************************************************/947#define DFT2_CTL1 0x838948#define FLD_DFT2_DWELL 0xffff0000949#define FLD_DFT2_FREQ 0x0000ffff950 951/*****************************************************************************/952#define DFT2_CTL2 0x83C953#define FLD_DFT2_THRESHOLD 0xffffff00954#define FLD_DFT2_CMP_CTL 0x00000080955#define FLD_DFT2_AVG 0x00000070956/* Reserved [3:1] */957#define FLD_DFT2_START 0x00000001958 959/*****************************************************************************/960#define DFT2_STATUS 0x840961#define FLD_DFT2_DONE 0x80000000962#define FLD_DFT2_TH_CMP_STAT 0x40000000963#define FLD_DFT2_RESULT 0x3fffffff964 965/*****************************************************************************/966#define DFT3_CTL1 0x844967#define FLD_DFT3_DWELL 0xffff0000968#define FLD_DFT3_FREQ 0x0000ffff969 970/*****************************************************************************/971#define DFT3_CTL2 0x848972#define FLD_DFT3_THRESHOLD 0xffffff00973#define FLD_DFT3_CMP_CTL 0x00000080974#define FLD_DFT3_AVG 0x00000070975/* Reserved [3:1] */976#define FLD_DFT3_START 0x00000001977 978/*****************************************************************************/979#define DFT3_STATUS 0x84c980#define FLD_DFT3_DONE 0x80000000981#define FLD_DFT3_TH_CMP_STAT 0x40000000982#define FLD_DFT3_RESULT 0x3fffffff983 984/*****************************************************************************/985#define DFT4_CTL1 0x850986#define FLD_DFT4_DWELL 0xffff0000987#define FLD_DFT4_FREQ 0x0000ffff988 989/*****************************************************************************/990#define DFT4_CTL2 0x854991#define FLD_DFT4_THRESHOLD 0xffffff00992#define FLD_DFT4_CMP_CTL 0x00000080993#define FLD_DFT4_AVG 0x00000070994/* Reserved [3:1] */995#define FLD_DFT4_START 0x00000001996 997/*****************************************************************************/998#define DFT4_STATUS 0x858999#define FLD_DFT4_DONE 0x800000001000#define FLD_DFT4_TH_CMP_STAT 0x400000001001#define FLD_DFT4_RESULT 0x3fffffff1002 1003/*****************************************************************************/1004#define AM_MTS_DET 0x85c1005#define FLD_AM_MTS_MODE 0x800000001006/* Reserved [30:26] */1007#define FLD_AM_SUB 0x020000001008#define FLD_AM_GAIN_EN 0x010000001009/* Reserved [23:16] */1010#define FLD_AMMTS_GAIN_SCALE 0x0000e0001011#define FLD_MTS_PDF_SHIFT 0x000018001012#define FLD_AM_REG_GAIN 0x000007001013#define FLD_AGC_REF 0x000000ff1014 1015/*****************************************************************************/1016#define ANALOG_MUX_CTL 0x8601017/* Reserved [31:29] */1018#define FLD_MUX21_SEL 0x100000001019#define FLD_MUX20_SEL 0x080000001020#define FLD_MUX19_SEL 0x040000001021#define FLD_MUX18_SEL 0x020000001022#define FLD_MUX17_SEL 0x010000001023#define FLD_MUX16_SEL 0x008000001024#define FLD_MUX15_SEL 0x004000001025#define FLD_MUX14_SEL 0x003000001026#define FLD_MUX13_SEL 0x000C00001027#define FLD_MUX12_SEL 0x000200001028#define FLD_MUX11_SEL 0x000180001029#define FLD_MUX10_SEL 0x000040001030#define FLD_MUX9_SEL 0x000020001031#define FLD_MUX8_SEL 0x000010001032#define FLD_MUX7_SEL 0x000008001033#define FLD_MUX6_SEL 0x000006001034#define FLD_MUX5_SEL 0x000001001035#define FLD_MUX4_SEL 0x000000c01036#define FLD_MUX3_SEL 0x000000301037#define FLD_MUX2_SEL 0x0000000c1038#define FLD_MUX1_SEL 0x000000031039 1040/*****************************************************************************/1041/* Cx231xx redefine */1042#define DPLL_CTRL1 0x8641043#define DIG_PLL_CTL1 0x8641044 1045#define FLD_PLL_STATUS 0x070000001046#define FLD_BANDWIDTH_SELECT 0x000300001047#define FLD_PLL_SHIFT_REG 0x000070001048#define FLD_PHASE_SHIFT 0x000007ff1049 1050/*****************************************************************************/1051/* Cx231xx redefine */1052#define DPLL_CTRL2 0x8681053#define DIG_PLL_CTL2 0x8681054#define FLD_PLL_UNLOCK_THR 0xff0000001055#define FLD_PLL_LOCK_THR 0x00ff00001056/* Reserved [15:8] */1057#define FLD_AM_PDF_SEL2 0x000000c01058#define FLD_AM_PDF_SEL1 0x000000301059#define FLD_DPLL_FSM_CTRL 0x0000000c1060/* Reserved [1] */1061#define FLD_PLL_PILOT_DET 0x000000011062 1063/*****************************************************************************/1064/* Cx231xx redefine */1065#define DPLL_CTRL3 0x86c1066#define DIG_PLL_CTL3 0x86c1067#define FLD_DISABLE_LOOP 0x010000001068#define FLD_A1_DS1_SEL 0x000c00001069#define FLD_A1_DS2_SEL 0x000300001070#define FLD_A1_KI 0x0000ff001071#define FLD_A1_KD 0x000000ff1072 1073/*****************************************************************************/1074/* Cx231xx redefine */1075#define DPLL_CTRL4 0x8701076#define DIG_PLL_CTL4 0x8701077#define FLD_A2_DS1_SEL 0x000c00001078#define FLD_A2_DS2_SEL 0x000300001079#define FLD_A2_KI 0x0000ff001080#define FLD_A2_KD 0x000000ff1081 1082/*****************************************************************************/1083/* Cx231xx redefine */1084#define DPLL_CTRL5 0x8741085#define DIG_PLL_CTL5 0x8741086#define FLD_TRK_DS1_SEL 0x000c00001087#define FLD_TRK_DS2_SEL 0x000300001088#define FLD_TRK_KI 0x0000ff001089#define FLD_TRK_KD 0x000000ff1090 1091/*****************************************************************************/1092#define DEEMPH_GAIN_CTL 0x8781093#define FLD_DEEMPH2_GAIN 0xFFFF00001094#define FLD_DEEMPH1_GAIN 0x0000FFFF1095 1096/*****************************************************************************/1097/* Cx231xx redefine */1098#define DEEMPH_COEFF1 0x87c1099#define DEEMPH_COEF1 0x87c1100#define FLD_DEEMPH_B0 0xffff00001101#define FLD_DEEMPH_A0 0x0000ffff1102 1103/*****************************************************************************/1104/* Cx231xx redefine */1105#define DEEMPH_COEFF2 0x8801106#define DEEMPH_COEF2 0x8801107#define FLD_DEEMPH_B1 0xFFFF00001108#define FLD_DEEMPH_A1 0x0000FFFF1109 1110/*****************************************************************************/1111#define DBX1_CTL1 0x8841112#define FLD_DBX1_WBE_GAIN 0xffff00001113#define FLD_DBX1_IN_GAIN 0x0000ffff1114 1115/*****************************************************************************/1116#define DBX1_CTL2 0x8881117#define FLD_DBX1_SE_BYPASS 0xffff00001118#define FLD_DBX1_SE_GAIN 0x0000ffff1119 1120/*****************************************************************************/1121#define DBX1_RMS_SE 0x88C1122#define FLD_DBX1_RMS_WBE 0xffff00001123#define FLD_DBX1_RMS_SE_FLD 0x0000ffff1124 1125/*****************************************************************************/1126#define DBX2_CTL1 0x8901127#define FLD_DBX2_WBE_GAIN 0xffff00001128#define FLD_DBX2_IN_GAIN 0x0000ffff1129 1130/*****************************************************************************/1131#define DBX2_CTL2 0x8941132#define FLD_DBX2_SE_BYPASS 0xffff00001133#define FLD_DBX2_SE_GAIN 0x0000ffff1134 1135/*****************************************************************************/1136#define DBX2_RMS_SE 0x8981137#define FLD_DBX2_RMS_WBE 0xffff00001138#define FLD_DBX2_RMS_SE_FLD 0x0000ffff1139 1140/*****************************************************************************/1141#define AM_FM_DIFF 0x89c1142/* Reserved [31] */1143#define FLD_FM_DIFF_OUT 0x7fff00001144/* Reserved [15] */1145#define FLD_AM_DIFF_OUT 0x00007fff1146 1147/*****************************************************************************/1148#define NICAM_FAW 0x8a01149#define FLD_FAWDETWINEND 0xFc0000001150#define FLD_FAWDETWINSTR 0x03ff00001151/* Reserved [15:12] */1152#define FLD_FAWDETTHRSHLD3 0x00000f001153#define FLD_FAWDETTHRSHLD2 0x000000f01154#define FLD_FAWDETTHRSHLD1 0x0000000f1155 1156/*****************************************************************************/1157/* Cx231xx redefine */1158#define DEEMPH_GAIN 0x8a41159#define NICAM_DEEMPHGAIN 0x8a41160/* Reserved [31:18] */1161#define FLD_DEEMPHGAIN 0x0003ffff1162 1163/*****************************************************************************/1164/* Cx231xx redefine */1165#define DEEMPH_NUMER1 0x8a81166#define NICAM_DEEMPHNUMER1 0x8a81167/* Reserved [31:18] */1168#define FLD_DEEMPHNUMER1 0x0003ffff1169 1170/*****************************************************************************/1171/* Cx231xx redefine */1172#define DEEMPH_NUMER2 0x8ac1173#define NICAM_DEEMPHNUMER2 0x8ac1174/* Reserved [31:18] */1175#define FLD_DEEMPHNUMER2 0x0003ffff1176 1177/*****************************************************************************/1178/* Cx231xx redefine */1179#define DEEMPH_DENOM1 0x8b01180#define NICAM_DEEMPHDENOM1 0x8b01181/* Reserved [31:18] */1182#define FLD_DEEMPHDENOM1 0x0003ffff1183 1184/*****************************************************************************/1185/* Cx231xx redefine */1186#define DEEMPH_DENOM2 0x8b41187#define NICAM_DEEMPHDENOM2 0x8b41188/* Reserved [31:18] */1189#define FLD_DEEMPHDENOM2 0x0003ffff1190 1191/*****************************************************************************/1192#define NICAM_ERRLOG_CTL1 0x8B81193/* Reserved [31:28] */1194#define FLD_ERRINTRPTTHSHLD1 0x0fff00001195/* Reserved [15:12] */1196#define FLD_ERRLOGPERIOD 0x00000fff1197 1198/*****************************************************************************/1199#define NICAM_ERRLOG_CTL2 0x8bc1200/* Reserved [31:28] */1201#define FLD_ERRINTRPTTHSHLD3 0x0fff00001202/* Reserved [15:12] */1203#define FLD_ERRINTRPTTHSHLD2 0x00000fff1204 1205/*****************************************************************************/1206#define NICAM_ERRLOG_STS1 0x8c01207/* Reserved [31:28] */1208#define FLD_ERRLOG2 0x0fff00001209/* Reserved [15:12] */1210#define FLD_ERRLOG1 0x00000fff1211 1212/*****************************************************************************/1213#define NICAM_ERRLOG_STS2 0x8c41214/* Reserved [31:12] */1215#define FLD_ERRLOG3 0x00000fff1216 1217/*****************************************************************************/1218#define NICAM_STATUS 0x8c81219/* Reserved [31:20] */1220#define FLD_NICAM_CIB 0x000c00001221#define FLD_NICAM_LOCK_STAT 0x000200001222#define FLD_NICAM_MUTE 0x000100001223#define FLD_NICAMADDIT_DATA 0x0000ffe01224#define FLD_NICAMCNTRL 0x0000001f1225 1226/*****************************************************************************/1227#define DEMATRIX_CTL 0x8cc1228#define FLD_AC97_IN_SHIFT 0xf00000001229#define FLD_I2S_IN_SHIFT 0x0f0000001230#define FLD_DEMATRIX_SEL_CTL 0x00ff00001231/* Reserved [15:11] */1232#define FLD_DMTRX_BYPASS 0x000004001233#define FLD_DEMATRIX_MODE 0x000003001234/* Reserved [7:6] */1235#define FLD_PH_DBX_SEL 0x000000201236#define FLD_PH_CH_SEL 0x000000101237#define FLD_PHASE_FIX 0x0000000f1238 1239/*****************************************************************************/1240#define PATH1_CTL1 0x8d01241/* Reserved [31:29] */1242#define FLD_PATH1_MUTE_CTL 0x1f0000001243/* Reserved [23:22] */1244#define FLD_PATH1_AVC_CG 0x003000001245#define FLD_PATH1_AVC_RT 0x000f00001246#define FLD_PATH1_AVC_AT 0x0000f0001247#define FLD_PATH1_AVC_STEREO 0x000008001248#define FLD_PATH1_AVC_CR 0x000007001249#define FLD_PATH1_AVC_RMS_CON 0x000000f01250#define FLD_PATH1_SEL_CTL 0x0000000f1251 1252/*****************************************************************************/1253#define PATH1_VOL_CTL 0x8d41254#define FLD_PATH1_AVC_THRESHOLD 0x7fff00001255#define FLD_PATH1_BAL_LEFT 0x000080001256#define FLD_PATH1_BAL_LEVEL 0x00007f001257#define FLD_PATH1_VOLUME 0x000000ff1258 1259/*****************************************************************************/1260#define PATH1_EQ_CTL 0x8d81261/* Reserved [31:30] */1262#define FLD_PATH1_EQ_TREBLE_VOL 0x3f0000001263/* Reserved [23:22] */1264#define FLD_PATH1_EQ_MID_VOL 0x003f00001265/* Reserved [15:14] */1266#define FLD_PATH1_EQ_BASS_VOL 0x00003f001267/* Reserved [7:1] */1268#define FLD_PATH1_EQ_BAND_SEL 0x000000011269 1270/*****************************************************************************/1271#define PATH1_SC_CTL 0x8dc1272#define FLD_PATH1_SC_THRESHOLD 0x7fff00001273#define FLD_PATH1_SC_RT 0x0000f0001274#define FLD_PATH1_SC_AT 0x00000f001275#define FLD_PATH1_SC_STEREO 0x000000801276#define FLD_PATH1_SC_CR 0x000000701277#define FLD_PATH1_SC_RMS_CON 0x0000000f1278 1279/*****************************************************************************/1280#define PATH2_CTL1 0x8e01281/* Reserved [31:26] */1282#define FLD_PATH2_MUTE_CTL 0x030000001283/* Reserved [23:22] */1284#define FLD_PATH2_AVC_CG 0x003000001285#define FLD_PATH2_AVC_RT 0x000f00001286#define FLD_PATH2_AVC_AT 0x0000f0001287#define FLD_PATH2_AVC_STEREO 0x000008001288#define FLD_PATH2_AVC_CR 0x000007001289#define FLD_PATH2_AVC_RMS_CON 0x000000f01290#define FLD_PATH2_SEL_CTL 0x0000000f1291 1292/*****************************************************************************/1293#define PATH2_VOL_CTL 0x8e41294#define FLD_PATH2_AVC_THRESHOLD 0xffff00001295#define FLD_PATH2_BAL_LEFT 0x000080001296#define FLD_PATH2_BAL_LEVEL 0x00007f001297#define FLD_PATH2_VOLUME 0x000000ff1298 1299/*****************************************************************************/1300#define PATH2_EQ_CTL 0x8e81301/* Reserved [31:30] */1302#define FLD_PATH2_EQ_TREBLE_VOL 0x3f0000001303/* Reserved [23:22] */1304#define FLD_PATH2_EQ_MID_VOL 0x003f00001305/* Reserved [15:14] */1306#define FLD_PATH2_EQ_BASS_VOL 0x00003f001307/* Reserved [7:1] */1308#define FLD_PATH2_EQ_BAND_SEL 0x000000011309 1310/*****************************************************************************/1311#define PATH2_SC_CTL 0x8eC1312#define FLD_PATH2_SC_THRESHOLD 0xffff00001313#define FLD_PATH2_SC_RT 0x0000f0001314#define FLD_PATH2_SC_AT 0x00000f001315#define FLD_PATH2_SC_STEREO 0x000000801316#define FLD_PATH2_SC_CR 0x000000701317#define FLD_PATH2_SC_RMS_CON 0x0000000f1318 1319/*****************************************************************************/1320#define SRC_CTL 0x8f01321#define FLD_SRC_STATUS 0xffffff001322#define FLD_FIFO_LF_EN 0x000000fc1323#define FLD_BYPASS_LI 0x000000021324#define FLD_BYPASS_PF 0x000000011325 1326/*****************************************************************************/1327#define SRC_LF_COEF 0x8f41328#define FLD_LOOP_FILTER_COEF2 0xffff00001329#define FLD_LOOP_FILTER_COEF1 0x0000ffff1330 1331/*****************************************************************************/1332#define SRC1_CTL 0x8f81333/* Reserved [31:28] */1334#define FLD_SRC1_FIFO_RD_TH 0x0f0000001335/* Reserved [23:18] */1336#define FLD_SRC1_PHASE_INC 0x0003ffff1337 1338/*****************************************************************************/1339#define SRC2_CTL 0x8fc1340/* Reserved [31:28] */1341#define FLD_SRC2_FIFO_RD_TH 0x0f0000001342/* Reserved [23:18] */1343#define FLD_SRC2_PHASE_INC 0x0003ffff1344 1345/*****************************************************************************/1346#define SRC3_CTL 0x9001347/* Reserved [31:28] */1348#define FLD_SRC3_FIFO_RD_TH 0x0f0000001349/* Reserved [23:18] */1350#define FLD_SRC3_PHASE_INC 0x0003ffff1351 1352/*****************************************************************************/1353#define SRC4_CTL 0x9041354/* Reserved [31:28] */1355#define FLD_SRC4_FIFO_RD_TH 0x0f0000001356/* Reserved [23:18] */1357#define FLD_SRC4_PHASE_INC 0x0003ffff1358 1359/*****************************************************************************/1360#define SRC5_CTL 0x9081361/* Reserved [31:28] */1362#define FLD_SRC5_FIFO_RD_TH 0x0f0000001363/* Reserved [23:18] */1364#define FLD_SRC5_PHASE_INC 0x0003ffff1365 1366/*****************************************************************************/1367#define SRC6_CTL 0x90c1368/* Reserved [31:28] */1369#define FLD_SRC6_FIFO_RD_TH 0x0f0000001370/* Reserved [23:18] */1371#define FLD_SRC6_PHASE_INC 0x0003ffff1372 1373/*****************************************************************************/1374#define BAND_OUT_SEL 0x9101375#define FLD_SRC6_IN_SEL 0xc00000001376#define FLD_SRC6_CLK_SEL 0x300000001377#define FLD_SRC5_IN_SEL 0x0c0000001378#define FLD_SRC5_CLK_SEL 0x030000001379#define FLD_SRC4_IN_SEL 0x00c000001380#define FLD_SRC4_CLK_SEL 0x003000001381#define FLD_SRC3_IN_SEL 0x000c00001382#define FLD_SRC3_CLK_SEL 0x000300001383#define FLD_BASEBAND_BYPASS_CTL 0x0000ff001384#define FLD_AC97_SRC_SEL 0x000000c01385#define FLD_I2S_SRC_SEL 0x000000301386#define FLD_PARALLEL2_SRC_SEL 0x0000000c1387#define FLD_PARALLEL1_SRC_SEL 0x000000031388 1389/*****************************************************************************/1390#define I2S_IN_CTL 0x9141391/* Reserved [31:11] */1392#define FLD_I2S_UP2X_BW20K 0x000004001393#define FLD_I2S_UP2X_BYPASS 0x000002001394#define FLD_I2S_IN_MASTER_MODE 0x000001001395#define FLD_I2S_IN_SONY_MODE 0x000000801396#define FLD_I2S_IN_RIGHT_JUST 0x000000401397#define FLD_I2S_IN_WS_SEL 0x000000201398#define FLD_I2S_IN_BCN_DEL 0x0000001f1399 1400/*****************************************************************************/1401#define I2S_OUT_CTL 0x9181402/* Reserved [31:17] */1403#define FLD_I2S_OUT_SOFT_RESET_EN 0x000100001404/* Reserved [15:9] */1405#define FLD_I2S_OUT_MASTER_MODE 0x000001001406#define FLD_I2S_OUT_SONY_MODE 0x000000801407#define FLD_I2S_OUT_RIGHT_JUST 0x000000401408#define FLD_I2S_OUT_WS_SEL 0x000000201409#define FLD_I2S_OUT_BCN_DEL 0x0000001f1410 1411/*****************************************************************************/1412#define AC97_CTL 0x91c1413/* Reserved [31:26] */1414#define FLD_AC97_UP2X_BW20K 0x020000001415#define FLD_AC97_UP2X_BYPASS 0x010000001416/* Reserved [23:17] */1417#define FLD_AC97_RST_ACL 0x000100001418/* Reserved [15:9] */1419#define FLD_AC97_WAKE_UP_SYNC 0x000001001420/* Reserved [7:1] */1421#define FLD_AC97_SHUTDOWN 0x000000011422 1423/* Cx231xx redefine */1424#define QPSK_IAGC_CTL1 0x94c1425#define QPSK_IAGC_CTL2 0x9501426#define QPSK_FEPR_FREQ 0x9541427#define QPSK_BTL_CTL1 0x9581428#define QPSK_BTL_CTL2 0x95c1429#define QPSK_CTL_CTL1 0x9601430#define QPSK_CTL_CTL2 0x9641431#define QPSK_MF_FAGC_CTL 0x9681432#define QPSK_EQ_CTL 0x96c1433#define QPSK_LOCK_CTL 0x9701434 1435/*****************************************************************************/1436#define FM1_DFT_CTL 0x9a81437#define FLD_FM1_DFT_THRESHOLD 0xffff00001438/* Reserved [15:8] */1439#define FLD_FM1_DFT_CMP_CTL 0x000000801440#define FLD_FM1_DFT_AVG 0x000000701441/* Reserved [3:1] */1442#define FLD_FM1_DFT_START 0x000000011443 1444/*****************************************************************************/1445#define FM1_DFT_STATUS 0x9ac1446#define FLD_FM1_DFT_DONE 0x800000001447/* Reserved [30:19] */1448#define FLD_FM_DFT_TH_CMP 0x000400001449#define FLD_FM1_DFT 0x0003ffff1450 1451/*****************************************************************************/1452#define FM2_DFT_CTL 0x9b01453#define FLD_FM2_DFT_THRESHOLD 0xffff00001454/* Reserved [15:8] */1455#define FLD_FM2_DFT_CMP_CTL 0x000000801456#define FLD_FM2_DFT_AVG 0x000000701457/* Reserved [3:1] */1458#define FLD_FM2_DFT_START 0x000000011459 1460/*****************************************************************************/1461#define FM2_DFT_STATUS 0x9b41462#define FLD_FM2_DFT_DONE 0x800000001463/* Reserved [30:19] */1464#define FLD_FM2_DFT_TH_CMP_STAT 0x000400001465#define FLD_FM2_DFT 0x0003ffff1466 1467/*****************************************************************************/1468/* Cx231xx redefine */1469#define AAGC_STATUS_REG 0x9b81470#define AAGC_STATUS 0x9b81471/* Reserved [31:27] */1472#define FLD_FM2_DAGC_OUT 0x070000001473/* Reserved [23:19] */1474#define FLD_FM1_DAGC_OUT 0x000700001475/* Reserved [15:6] */1476#define FLD_AFE_VGA_OUT 0x0000003f1477 1478/*****************************************************************************/1479#define MTS_GAIN_STATUS 0x9bc1480/* Reserved [31:14] */1481#define FLD_MTS_GAIN 0x00003fff1482 1483#define RDS_OUT 0x9c01484#define FLD_RDS_Q 0xffff00001485#define FLD_RDS_I 0x0000ffff1486 1487/*****************************************************************************/1488#define AUTOCONFIG_REG 0x9c41489/* Reserved [31:4] */1490#define FLD_AUTOCONFIG_MODE 0x0000000f1491 1492#define FM_AFC 0x9c81493#define FLD_FM2_AFC 0xffff00001494#define FLD_FM1_AFC 0x0000ffff1495 1496/*****************************************************************************/1497/* Cx231xx redefine */1498#define NEW_SPARE 0x9cc1499#define NEW_SPARE_REG 0x9cc1500 1501/*****************************************************************************/1502#define DBX_ADJ 0x9d01503/* Reserved [31:28] */1504#define FLD_DBX2_ADJ 0x0fff00001505/* Reserved [15:12] */1506#define FLD_DBX1_ADJ 0x00000fff1507 1508#define VID_FMT_AUTO 01509#define VID_FMT_NTSC_M 11510#define VID_FMT_NTSC_J 21511#define VID_FMT_NTSC_443 31512#define VID_FMT_PAL_BDGHI 41513#define VID_FMT_PAL_M 51514#define VID_FMT_PAL_N 61515#define VID_FMT_PAL_NC 71516#define VID_FMT_PAL_60 81517#define VID_FMT_SECAM 121518#define VID_FMT_SECAM_60 131519 1520#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */1521#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */1522#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */1523#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */1524 1525#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */1526#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */1527#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */1528 1529#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */1530#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */1531#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */1532 1533#define TWO_TAP_FILT 01534#define THREE_TAP_FILT 11535#define FOUR_TAP_FILT 21536#define FIVE_TAP_FILT 31537 1538#define AUD_CHAN_SRC_PARALLEL 01539#define AUD_CHAN_SRC_I2S_INPUT 11540#define AUD_CHAN_SRC_FLATIRON 21541#define AUD_CHAN_SRC_PARALLEL3 31542 1543#define OUT_MODE_601 01544#define OUT_MODE_656 11545#define OUT_MODE_VIP11 21546#define OUT_MODE_VIP20 31547 1548#define PHASE_INC_49MHZ 0x0df221549#define PHASE_INC_56MHZ 0x0fa5b1550#define PHASE_INC_28MHZ 0x0100001551 1552#endif1553