325 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * mxl111sf-phy.c - driver for the MaxLinear MXL111SF4 *5 * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>6 */7 8#include "mxl111sf-phy.h"9#include "mxl111sf-reg.h"10 11int mxl111sf_init_tuner_demod(struct mxl111sf_state *state)12{13 struct mxl111sf_reg_ctrl_info mxl_111_overwrite_default[] = {14 {0x07, 0xff, 0x0c},15 {0x58, 0xff, 0x9d},16 {0x09, 0xff, 0x00},17 {0x06, 0xff, 0x06},18 {0xc8, 0xff, 0x40}, /* ED_LE_WIN_OLD = 0 */19 {0x8d, 0x01, 0x01}, /* NEGATE_Q */20 {0x32, 0xff, 0xac}, /* DIG_RFREFSELECT = 12 */21 {0x42, 0xff, 0x43}, /* DIG_REG_AMP = 4 */22 {0x74, 0xff, 0xc4}, /* SSPUR_FS_PRIO = 4 */23 {0x71, 0xff, 0xe6}, /* SPUR_ROT_PRIO_VAL = 1 */24 {0x83, 0xff, 0x64}, /* INF_FILT1_THD_SC = 100 */25 {0x85, 0xff, 0x64}, /* INF_FILT2_THD_SC = 100 */26 {0x88, 0xff, 0xf0}, /* INF_THD = 240 */27 {0x6f, 0xf0, 0xb0}, /* DFE_DLY = 11 */28 {0x00, 0xff, 0x01}, /* Change to page 1 */29 {0x81, 0xff, 0x11}, /* DSM_FERR_BYPASS = 1 */30 {0xf4, 0xff, 0x07}, /* DIG_FREQ_CORR = 1 */31 {0xd4, 0x1f, 0x0f}, /* SPUR_TEST_NOISE_TH = 15 */32 {0xd6, 0xff, 0x0c}, /* SPUR_TEST_NOISE_PAPR = 12 */33 {0x00, 0xff, 0x00}, /* Change to page 0 */34 {0, 0, 0}35 };36 37 mxl_debug("()");38 39 return mxl111sf_ctrl_program_regs(state, mxl_111_overwrite_default);40}41 42int mxl1x1sf_soft_reset(struct mxl111sf_state *state)43{44 int ret;45 mxl_debug("()");46 47 ret = mxl111sf_write_reg(state, 0xff, 0x00); /* AIC */48 if (mxl_fail(ret))49 goto fail;50 ret = mxl111sf_write_reg(state, 0x02, 0x01); /* get out of reset */51 mxl_fail(ret);52fail:53 return ret;54}55 56int mxl1x1sf_set_device_mode(struct mxl111sf_state *state, int mode)57{58 int ret;59 60 mxl_debug("(%s)", MXL_SOC_MODE == mode ?61 "MXL_SOC_MODE" : "MXL_TUNER_MODE");62 63 /* set device mode */64 ret = mxl111sf_write_reg(state, 0x03,65 MXL_SOC_MODE == mode ? 0x01 : 0x00);66 if (mxl_fail(ret))67 goto fail;68 69 ret = mxl111sf_write_reg_mask(state,70 0x7d, 0x40, MXL_SOC_MODE == mode ?71 0x00 : /* enable impulse noise filter,72 INF_BYP = 0 */73 0x40); /* disable impulse noise filter,74 INF_BYP = 1 */75 if (mxl_fail(ret))76 goto fail;77 78 state->device_mode = mode;79fail:80 return ret;81}82 83/* power up tuner */84int mxl1x1sf_top_master_ctrl(struct mxl111sf_state *state, int onoff)85{86 mxl_debug("(%d)", onoff);87 88 return mxl111sf_write_reg(state, 0x01, onoff ? 0x01 : 0x00);89}90 91int mxl111sf_disable_656_port(struct mxl111sf_state *state)92{93 mxl_debug("()");94 95 return mxl111sf_write_reg_mask(state, 0x12, 0x04, 0x00);96}97 98int mxl111sf_enable_usb_output(struct mxl111sf_state *state)99{100 mxl_debug("()");101 102 return mxl111sf_write_reg_mask(state, 0x17, 0x40, 0x00);103}104 105/* initialize TSIF as input port of MxL1X1SF for MPEG2 data transfer */106int mxl111sf_config_mpeg_in(struct mxl111sf_state *state,107 unsigned int parallel_serial,108 unsigned int msb_lsb_1st,109 unsigned int clock_phase,110 unsigned int mpeg_valid_pol,111 unsigned int mpeg_sync_pol)112{113 int ret;114 u8 mode, tmp;115 116 mxl_debug("(%u,%u,%u,%u,%u)", parallel_serial, msb_lsb_1st,117 clock_phase, mpeg_valid_pol, mpeg_sync_pol);118 119 /* Enable PIN MUX */120 ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX);121 mxl_fail(ret);122 123 /* Configure MPEG Clock phase */124 mxl111sf_read_reg(state, V6_MPEG_IN_CLK_INV_REG, &mode);125 126 if (clock_phase == TSIF_NORMAL)127 mode &= ~V6_INVERTED_CLK_PHASE;128 else129 mode |= V6_INVERTED_CLK_PHASE;130 131 ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode);132 mxl_fail(ret);133 134 /* Configure data input mode, MPEG Valid polarity, MPEG Sync polarity135 * Get current configuration */136 ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode);137 mxl_fail(ret);138 139 /* Data Input mode */140 if (parallel_serial == TSIF_INPUT_PARALLEL) {141 /* Disable serial mode */142 mode &= ~V6_MPEG_IN_DATA_SERIAL;143 144 /* Enable Parallel mode */145 mode |= V6_MPEG_IN_DATA_PARALLEL;146 } else {147 /* Disable Parallel mode */148 mode &= ~V6_MPEG_IN_DATA_PARALLEL;149 150 /* Enable Serial Mode */151 mode |= V6_MPEG_IN_DATA_SERIAL;152 153 /* If serial interface is chosen, configure154 MSB or LSB order in transmission */155 ret = mxl111sf_read_reg(state,156 V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,157 &tmp);158 mxl_fail(ret);159 160 if (msb_lsb_1st == MPEG_SER_MSB_FIRST_ENABLED)161 tmp |= V6_MPEG_SER_MSB_FIRST;162 else163 tmp &= ~V6_MPEG_SER_MSB_FIRST;164 165 ret = mxl111sf_write_reg(state,166 V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,167 tmp);168 mxl_fail(ret);169 }170 171 /* MPEG Sync polarity */172 if (mpeg_sync_pol == TSIF_NORMAL)173 mode &= ~V6_INVERTED_MPEG_SYNC;174 else175 mode |= V6_INVERTED_MPEG_SYNC;176 177 /* MPEG Valid polarity */178 if (mpeg_valid_pol == 0)179 mode &= ~V6_INVERTED_MPEG_VALID;180 else181 mode |= V6_INVERTED_MPEG_VALID;182 183 ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode);184 mxl_fail(ret);185 186 return ret;187}188 189int mxl111sf_init_i2s_port(struct mxl111sf_state *state, u8 sample_size)190{191 static struct mxl111sf_reg_ctrl_info init_i2s[] = {192 {0x1b, 0xff, 0x1e}, /* pin mux mode, Choose 656/I2S input */193 {0x15, 0x60, 0x60}, /* Enable I2S */194 {0x17, 0xe0, 0x20}, /* Input, MPEG MODE USB,195 Inverted 656 Clock, I2S_SOFT_RESET,196 0 : Normal operation, 1 : Reset State */197#if 0198 {0x12, 0x01, 0x00}, /* AUDIO_IRQ_CLR (Overflow Indicator) */199#endif200 {0x00, 0xff, 0x02}, /* Change to Control Page */201 {0x26, 0x0d, 0x0d}, /* I2S_MODE & BT656_SRC_SEL for FPGA only */202 {0x00, 0xff, 0x00},203 {0, 0, 0}204 };205 int ret;206 207 mxl_debug("(0x%02x)", sample_size);208 209 ret = mxl111sf_ctrl_program_regs(state, init_i2s);210 if (mxl_fail(ret))211 goto fail;212 213 ret = mxl111sf_write_reg(state, V6_I2S_NUM_SAMPLES_REG, sample_size);214 mxl_fail(ret);215fail:216 return ret;217}218 219int mxl111sf_disable_i2s_port(struct mxl111sf_state *state)220{221 static struct mxl111sf_reg_ctrl_info disable_i2s[] = {222 {0x15, 0x40, 0x00},223 {0, 0, 0}224 };225 226 mxl_debug("()");227 228 return mxl111sf_ctrl_program_regs(state, disable_i2s);229}230 231int mxl111sf_config_i2s(struct mxl111sf_state *state,232 u8 msb_start_pos, u8 data_width)233{234 int ret;235 u8 tmp;236 237 mxl_debug("(0x%02x, 0x%02x)", msb_start_pos, data_width);238 239 ret = mxl111sf_read_reg(state, V6_I2S_STREAM_START_BIT_REG, &tmp);240 if (mxl_fail(ret))241 goto fail;242 243 tmp &= 0xe0;244 tmp |= msb_start_pos;245 ret = mxl111sf_write_reg(state, V6_I2S_STREAM_START_BIT_REG, tmp);246 if (mxl_fail(ret))247 goto fail;248 249 ret = mxl111sf_read_reg(state, V6_I2S_STREAM_END_BIT_REG, &tmp);250 if (mxl_fail(ret))251 goto fail;252 253 tmp &= 0xe0;254 tmp |= data_width;255 ret = mxl111sf_write_reg(state, V6_I2S_STREAM_END_BIT_REG, tmp);256 mxl_fail(ret);257fail:258 return ret;259}260 261int mxl111sf_config_spi(struct mxl111sf_state *state, int onoff)262{263 u8 val;264 int ret;265 266 mxl_debug("(%d)", onoff);267 268 ret = mxl111sf_write_reg(state, 0x00, 0x02);269 if (mxl_fail(ret))270 goto fail;271 272 ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val);273 if (mxl_fail(ret))274 goto fail;275 276 if (onoff)277 val |= 0x04;278 else279 val &= ~0x04;280 281 ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val);282 if (mxl_fail(ret))283 goto fail;284 285 ret = mxl111sf_write_reg(state, 0x00, 0x00);286 mxl_fail(ret);287fail:288 return ret;289}290 291int mxl111sf_idac_config(struct mxl111sf_state *state,292 u8 control_mode, u8 current_setting,293 u8 current_value, u8 hysteresis_value)294{295 int ret;296 u8 val;297 /* current value will be set for both automatic & manual IDAC control */298 val = current_value;299 300 if (control_mode == IDAC_MANUAL_CONTROL) {301 /* enable manual control of IDAC */302 val |= IDAC_MANUAL_CONTROL_BIT_MASK;303 304 if (current_setting == IDAC_CURRENT_SINKING_ENABLE)305 /* enable current sinking in manual mode */306 val |= IDAC_CURRENT_SINKING_BIT_MASK;307 else308 /* disable current sinking in manual mode */309 val &= ~IDAC_CURRENT_SINKING_BIT_MASK;310 } else {311 /* disable manual control of IDAC */312 val &= ~IDAC_MANUAL_CONTROL_BIT_MASK;313 314 /* set hysteresis value reg: 0x0B<5:0> */315 ret = mxl111sf_write_reg(state, V6_IDAC_HYSTERESIS_REG,316 (hysteresis_value & 0x3F));317 mxl_fail(ret);318 }319 320 ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val);321 mxl_fail(ret);322 323 return ret;324}325