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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * mxl111sf-reg.h - driver for the MaxLinear MXL111SF4 *5 * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>6 */7 8#ifndef _DVB_USB_MXL111SF_REG_H_9#define _DVB_USB_MXL111SF_REG_H_10 11#define CHIP_ID_REG 0xFC12#define TOP_CHIP_REV_ID_REG 0xFA13 14#define V6_SNR_RB_LSB_REG 0x2715#define V6_SNR_RB_MSB_REG 0x2816 17#define V6_N_ACCUMULATE_REG 0x1118#define V6_RS_AVG_ERRORS_LSB_REG 0x2C19#define V6_RS_AVG_ERRORS_MSB_REG 0x2D20 21#define V6_IRQ_STATUS_REG 0x2422#define IRQ_MASK_FEC_LOCK 0x1023 24#define V6_SYNC_LOCK_REG 0x2825#define SYNC_LOCK_MASK 0x1026 27#define V6_RS_LOCK_DET_REG 0x2828#define RS_LOCK_DET_MASK 0x0829 30#define V6_INITACQ_NODETECT_REG 0x2031#define V6_FORCE_NFFT_CPSIZE_REG 0x2032 33#define V6_CODE_RATE_TPS_REG 0x2934#define V6_CODE_RATE_TPS_MASK 0x0735 36 37#define V6_CP_LOCK_DET_REG 0x2838#define V6_CP_LOCK_DET_MASK 0x0439 40#define V6_TPS_HIERACHY_REG 0x2941#define V6_TPS_HIERARCHY_INFO_MASK 0x4042 43#define V6_MODORDER_TPS_REG 0x2A44#define V6_PARAM_CONSTELLATION_MASK 0x3045 46#define V6_MODE_TPS_REG 0x2A47#define V6_PARAM_FFT_MODE_MASK 0x0C48 49 50#define V6_CP_TPS_REG 0x2951#define V6_PARAM_GI_MASK 0x3052 53#define V6_TPS_LOCK_REG 0x2A54#define V6_PARAM_TPS_LOCK_MASK 0x4055 56#define V6_FEC_PER_COUNT_REG 0x2E57#define V6_FEC_PER_SCALE_REG 0x2B58#define V6_FEC_PER_SCALE_MASK 0x0359#define V6_FEC_PER_CLR_REG 0x2060#define V6_FEC_PER_CLR_MASK 0x0161 62#define V6_PIN_MUX_MODE_REG 0x1B63#define V6_ENABLE_PIN_MUX 0x1E64 65#define V6_I2S_NUM_SAMPLES_REG 0x1666 67#define V6_MPEG_IN_CLK_INV_REG 0x1768#define V6_MPEG_IN_CTRL_REG 0x1869 70#define V6_INVERTED_CLK_PHASE 0x2071#define V6_MPEG_IN_DATA_PARALLEL 0x0172#define V6_MPEG_IN_DATA_SERIAL 0x0273 74#define V6_INVERTED_MPEG_SYNC 0x0475#define V6_INVERTED_MPEG_VALID 0x0876 77#define TSIF_INPUT_PARALLEL 078#define TSIF_INPUT_SERIAL 179#define TSIF_NORMAL 080 81#define V6_MPEG_INOUT_BIT_ORDER_CTRL_REG 0x1982#define V6_MPEG_SER_MSB_FIRST 0x8083#define MPEG_SER_MSB_FIRST_ENABLED 0x0184 85#define V6_656_I2S_BUFF_STATUS_REG 0x2F86#define V6_656_OVERFLOW_MASK_BIT 0x0887#define V6_I2S_OVERFLOW_MASK_BIT 0x0188 89#define V6_I2S_STREAM_START_BIT_REG 0x1490#define V6_I2S_STREAM_END_BIT_REG 0x1591#define I2S_RIGHT_JUSTIFIED 092#define I2S_LEFT_JUSTIFIED 193#define I2S_DATA_FORMAT 294 95#define V6_TUNER_LOOP_THRU_CONTROL_REG 0x0996#define V6_ENABLE_LOOP_THRU 0x0197 98#define TOTAL_NUM_IF_OUTPUT_FREQ 1699 100#define TUNER_NORMAL_IF_SPECTRUM 0x0101#define TUNER_INVERT_IF_SPECTRUM 0x10102 103#define V6_TUNER_IF_SEL_REG 0x06104#define V6_TUNER_IF_FCW_REG 0x3C105#define V6_TUNER_IF_FCW_BYP_REG 0x3D106#define V6_RF_LOCK_STATUS_REG 0x23107 108#define NUM_DIG_TV_CHANNEL 1000109 110#define V6_DIG_CLK_FREQ_SEL_REG 0x07111#define V6_REF_SYNTH_INT_REG 0x5C112#define V6_REF_SYNTH_REMAIN_REG 0x58113#define V6_DIG_RFREFSELECT_REG 0x32114#define V6_XTAL_CLK_OUT_GAIN_REG 0x31115#define V6_TUNER_LOOP_THRU_CTRL_REG 0x09116#define V6_DIG_XTAL_ENABLE_REG 0x06117#define V6_DIG_XTAL_BIAS_REG 0x66118#define V6_XTAL_CAP_REG 0x08119 120#define V6_GPO_CTRL_REG 0x18121#define MXL_GPO_0 0x00122#define MXL_GPO_1 0x01123#define V6_GPO_0_MASK 0x10124#define V6_GPO_1_MASK 0x20125 126#define V6_111SF_GPO_CTRL_REG 0x19127#define MXL_111SF_GPO_1 0x00128#define MXL_111SF_GPO_2 0x01129#define MXL_111SF_GPO_3 0x02130#define MXL_111SF_GPO_4 0x03131#define MXL_111SF_GPO_5 0x04132#define MXL_111SF_GPO_6 0x05133#define MXL_111SF_GPO_7 0x06134 135#define MXL_111SF_GPO_0_MASK 0x01136#define MXL_111SF_GPO_1_MASK 0x02137#define MXL_111SF_GPO_2_MASK 0x04138#define MXL_111SF_GPO_3_MASK 0x08139#define MXL_111SF_GPO_4_MASK 0x10140#define MXL_111SF_GPO_5_MASK 0x20141#define MXL_111SF_GPO_6_MASK 0x40142 143#define V6_ATSC_CONFIG_REG 0x0A144 145#define MXL_MODE_REG 0x03146#define START_TUNE_REG 0x1C147 148#define V6_IDAC_HYSTERESIS_REG 0x0B149#define V6_IDAC_SETTINGS_REG 0x0C150#define IDAC_MANUAL_CONTROL 1151#define IDAC_CURRENT_SINKING_ENABLE 1152#define IDAC_MANUAL_CONTROL_BIT_MASK 0x80153#define IDAC_CURRENT_SINKING_BIT_MASK 0x40154 155#define V8_SPI_MODE_REG 0xE9156 157#define V6_DIG_RF_PWR_LSB_REG 0x46158#define V6_DIG_RF_PWR_MSB_REG 0x47159 160#endif /* _DVB_USB_MXL111SF_REG_H_ */161