302 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2 3/*4 * em28xx-reg.h - Register definitions for em28xx driver5 */6 7#define EM_GPIO_0 ((unsigned char)BIT(0))8#define EM_GPIO_1 ((unsigned char)BIT(1))9#define EM_GPIO_2 ((unsigned char)BIT(2))10#define EM_GPIO_3 ((unsigned char)BIT(3))11#define EM_GPIO_4 ((unsigned char)BIT(4))12#define EM_GPIO_5 ((unsigned char)BIT(5))13#define EM_GPIO_6 ((unsigned char)BIT(6))14#define EM_GPIO_7 ((unsigned char)BIT(7))15 16#define EM_GPO_0 ((unsigned char)BIT(0))17#define EM_GPO_1 ((unsigned char)BIT(1))18#define EM_GPO_2 ((unsigned char)BIT(2))19#define EM_GPO_3 ((unsigned char)BIT(3))20 21/* em28xx endpoints */22/* 0x82: (always ?) analog */23#define EM28XX_EP_AUDIO 0x8324/* 0x84: digital or analog */25 26/* em2800 registers */27#define EM2800_R08_AUDIOSRC 0x0828 29/* em28xx registers */30 31#define EM28XX_R00_CHIPCFG 0x0032 33/* em28xx Chip Configuration 0x00 */34#define EM2860_CHIPCFG_VENDOR_AUDIO 0x8035#define EM2860_CHIPCFG_I2S_VOLUME_CAPABLE 0x4036#define EM2820_CHIPCFG_I2S_3_SAMPRATES 0x3037#define EM2860_CHIPCFG_I2S_5_SAMPRATES 0x3038#define EM2820_CHIPCFG_I2S_1_SAMPRATE 0x2039#define EM2860_CHIPCFG_I2S_3_SAMPRATES 0x2040#define EM28XX_CHIPCFG_AC97 0x1041#define EM28XX_CHIPCFG_AUDIOMASK 0x3042 43#define EM28XX_R01_CHIPCFG2 0x0144 45/* em28xx Chip Configuration 2 0x01 */46#define EM28XX_CHIPCFG2_TS_PRESENT 0x1047#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK 0x0c /* bits 3-2 */48#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF 0x0049#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF 0x0450#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF 0x0851#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF 0x0c52#define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK 0x03 /* bits 0-1 */53#define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 0x0054#define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 0x0155#define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 0x0256#define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 0x0357 58/* GPIO/GPO registers */59#define EM2880_R04_GPO 0x04 /* em2880-em2883 only */60#define EM2820_R08_GPIO_CTRL 0x08 /* em2820-em2873/83 only */61#define EM2820_R09_GPIO_STATE 0x09 /* em2820-em2873/83 only */62 63#define EM28XX_R06_I2C_CLK 0x0664 65/* em28xx I2C Clock Register (0x06) */66#define EM28XX_I2C_CLK_ACK_LAST_READ 0x8067#define EM28XX_I2C_CLK_WAIT_ENABLE 0x4068#define EM28XX_I2C_EEPROM_ON_BOARD 0x0869#define EM28XX_I2C_EEPROM_KEY_VALID 0x0470#define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c buses */71#define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */72#define EM28XX_I2C_FREQ_25_KHZ 0x0273#define EM28XX_I2C_FREQ_400_KHZ 0x0174#define EM28XX_I2C_FREQ_100_KHZ 0x0075 76#define EM28XX_R0A_CHIPID 0x0a77#define EM28XX_R0C_USBSUSP 0x0c78#define EM28XX_R0C_USBSUSP_SNAPSHOT 0x20 /* 1=button pressed, needs reset */79 80#define EM28XX_R0E_AUDIOSRC 0x0e81#define EM28XX_R0F_XCLK 0x0f82 83/* em28xx XCLK Register (0x0f) */84#define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */85#define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */86#define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */87#define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x1088#define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */89#define EM28XX_XCLK_FREQUENCY_15MHZ 0x0190#define EM28XX_XCLK_FREQUENCY_10MHZ 0x0291#define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x0392#define EM28XX_XCLK_FREQUENCY_6MHZ 0x0493#define EM28XX_XCLK_FREQUENCY_5MHZ 0x0594#define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x0695#define EM28XX_XCLK_FREQUENCY_12MHZ 0x0796#define EM28XX_XCLK_FREQUENCY_20MHZ 0x0897#define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x0998#define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a99#define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b100 101#define EM28XX_R10_VINMODE 0x10102 /* used by all non-camera devices: */103#define EM28XX_VINMODE_YUV422_CbYCrY 0x10104 /* used by camera devices: */105#define EM28XX_VINMODE_YUV422_YUYV 0x08106#define EM28XX_VINMODE_YUV422_YVYU 0x09107#define EM28XX_VINMODE_YUV422_UYVY 0x0a108#define EM28XX_VINMODE_YUV422_VYUY 0x0b109#define EM28XX_VINMODE_RGB8_BGGR 0x0c110#define EM28XX_VINMODE_RGB8_GRBG 0x0d111#define EM28XX_VINMODE_RGB8_GBRG 0x0e112#define EM28XX_VINMODE_RGB8_RGGB 0x0f113 /*114 * apparently:115 * bit 0: swap component 1+2 with 3+4116 * => e.g.: YUYV => YVYU, BGGR => GRBG117 * bit 1: swap component 1 with 2 and 3 with 4118 * => e.g.: YUYV => UYVY, BGGR => GBRG119 */120 121#define EM28XX_R11_VINCTRL 0x11122 123/* em28xx Video Input Control Register 0x11 */124#define EM28XX_VINCTRL_VBI_SLICED 0x80125#define EM28XX_VINCTRL_VBI_RAW 0x40126#define EM28XX_VINCTRL_VOUT_MODE_IN 0x20 /* HREF,VREF,VACT in output */127#define EM28XX_VINCTRL_CCIR656_ENABLE 0x10128#define EM28XX_VINCTRL_VBI_16BIT_RAW 0x08 /* otherwise 8-bit raw */129#define EM28XX_VINCTRL_FID_ON_HREF 0x04130#define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02131#define EM28XX_VINCTRL_INTERLACED 0x01132 133#define EM28XX_R12_VINENABLE 0x12 /* */134 135#define EM28XX_R14_GAMMA 0x14136#define EM28XX_R15_RGAIN 0x15137#define EM28XX_R16_GGAIN 0x16138#define EM28XX_R17_BGAIN 0x17139#define EM28XX_R18_ROFFSET 0x18140#define EM28XX_R19_GOFFSET 0x19141#define EM28XX_R1A_BOFFSET 0x1a142 143#define EM28XX_R1B_OFLOW 0x1b144#define EM28XX_R1C_HSTART 0x1c145#define EM28XX_R1D_VSTART 0x1d146#define EM28XX_R1E_CWIDTH 0x1e147#define EM28XX_R1F_CHEIGHT 0x1f148 149#define EM28XX_R20_YGAIN 0x20 /* contrast [0:4] */150#define CONTRAST_DEFAULT 0x10151 152#define EM28XX_R21_YOFFSET 0x21 /* brightness */ /* signed */153#define BRIGHTNESS_DEFAULT 0x00154 155#define EM28XX_R22_UVGAIN 0x22 /* saturation [0:4] */156#define SATURATION_DEFAULT 0x10157 158#define EM28XX_R23_UOFFSET 0x23 /* blue balance */ /* signed */159#define BLUE_BALANCE_DEFAULT 0x00160 161#define EM28XX_R24_VOFFSET 0x24 /* red balance */ /* signed */162#define RED_BALANCE_DEFAULT 0x00163 164#define EM28XX_R25_SHARPNESS 0x25 /* sharpness [0:4] */165#define SHARPNESS_DEFAULT 0x00166 167#define EM28XX_R26_COMPR 0x26168#define EM28XX_R27_OUTFMT 0x27169 170/* em28xx Output Format Register (0x27) */171#define EM28XX_OUTFMT_RGB_8_RGRG 0x00172#define EM28XX_OUTFMT_RGB_8_GRGR 0x01173#define EM28XX_OUTFMT_RGB_8_GBGB 0x02174#define EM28XX_OUTFMT_RGB_8_BGBG 0x03175#define EM28XX_OUTFMT_RGB_16_656 0x04176#define EM28XX_OUTFMT_RGB_8_BAYER 0x08 /* Pattern in Reg 0x10[1-0] */177#define EM28XX_OUTFMT_YUV211 0x10178#define EM28XX_OUTFMT_YUV422_Y0UY1V 0x14179#define EM28XX_OUTFMT_YUV422_Y1UY0V 0x15180#define EM28XX_OUTFMT_YUV411 0x18181 182#define EM28XX_R28_XMIN 0x28183#define EM28XX_R29_XMAX 0x29184#define EM28XX_R2A_YMIN 0x2a185#define EM28XX_R2B_YMAX 0x2b186 187#define EM28XX_R30_HSCALELOW 0x30188#define EM28XX_R31_HSCALEHIGH 0x31189#define EM28XX_R32_VSCALELOW 0x32190#define EM28XX_R33_VSCALEHIGH 0x33191#define EM28XX_HVSCALE_MAX 0x3fff /* => 20% */192 193#define EM28XX_R34_VBI_START_H 0x34194#define EM28XX_R35_VBI_START_V 0x35195/*196 * NOTE: the EM276x (and EM25xx, EM277x/8x ?) (camera bridges) use these197 * registers for a different unknown purpose.198 * => register 0x34 is set to capture width / 16199 * => register 0x35 is set to capture height / 16200 */201 202#define EM28XX_R36_VBI_WIDTH 0x36203#define EM28XX_R37_VBI_HEIGHT 0x37204 205#define EM28XX_R40_AC97LSB 0x40206#define EM28XX_R41_AC97MSB 0x41207#define EM28XX_R42_AC97ADDR 0x42208#define EM28XX_R43_AC97BUSY 0x43209 210#define EM28XX_R45_IR 0x45211 /*212 * 0x45 bit 7 - parity bit213 * bits 6-0 - count214 * 0x46 IR brand215 * 0x47 IR data216 */217 218/* em2874 registers */219#define EM2874_R50_IR_CONFIG 0x50220#define EM2874_R51_IR 0x51221#define EM2874_R5D_TS1_PKT_SIZE 0x5d222#define EM2874_R5E_TS2_PKT_SIZE 0x5e223 /*224 * For both TS1 and TS2, In isochronous mode:225 * 0x01 188 bytes226 * 0x02 376 bytes227 * 0x03 564 bytes228 * 0x04 752 bytes229 * 0x05 940 bytes230 * In bulk mode:231 * 0x01..0xff total packet count in 188-byte232 */233 234#define EM2874_R5F_TS_ENABLE 0x5f235 236/* em2874/174/84, em25xx, em276x/7x/8x GPIO registers */237/*238 * NOTE: not all ports are bonded out;239 * Some ports are multiplexed with special function I/O240 */241#define EM2874_R80_GPIO_P0_CTRL 0x80242#define EM2874_R81_GPIO_P1_CTRL 0x81243#define EM2874_R82_GPIO_P2_CTRL 0x82244#define EM2874_R83_GPIO_P3_CTRL 0x83245#define EM2874_R84_GPIO_P0_STATE 0x84246#define EM2874_R85_GPIO_P1_STATE 0x85247#define EM2874_R86_GPIO_P2_STATE 0x86248#define EM2874_R87_GPIO_P3_STATE 0x87249 250/* em2874 IR config register (0x50) */251#define EM2874_IR_NEC 0x00252#define EM2874_IR_NEC_NO_PARITY 0x01253#define EM2874_IR_RC5 0x04254#define EM2874_IR_RC6_MODE_0 0x08255#define EM2874_IR_RC6_MODE_6A 0x0b256 257/* em2874 Transport Stream Enable Register (0x5f) */258#define EM2874_TS1_CAPTURE_ENABLE ((unsigned char)BIT(0))259#define EM2874_TS1_FILTER_ENABLE ((unsigned char)BIT(1))260#define EM2874_TS1_NULL_DISCARD ((unsigned char)BIT(2))261#define EM2874_TS2_CAPTURE_ENABLE ((unsigned char)BIT(4))262#define EM2874_TS2_FILTER_ENABLE ((unsigned char)BIT(5))263#define EM2874_TS2_NULL_DISCARD ((unsigned char)BIT(6))264 265/* register settings */266#define EM2800_AUDIO_SRC_TUNER 0x0d267#define EM2800_AUDIO_SRC_LINE 0x0c268#define EM28XX_AUDIO_SRC_TUNER 0xc0269#define EM28XX_AUDIO_SRC_LINE 0x80270 271/* FIXME: Need to be populated with the other chip ID's */272enum em28xx_chip_id {273 CHIP_ID_EM2800 = 7,274 CHIP_ID_EM2710 = 17,275 CHIP_ID_EM2820 = 18, /* Also used by some em2710 */276 CHIP_ID_EM2840 = 20,277 CHIP_ID_EM2750 = 33,278 CHIP_ID_EM2860 = 34,279 CHIP_ID_EM2870 = 35,280 CHIP_ID_EM2883 = 36,281 CHIP_ID_EM2765 = 54,282 CHIP_ID_EM2874 = 65,283 CHIP_ID_EM2884 = 68,284 CHIP_ID_EM28174 = 113,285 CHIP_ID_EM28178 = 114,286};287 288/*289 * Registers used by em202290 */291 292/* EMP202 vendor registers */293#define EM202_EXT_MODEM_CTRL 0x3e294#define EM202_GPIO_CONF 0x4c295#define EM202_GPIO_POLARITY 0x4e296#define EM202_GPIO_STICKY 0x50297#define EM202_GPIO_MASK 0x52298#define EM202_GPIO_STATUS 0x54299#define EM202_SPDIF_OUT_SEL 0x6a300#define EM202_ANTIPOP 0x72301#define EM202_EAPD_GPIO_ACCESS 0x74302