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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Defines for the EMIF driver4 *5 * Copyright (C) 2012 Texas Instruments, Inc.6 *7 * Benoit Cousson (b-cousson@ti.com)8 */9#ifndef __EMIF_H10#define __EMIF_H11 12/*13 * Maximum number of different frequencies supported by EMIF driver14 * Determines the number of entries in the pointer array for register15 * cache16 */17#define EMIF_MAX_NUM_FREQUENCIES 618 19/* State of the core voltage */20#define DDR_VOLTAGE_STABLE 021#define DDR_VOLTAGE_RAMPING 122 23/* Defines for timing De-rating */24#define EMIF_NORMAL_TIMINGS 025#define EMIF_DERATED_TIMINGS 126 27/* Length of the forced read idle period in terms of cycles */28#define EMIF_READ_IDLE_LEN_VAL 529 30/*31 * forced read idle interval to be used when voltage32 * is changed as part of DVFS/DPS - 1ms33 */34#define READ_IDLE_INTERVAL_DVFS (1*1000000)35 36/*37 * Forced read idle interval to be used when voltage is stable38 * 50us - or maximum value will do39 */40#define READ_IDLE_INTERVAL_NORMAL (50*1000000)41 42/* DLL calibration interval when voltage is NOT stable - 1us */43#define DLL_CALIB_INTERVAL_DVFS (1*1000000)44 45#define DLL_CALIB_ACK_WAIT_VAL 546 47/* Interval between ZQCS commands - hw team recommended value */48#define EMIF_ZQCS_INTERVAL_US (50*1000)49/* Enable ZQ Calibration on exiting Self-refresh */50#define ZQ_SFEXITEN_ENABLE 151/*52 * ZQ Calibration simultaneously on both chip-selects:53 * Needs one calibration resistor per CS54 */55#define ZQ_DUALCALEN_DISABLE 056#define ZQ_DUALCALEN_ENABLE 157 58#define T_ZQCS_DEFAULT_NS 9059#define T_ZQCL_DEFAULT_NS 36060#define T_ZQINIT_DEFAULT_NS 100061 62/* DPD_EN */63#define DPD_DISABLE 064#define DPD_ENABLE 165 66/*67 * Default values for the low-power entry to be used if not provided by user.68 * OMAP4/5 has a hw bug(i735) due to which this value can not be less than 51269 * Timeout values are in DDR clock 'cycles' and frequency threshold in Hz70 */71#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 204872#define EMIF_LP_MODE_TIMEOUT_POWER 51273#define EMIF_LP_MODE_FREQ_THRESHOLD 40000000074 75/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */76#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF00077#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x4178#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x8079#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF80 81/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */82#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E08420083#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 1000084 85/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */86#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 36087 88#define EMIF_T_CSTA 389#define EMIF_T_PDLL_UL 12890 91/* External PHY control registers magic values */92#define EMIF_EXT_PHY_CTRL_1_VAL 0x0402008093#define EMIF_EXT_PHY_CTRL_5_VAL 0x0401004094#define EMIF_EXT_PHY_CTRL_6_VAL 0x0100401095#define EMIF_EXT_PHY_CTRL_7_VAL 0x0000100496#define EMIF_EXT_PHY_CTRL_8_VAL 0x0401004097#define EMIF_EXT_PHY_CTRL_9_VAL 0x0100401098#define EMIF_EXT_PHY_CTRL_10_VAL 0x0000100499#define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000100#define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000101#define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000102#define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080103#define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800104#define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040105#define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001106#define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150107#define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0108#define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540109#define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000110#define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000111#define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000112#define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077113 114#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200115 116/* Registers offset */117#define EMIF_MODULE_ID_AND_REVISION 0x0000118#define EMIF_STATUS 0x0004119#define EMIF_SDRAM_CONFIG 0x0008120#define EMIF_SDRAM_CONFIG_2 0x000c121#define EMIF_SDRAM_REFRESH_CONTROL 0x0010122#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014123#define EMIF_SDRAM_TIMING_1 0x0018124#define EMIF_SDRAM_TIMING_1_SHDW 0x001c125#define EMIF_SDRAM_TIMING_2 0x0020126#define EMIF_SDRAM_TIMING_2_SHDW 0x0024127#define EMIF_SDRAM_TIMING_3 0x0028128#define EMIF_SDRAM_TIMING_3_SHDW 0x002c129#define EMIF_LPDDR2_NVM_TIMING 0x0030130#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034131#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038132#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c133#define EMIF_LPDDR2_MODE_REG_DATA 0x0040134#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050135#define EMIF_OCP_CONFIG 0x0054136#define EMIF_OCP_CONFIG_VALUE_1 0x0058137#define EMIF_OCP_CONFIG_VALUE_2 0x005c138#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060139#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064140#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068141#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c142#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070143#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074144#define EMIF_PERFORMANCE_COUNTER_1 0x0080145#define EMIF_PERFORMANCE_COUNTER_2 0x0084146#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088147#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c148#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090149#define EMIF_MISC_REG 0x0094150#define EMIF_DLL_CALIB_CTRL 0x0098151#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c152#define EMIF_END_OF_INTERRUPT 0x00a0153#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4154#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8155#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac156#define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0157#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4158#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8159#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc160#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0161#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8162#define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc163#define EMIF_OCP_ERROR_LOG 0x00d0164#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4165#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8166#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc167#define EMIF_DDR_PHY_CTRL_1 0x00e4168#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8169#define EMIF_DDR_PHY_CTRL_2 0x00ec170#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100171#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104172#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108173#define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120174#define EMIF_COS_CONFIG 0x0124175#define EMIF_PHY_STATUS_1 0x0140176#define EMIF_PHY_STATUS_2 0x0144177#define EMIF_PHY_STATUS_3 0x0148178#define EMIF_PHY_STATUS_4 0x014c179#define EMIF_PHY_STATUS_5 0x0150180#define EMIF_PHY_STATUS_6 0x0154181#define EMIF_PHY_STATUS_7 0x0158182#define EMIF_PHY_STATUS_8 0x015c183#define EMIF_PHY_STATUS_9 0x0160184#define EMIF_PHY_STATUS_10 0x0164185#define EMIF_PHY_STATUS_11 0x0168186#define EMIF_PHY_STATUS_12 0x016c187#define EMIF_PHY_STATUS_13 0x0170188#define EMIF_PHY_STATUS_14 0x0174189#define EMIF_PHY_STATUS_15 0x0178190#define EMIF_PHY_STATUS_16 0x017c191#define EMIF_PHY_STATUS_17 0x0180192#define EMIF_PHY_STATUS_18 0x0184193#define EMIF_PHY_STATUS_19 0x0188194#define EMIF_PHY_STATUS_20 0x018c195#define EMIF_PHY_STATUS_21 0x0190196#define EMIF_EXT_PHY_CTRL_1 0x0200197#define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204198#define EMIF_EXT_PHY_CTRL_2 0x0208199#define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c200#define EMIF_EXT_PHY_CTRL_3 0x0210201#define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214202#define EMIF_EXT_PHY_CTRL_4 0x0218203#define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c204#define EMIF_EXT_PHY_CTRL_5 0x0220205#define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224206#define EMIF_EXT_PHY_CTRL_6 0x0228207#define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c208#define EMIF_EXT_PHY_CTRL_7 0x0230209#define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234210#define EMIF_EXT_PHY_CTRL_8 0x0238211#define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c212#define EMIF_EXT_PHY_CTRL_9 0x0240213#define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244214#define EMIF_EXT_PHY_CTRL_10 0x0248215#define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c216#define EMIF_EXT_PHY_CTRL_11 0x0250217#define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254218#define EMIF_EXT_PHY_CTRL_12 0x0258219#define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c220#define EMIF_EXT_PHY_CTRL_13 0x0260221#define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264222#define EMIF_EXT_PHY_CTRL_14 0x0268223#define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c224#define EMIF_EXT_PHY_CTRL_15 0x0270225#define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274226#define EMIF_EXT_PHY_CTRL_16 0x0278227#define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c228#define EMIF_EXT_PHY_CTRL_17 0x0280229#define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284230#define EMIF_EXT_PHY_CTRL_18 0x0288231#define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c232#define EMIF_EXT_PHY_CTRL_19 0x0290233#define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294234#define EMIF_EXT_PHY_CTRL_20 0x0298235#define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c236#define EMIF_EXT_PHY_CTRL_21 0x02a0237#define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4238#define EMIF_EXT_PHY_CTRL_22 0x02a8239#define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac240#define EMIF_EXT_PHY_CTRL_23 0x02b0241#define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4242#define EMIF_EXT_PHY_CTRL_24 0x02b8243#define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc244#define EMIF_EXT_PHY_CTRL_25 0x02c0245#define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4246#define EMIF_EXT_PHY_CTRL_26 0x02c8247#define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc248#define EMIF_EXT_PHY_CTRL_27 0x02d0249#define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4250#define EMIF_EXT_PHY_CTRL_28 0x02d8251#define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc252#define EMIF_EXT_PHY_CTRL_29 0x02e0253#define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4254#define EMIF_EXT_PHY_CTRL_30 0x02e8255#define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec256 257/* Registers shifts and masks */258 259/* EMIF_MODULE_ID_AND_REVISION */260#define SCHEME_SHIFT 30261#define SCHEME_MASK (0x3 << 30)262#define MODULE_ID_SHIFT 16263#define MODULE_ID_MASK (0xfff << 16)264#define RTL_VERSION_SHIFT 11265#define RTL_VERSION_MASK (0x1f << 11)266#define MAJOR_REVISION_SHIFT 8267#define MAJOR_REVISION_MASK (0x7 << 8)268#define MINOR_REVISION_SHIFT 0269#define MINOR_REVISION_MASK (0x3f << 0)270 271/* STATUS */272#define BE_SHIFT 31273#define BE_MASK (1 << 31)274#define DUAL_CLK_MODE_SHIFT 30275#define DUAL_CLK_MODE_MASK (1 << 30)276#define FAST_INIT_SHIFT 29277#define FAST_INIT_MASK (1 << 29)278#define RDLVLGATETO_SHIFT 6279#define RDLVLGATETO_MASK (1 << 6)280#define RDLVLTO_SHIFT 5281#define RDLVLTO_MASK (1 << 5)282#define WRLVLTO_SHIFT 4283#define WRLVLTO_MASK (1 << 4)284#define PHY_DLL_READY_SHIFT 2285#define PHY_DLL_READY_MASK (1 << 2)286 287/* SDRAM_CONFIG */288#define SDRAM_TYPE_SHIFT 29289#define SDRAM_TYPE_MASK (0x7 << 29)290#define IBANK_POS_SHIFT 27291#define IBANK_POS_MASK (0x3 << 27)292#define DDR_TERM_SHIFT 24293#define DDR_TERM_MASK (0x7 << 24)294#define DDR2_DDQS_SHIFT 23295#define DDR2_DDQS_MASK (1 << 23)296#define DYN_ODT_SHIFT 21297#define DYN_ODT_MASK (0x3 << 21)298#define DDR_DISABLE_DLL_SHIFT 20299#define DDR_DISABLE_DLL_MASK (1 << 20)300#define SDRAM_DRIVE_SHIFT 18301#define SDRAM_DRIVE_MASK (0x3 << 18)302#define CWL_SHIFT 16303#define CWL_MASK (0x3 << 16)304#define NARROW_MODE_SHIFT 14305#define NARROW_MODE_MASK (0x3 << 14)306#define CL_SHIFT 10307#define CL_MASK (0xf << 10)308#define ROWSIZE_SHIFT 7309#define ROWSIZE_MASK (0x7 << 7)310#define IBANK_SHIFT 4311#define IBANK_MASK (0x7 << 4)312#define EBANK_SHIFT 3313#define EBANK_MASK (1 << 3)314#define PAGESIZE_SHIFT 0315#define PAGESIZE_MASK (0x7 << 0)316 317/* SDRAM_CONFIG_2 */318#define CS1NVMEN_SHIFT 30319#define CS1NVMEN_MASK (1 << 30)320#define EBANK_POS_SHIFT 27321#define EBANK_POS_MASK (1 << 27)322#define RDBNUM_SHIFT 4323#define RDBNUM_MASK (0x3 << 4)324#define RDBSIZE_SHIFT 0325#define RDBSIZE_MASK (0x7 << 0)326 327/* SDRAM_REFRESH_CONTROL */328#define INITREF_DIS_SHIFT 31329#define INITREF_DIS_MASK (1 << 31)330#define SRT_SHIFT 29331#define SRT_MASK (1 << 29)332#define ASR_SHIFT 28333#define ASR_MASK (1 << 28)334#define PASR_SHIFT 24335#define PASR_MASK (0x7 << 24)336#define REFRESH_RATE_SHIFT 0337#define REFRESH_RATE_MASK (0xffff << 0)338 339/* SDRAM_TIMING_1 */340#define T_RTW_SHIFT 29341#define T_RTW_MASK (0x7 << 29)342#define T_RP_SHIFT 25343#define T_RP_MASK (0xf << 25)344#define T_RCD_SHIFT 21345#define T_RCD_MASK (0xf << 21)346#define T_WR_SHIFT 17347#define T_WR_MASK (0xf << 17)348#define T_RAS_SHIFT 12349#define T_RAS_MASK (0x1f << 12)350#define T_RC_SHIFT 6351#define T_RC_MASK (0x3f << 6)352#define T_RRD_SHIFT 3353#define T_RRD_MASK (0x7 << 3)354#define T_WTR_SHIFT 0355#define T_WTR_MASK (0x7 << 0)356 357/* SDRAM_TIMING_2 */358#define T_XP_SHIFT 28359#define T_XP_MASK (0x7 << 28)360#define T_ODT_SHIFT 25361#define T_ODT_MASK (0x7 << 25)362#define T_XSNR_SHIFT 16363#define T_XSNR_MASK (0x1ff << 16)364#define T_XSRD_SHIFT 6365#define T_XSRD_MASK (0x3ff << 6)366#define T_RTP_SHIFT 3367#define T_RTP_MASK (0x7 << 3)368#define T_CKE_SHIFT 0369#define T_CKE_MASK (0x7 << 0)370 371/* SDRAM_TIMING_3 */372#define T_PDLL_UL_SHIFT 28373#define T_PDLL_UL_MASK (0xf << 28)374#define T_CSTA_SHIFT 24375#define T_CSTA_MASK (0xf << 24)376#define T_CKESR_SHIFT 21377#define T_CKESR_MASK (0x7 << 21)378#define ZQ_ZQCS_SHIFT 15379#define ZQ_ZQCS_MASK (0x3f << 15)380#define T_TDQSCKMAX_SHIFT 13381#define T_TDQSCKMAX_MASK (0x3 << 13)382#define T_RFC_SHIFT 4383#define T_RFC_MASK (0x1ff << 4)384#define T_RAS_MAX_SHIFT 0385#define T_RAS_MAX_MASK (0xf << 0)386 387/* POWER_MANAGEMENT_CONTROL */388#define PD_TIM_SHIFT 12389#define PD_TIM_MASK (0xf << 12)390#define DPD_EN_SHIFT 11391#define DPD_EN_MASK (1 << 11)392#define LP_MODE_SHIFT 8393#define LP_MODE_MASK (0x7 << 8)394#define SR_TIM_SHIFT 4395#define SR_TIM_MASK (0xf << 4)396#define CS_TIM_SHIFT 0397#define CS_TIM_MASK (0xf << 0)398 399/* LPDDR2_MODE_REG_DATA */400#define VALUE_0_SHIFT 0401#define VALUE_0_MASK (0x7f << 0)402 403/* LPDDR2_MODE_REG_CONFIG */404#define CS_SHIFT 31405#define CS_MASK (1 << 31)406#define REFRESH_EN_SHIFT 30407#define REFRESH_EN_MASK (1 << 30)408#define ADDRESS_SHIFT 0409#define ADDRESS_MASK (0xff << 0)410 411/* OCP_CONFIG */412#define SYS_THRESH_MAX_SHIFT 24413#define SYS_THRESH_MAX_MASK (0xf << 24)414#define MPU_THRESH_MAX_SHIFT 20415#define MPU_THRESH_MAX_MASK (0xf << 20)416#define LL_THRESH_MAX_SHIFT 16417#define LL_THRESH_MAX_MASK (0xf << 16)418 419/* PERFORMANCE_COUNTER_1 */420#define COUNTER1_SHIFT 0421#define COUNTER1_MASK (0xffffffff << 0)422 423/* PERFORMANCE_COUNTER_2 */424#define COUNTER2_SHIFT 0425#define COUNTER2_MASK (0xffffffff << 0)426 427/* PERFORMANCE_COUNTER_CONFIG */428#define CNTR2_MCONNID_EN_SHIFT 31429#define CNTR2_MCONNID_EN_MASK (1 << 31)430#define CNTR2_REGION_EN_SHIFT 30431#define CNTR2_REGION_EN_MASK (1 << 30)432#define CNTR2_CFG_SHIFT 16433#define CNTR2_CFG_MASK (0xf << 16)434#define CNTR1_MCONNID_EN_SHIFT 15435#define CNTR1_MCONNID_EN_MASK (1 << 15)436#define CNTR1_REGION_EN_SHIFT 14437#define CNTR1_REGION_EN_MASK (1 << 14)438#define CNTR1_CFG_SHIFT 0439#define CNTR1_CFG_MASK (0xf << 0)440 441/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */442#define MCONNID2_SHIFT 24443#define MCONNID2_MASK (0xff << 24)444#define REGION_SEL2_SHIFT 16445#define REGION_SEL2_MASK (0x3 << 16)446#define MCONNID1_SHIFT 8447#define MCONNID1_MASK (0xff << 8)448#define REGION_SEL1_SHIFT 0449#define REGION_SEL1_MASK (0x3 << 0)450 451/* PERFORMANCE_COUNTER_TIME */452#define TOTAL_TIME_SHIFT 0453#define TOTAL_TIME_MASK (0xffffffff << 0)454 455/* DLL_CALIB_CTRL */456#define ACK_WAIT_SHIFT 16457#define ACK_WAIT_MASK (0xf << 16)458#define DLL_CALIB_INTERVAL_SHIFT 0459#define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)460 461/* END_OF_INTERRUPT */462#define EOI_SHIFT 0463#define EOI_MASK (1 << 0)464 465/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */466#define DNV_SYS_SHIFT 2467#define DNV_SYS_MASK (1 << 2)468#define TA_SYS_SHIFT 1469#define TA_SYS_MASK (1 << 1)470#define ERR_SYS_SHIFT 0471#define ERR_SYS_MASK (1 << 0)472 473/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */474#define DNV_LL_SHIFT 2475#define DNV_LL_MASK (1 << 2)476#define TA_LL_SHIFT 1477#define TA_LL_MASK (1 << 1)478#define ERR_LL_SHIFT 0479#define ERR_LL_MASK (1 << 0)480 481/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */482#define EN_DNV_SYS_SHIFT 2483#define EN_DNV_SYS_MASK (1 << 2)484#define EN_TA_SYS_SHIFT 1485#define EN_TA_SYS_MASK (1 << 1)486#define EN_ERR_SYS_SHIFT 0487#define EN_ERR_SYS_MASK (1 << 0)488 489/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */490#define EN_DNV_LL_SHIFT 2491#define EN_DNV_LL_MASK (1 << 2)492#define EN_TA_LL_SHIFT 1493#define EN_TA_LL_MASK (1 << 1)494#define EN_ERR_LL_SHIFT 0495#define EN_ERR_LL_MASK (1 << 0)496 497/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */498#define ZQ_CS1EN_SHIFT 31499#define ZQ_CS1EN_MASK (1 << 31)500#define ZQ_CS0EN_SHIFT 30501#define ZQ_CS0EN_MASK (1 << 30)502#define ZQ_DUALCALEN_SHIFT 29503#define ZQ_DUALCALEN_MASK (1 << 29)504#define ZQ_SFEXITEN_SHIFT 28505#define ZQ_SFEXITEN_MASK (1 << 28)506#define ZQ_ZQINIT_MULT_SHIFT 18507#define ZQ_ZQINIT_MULT_MASK (0x3 << 18)508#define ZQ_ZQCL_MULT_SHIFT 16509#define ZQ_ZQCL_MULT_MASK (0x3 << 16)510#define ZQ_REFINTERVAL_SHIFT 0511#define ZQ_REFINTERVAL_MASK (0xffff << 0)512 513/* TEMPERATURE_ALERT_CONFIG */514#define TA_CS1EN_SHIFT 31515#define TA_CS1EN_MASK (1 << 31)516#define TA_CS0EN_SHIFT 30517#define TA_CS0EN_MASK (1 << 30)518#define TA_SFEXITEN_SHIFT 28519#define TA_SFEXITEN_MASK (1 << 28)520#define TA_DEVWDT_SHIFT 26521#define TA_DEVWDT_MASK (0x3 << 26)522#define TA_DEVCNT_SHIFT 24523#define TA_DEVCNT_MASK (0x3 << 24)524#define TA_REFINTERVAL_SHIFT 0525#define TA_REFINTERVAL_MASK (0x3fffff << 0)526 527/* OCP_ERROR_LOG */528#define MADDRSPACE_SHIFT 14529#define MADDRSPACE_MASK (0x3 << 14)530#define MBURSTSEQ_SHIFT 11531#define MBURSTSEQ_MASK (0x7 << 11)532#define MCMD_SHIFT 8533#define MCMD_MASK (0x7 << 8)534#define MCONNID_SHIFT 0535#define MCONNID_MASK (0xff << 0)536 537/* READ_WRITE_LEVELING_CONTROL */538#define RDWRLVLFULL_START 0x80000000539 540/* DDR_PHY_CTRL_1 - EMIF4D */541#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4542#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)543#define READ_LATENCY_SHIFT_4D 0544#define READ_LATENCY_MASK_4D (0xf << 0)545 546/* DDR_PHY_CTRL_1 - EMIF4D5 */547#define DLL_HALF_DELAY_SHIFT_4D5 21548#define DLL_HALF_DELAY_MASK_4D5 (1 << 21)549#define READ_LATENCY_SHIFT_4D5 0550#define READ_LATENCY_MASK_4D5 (0x1f << 0)551 552/* DDR_PHY_CTRL_1_SHDW */553#define DDR_PHY_CTRL_1_SHDW_SHIFT 5554#define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)555#define READ_LATENCY_SHDW_SHIFT 0556#define READ_LATENCY_SHDW_MASK (0x1f << 0)557 558#define EMIF_SRAM_AM33_REG_LAYOUT 0x00000000559#define EMIF_SRAM_AM43_REG_LAYOUT 0x00000001560 561#ifndef __ASSEMBLY__562/*563 * Structure containing shadow of important registers in EMIF564 * The calculation function fills in this structure to be later used for565 * initialisation and DVFS566 */567struct emif_regs {568 u32 freq;569 u32 ref_ctrl_shdw;570 u32 ref_ctrl_shdw_derated;571 u32 sdram_tim1_shdw;572 u32 sdram_tim1_shdw_derated;573 u32 sdram_tim2_shdw;574 u32 sdram_tim3_shdw;575 u32 sdram_tim3_shdw_derated;576 u32 pwr_mgmt_ctrl_shdw;577 union {578 u32 read_idle_ctrl_shdw_normal;579 u32 dll_calib_ctrl_shdw_normal;580 };581 union {582 u32 read_idle_ctrl_shdw_volt_ramp;583 u32 dll_calib_ctrl_shdw_volt_ramp;584 };585 586 u32 phy_ctrl_1_shdw;587 u32 ext_phy_ctrl_2_shdw;588 u32 ext_phy_ctrl_3_shdw;589 u32 ext_phy_ctrl_4_shdw;590};591 592struct ti_emif_pm_functions;593 594extern unsigned int ti_emif_sram;595extern unsigned int ti_emif_sram_sz;596extern struct ti_emif_pm_data ti_emif_pm_sram_data;597extern struct emif_regs_amx3 ti_emif_regs_amx3;598 599void ti_emif_save_context(void);600void ti_emif_restore_context(void);601void ti_emif_run_hw_leveling(void);602void ti_emif_enter_sr(void);603void ti_emif_exit_sr(void);604void ti_emif_abort_sr(void);605 606#endif /* __ASSEMBLY__ */607#endif /* __EMIF_H */608