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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Definitions for DDR memories based on JEDEC specs4 *5 * Copyright (C) 2012 Texas Instruments, Inc.6 *7 * Aneesh V <aneesh@ti.com>8 */9#ifndef __JEDEC_DDR_H10#define __JEDEC_DDR_H11 12#include <linux/types.h>13 14/* DDR Densities */15#define DDR_DENSITY_64Mb 116#define DDR_DENSITY_128Mb 217#define DDR_DENSITY_256Mb 318#define DDR_DENSITY_512Mb 419#define DDR_DENSITY_1Gb 520#define DDR_DENSITY_2Gb 621#define DDR_DENSITY_4Gb 722#define DDR_DENSITY_8Gb 823#define DDR_DENSITY_16Gb 924#define DDR_DENSITY_32Gb 1025 26/* DDR type */27#define DDR_TYPE_DDR2 128#define DDR_TYPE_DDR3 229#define DDR_TYPE_LPDDR2_S4 330#define DDR_TYPE_LPDDR2_S2 431#define DDR_TYPE_LPDDR2_NVM 532#define DDR_TYPE_LPDDR3 633 34/* DDR IO width */35#define DDR_IO_WIDTH_4 136#define DDR_IO_WIDTH_8 237#define DDR_IO_WIDTH_16 338#define DDR_IO_WIDTH_32 439 40/* Number of Row bits */41#define R9 942#define R10 1043#define R11 1144#define R12 1245#define R13 1346#define R14 1447#define R15 1548#define R16 1649 50/* Number of Column bits */51#define C7 752#define C8 853#define C9 954#define C10 1055#define C11 1156#define C12 1257 58/* Number of Banks */59#define B1 060#define B2 161#define B4 262#define B8 363 64/* Refresh rate in nano-seconds */65#define T_REFI_15_6 1560066#define T_REFI_7_8 780067#define T_REFI_3_9 390068 69/* tRFC values */70#define T_RFC_90 9000071#define T_RFC_110 11000072#define T_RFC_130 13000073#define T_RFC_160 16000074#define T_RFC_210 21000075#define T_RFC_300 30000076#define T_RFC_350 35000077 78/* Mode register numbers */79#define DDR_MR0 080#define DDR_MR1 181#define DDR_MR2 282#define DDR_MR3 383#define DDR_MR4 484#define DDR_MR5 585#define DDR_MR6 686#define DDR_MR7 787#define DDR_MR8 888#define DDR_MR9 989#define DDR_MR10 1090#define DDR_MR11 1191#define DDR_MR16 1692#define DDR_MR17 1793#define DDR_MR18 1894 95/*96 * LPDDR2 related defines97 */98 99/* MR4 register fields */100#define MR4_SDRAM_REF_RATE_SHIFT 0101#define MR4_SDRAM_REF_RATE_MASK 7102#define MR4_TUF_SHIFT 7103#define MR4_TUF_MASK (1 << 7)104 105/* MR4 SDRAM Refresh Rate field values */106#define SDRAM_TEMP_NOMINAL 0x3107#define SDRAM_TEMP_RESERVED_4 0x4108#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5109#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6110#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7111 112#define NUM_DDR_ADDR_TABLE_ENTRIES 11113#define NUM_DDR_TIMING_TABLE_ENTRIES 4114 115#define LPDDR2_MANID_SAMSUNG 1116#define LPDDR2_MANID_QIMONDA 2117#define LPDDR2_MANID_ELPIDA 3118#define LPDDR2_MANID_ETRON 4119#define LPDDR2_MANID_NANYA 5120#define LPDDR2_MANID_HYNIX 6121#define LPDDR2_MANID_MOSEL 7122#define LPDDR2_MANID_WINBOND 8123#define LPDDR2_MANID_ESMT 9124#define LPDDR2_MANID_SPANSION 11125#define LPDDR2_MANID_SST 12126#define LPDDR2_MANID_ZMOS 13127#define LPDDR2_MANID_INTEL 14128#define LPDDR2_MANID_NUMONYX 254129#define LPDDR2_MANID_MICRON 255130 131#define LPDDR2_TYPE_S4 0132#define LPDDR2_TYPE_S2 1133#define LPDDR2_TYPE_NVM 2134 135/* Structure for DDR addressing info from the JEDEC spec */136struct lpddr2_addressing {137 u32 num_banks;138 u32 tREFI_ns;139 u32 tRFCab_ps;140};141 142/*143 * Structure for timings from the LPDDR2 datasheet144 * All parameters are in pico seconds(ps) unless explicitly indicated145 * with a suffix like tRAS_max_ns below146 */147struct lpddr2_timings {148 u32 max_freq;149 u32 min_freq;150 u32 tRPab;151 u32 tRCD;152 u32 tWR;153 u32 tRAS_min;154 u32 tRRD;155 u32 tWTR;156 u32 tXP;157 u32 tRTP;158 u32 tCKESR;159 u32 tDQSCK_max;160 u32 tDQSCK_max_derated;161 u32 tFAW;162 u32 tZQCS;163 u32 tZQCL;164 u32 tZQinit;165 u32 tRAS_max_ns;166};167 168/*169 * Min value for some parameters in terms of number of tCK cycles(nCK)170 * Please set to zero parameters that are not valid for a given memory171 * type172 */173struct lpddr2_min_tck {174 u32 tRPab;175 u32 tRCD;176 u32 tWR;177 u32 tRASmin;178 u32 tRRD;179 u32 tWTR;180 u32 tXP;181 u32 tRTP;182 u32 tCKE;183 u32 tCKESR;184 u32 tFAW;185};186 187extern const struct lpddr2_addressing188 lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];189extern const struct lpddr2_timings190 lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];191extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;192 193/* Structure of MR8 */194union lpddr2_basic_config4 {195 u32 value;196 197 struct {198 unsigned int arch_type : 2;199 unsigned int density : 4;200 unsigned int io_width : 2;201 } __packed;202};203 204/*205 * Structure for information about LPDDR2 chip. All parameters are206 * matching raw values of standard mode register bitfields or set to207 * -ENOENT if info unavailable.208 */209struct lpddr2_info {210 int arch_type;211 int density;212 int io_width;213 int manufacturer_id;214 int revision_id1;215 int revision_id2;216};217 218const char *lpddr2_jedec_manufacturer(unsigned int manufacturer_id);219 220/*221 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.222 * All parameters are in pico seconds(ps) excluding max_freq, min_freq which223 * are in Hz.224 */225struct lpddr3_timings {226 u32 max_freq;227 u32 min_freq;228 u32 tRFC;229 u32 tRRD;230 u32 tRPab;231 u32 tRPpb;232 u32 tRCD;233 u32 tRC;234 u32 tRAS;235 u32 tWTR;236 u32 tWR;237 u32 tRTP;238 u32 tW2W_C2C;239 u32 tR2R_C2C;240 u32 tWL;241 u32 tDQSCK;242 u32 tRL;243 u32 tFAW;244 u32 tXSR;245 u32 tXP;246 u32 tCKE;247 u32 tCKESR;248 u32 tMRD;249};250 251/*252 * Min value for some parameters in terms of number of tCK cycles(nCK)253 * Please set to zero parameters that are not valid for a given memory254 * type255 */256struct lpddr3_min_tck {257 u32 tRFC;258 u32 tRRD;259 u32 tRPab;260 u32 tRPpb;261 u32 tRCD;262 u32 tRC;263 u32 tRAS;264 u32 tWTR;265 u32 tWR;266 u32 tRTP;267 u32 tW2W_C2C;268 u32 tR2R_C2C;269 u32 tWL;270 u32 tDQSCK;271 u32 tRL;272 u32 tFAW;273 u32 tXSR;274 u32 tXP;275 u32 tCKE;276 u32 tCKESR;277 u32 tMRD;278};279 280#endif /* __JEDEC_DDR_H */281