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1// SPDX-License-Identifier: GPL-2.02/*3 * Memory controller driver for ARM PrimeCell PL1724 * PrimeCell MultiPort Memory Controller (PL172)5 *6 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>7 *8 * Based on:9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.10 */11 12#include <linux/amba/bus.h>13#include <linux/clk.h>14#include <linux/device.h>15#include <linux/err.h>16#include <linux/init.h>17#include <linux/io.h>18#include <linux/kernel.h>19#include <linux/module.h>20#include <linux/of.h>21#include <linux/of_platform.h>22#include <linux/time.h>23 24#define MPMC_STATIC_CFG(n) (0x200 + 0x20 * (n))25#define MPMC_STATIC_CFG_MW_8BIT 0x026#define MPMC_STATIC_CFG_MW_16BIT 0x127#define MPMC_STATIC_CFG_MW_32BIT 0x228#define MPMC_STATIC_CFG_PM BIT(3)29#define MPMC_STATIC_CFG_PC BIT(6)30#define MPMC_STATIC_CFG_PB BIT(7)31#define MPMC_STATIC_CFG_EW BIT(8)32#define MPMC_STATIC_CFG_B BIT(19)33#define MPMC_STATIC_CFG_P BIT(20)34#define MPMC_STATIC_WAIT_WEN(n) (0x204 + 0x20 * (n))35#define MPMC_STATIC_WAIT_WEN_MAX 0x0f36#define MPMC_STATIC_WAIT_OEN(n) (0x208 + 0x20 * (n))37#define MPMC_STATIC_WAIT_OEN_MAX 0x0f38#define MPMC_STATIC_WAIT_RD(n) (0x20c + 0x20 * (n))39#define MPMC_STATIC_WAIT_RD_MAX 0x1f40#define MPMC_STATIC_WAIT_PAGE(n) (0x210 + 0x20 * (n))41#define MPMC_STATIC_WAIT_PAGE_MAX 0x1f42#define MPMC_STATIC_WAIT_WR(n) (0x214 + 0x20 * (n))43#define MPMC_STATIC_WAIT_WR_MAX 0x1f44#define MPMC_STATIC_WAIT_TURN(n) (0x218 + 0x20 * (n))45#define MPMC_STATIC_WAIT_TURN_MAX 0x0f46 47/* Maximum number of static chip selects */48#define PL172_MAX_CS 449 50struct pl172_data {51 void __iomem *base;52 unsigned long rate;53 struct clk *clk;54};55 56static int pl172_timing_prop(struct amba_device *adev,57 const struct device_node *np, const char *name,58 u32 reg_offset, u32 max, int start)59{60 struct pl172_data *pl172 = amba_get_drvdata(adev);61 int cycles;62 u32 val;63 64 if (!of_property_read_u32(np, name, &val)) {65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;66 if (cycles < 0) {67 cycles = 0;68 } else if (cycles > max) {69 dev_err(&adev->dev, "%s timing too tight\n", name);70 return -EINVAL;71 }72 73 writel(cycles, pl172->base + reg_offset);74 }75 76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +77 readl(pl172->base + reg_offset));78 79 return 0;80}81 82static int pl172_setup_static(struct amba_device *adev,83 struct device_node *np, u32 cs)84{85 struct pl172_data *pl172 = amba_get_drvdata(adev);86 u32 cfg;87 int ret;88 89 /* MPMC static memory configuration */90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {91 if (cfg == 8) {92 cfg = MPMC_STATIC_CFG_MW_8BIT;93 } else if (cfg == 16) {94 cfg = MPMC_STATIC_CFG_MW_16BIT;95 } else if (cfg == 32) {96 cfg = MPMC_STATIC_CFG_MW_32BIT;97 } else {98 dev_err(&adev->dev, "invalid memory width cs%u\n", cs);99 return -EINVAL;100 }101 } else {102 dev_err(&adev->dev, "memory-width property required\n");103 return -EINVAL;104 }105 106 if (of_property_read_bool(np, "mpmc,async-page-mode"))107 cfg |= MPMC_STATIC_CFG_PM;108 109 if (of_property_read_bool(np, "mpmc,cs-active-high"))110 cfg |= MPMC_STATIC_CFG_PC;111 112 if (of_property_read_bool(np, "mpmc,byte-lane-low"))113 cfg |= MPMC_STATIC_CFG_PB;114 115 if (of_property_read_bool(np, "mpmc,extended-wait"))116 cfg |= MPMC_STATIC_CFG_EW;117 118 if (amba_part(adev) == 0x172 &&119 of_property_read_bool(np, "mpmc,buffer-enable"))120 cfg |= MPMC_STATIC_CFG_B;121 122 if (of_property_read_bool(np, "mpmc,write-protect"))123 cfg |= MPMC_STATIC_CFG_P;124 125 writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));126 dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);127 128 /* MPMC static memory timing */129 ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",130 MPMC_STATIC_WAIT_WEN(cs),131 MPMC_STATIC_WAIT_WEN_MAX, 1);132 if (ret)133 goto fail;134 135 ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",136 MPMC_STATIC_WAIT_OEN(cs),137 MPMC_STATIC_WAIT_OEN_MAX, 0);138 if (ret)139 goto fail;140 141 ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",142 MPMC_STATIC_WAIT_RD(cs),143 MPMC_STATIC_WAIT_RD_MAX, 1);144 if (ret)145 goto fail;146 147 ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",148 MPMC_STATIC_WAIT_PAGE(cs),149 MPMC_STATIC_WAIT_PAGE_MAX, 1);150 if (ret)151 goto fail;152 153 ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",154 MPMC_STATIC_WAIT_WR(cs),155 MPMC_STATIC_WAIT_WR_MAX, 2);156 if (ret)157 goto fail;158 159 ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",160 MPMC_STATIC_WAIT_TURN(cs),161 MPMC_STATIC_WAIT_TURN_MAX, 1);162 if (ret)163 goto fail;164 165 return 0;166fail:167 dev_err(&adev->dev, "failed to configure cs%u\n", cs);168 return ret;169}170 171static int pl172_parse_cs_config(struct amba_device *adev,172 struct device_node *np)173{174 u32 cs;175 176 if (!of_property_read_u32(np, "mpmc,cs", &cs)) {177 if (cs >= PL172_MAX_CS) {178 dev_err(&adev->dev, "cs%u invalid\n", cs);179 return -EINVAL;180 }181 182 return pl172_setup_static(adev, np, cs);183 }184 185 dev_err(&adev->dev, "cs property required\n");186 187 return -EINVAL;188}189 190static void pl172_amba_release_regions(void *data)191{192 struct amba_device *adev = data;193 194 amba_release_regions(adev);195}196 197static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};198static const char * const pl175_revisions[] = {"r1"};199static const char * const pl176_revisions[] = {"r0"};200 201static int pl172_probe(struct amba_device *adev, const struct amba_id *id)202{203 struct device_node *child_np, *np = adev->dev.of_node;204 struct device *dev = &adev->dev;205 static const char *rev = "?";206 struct pl172_data *pl172;207 int ret;208 209 if (amba_part(adev) == 0x172) {210 if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))211 rev = pl172_revisions[amba_rev(adev)];212 } else if (amba_part(adev) == 0x175) {213 if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))214 rev = pl175_revisions[amba_rev(adev)];215 } else if (amba_part(adev) == 0x176) {216 if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))217 rev = pl176_revisions[amba_rev(adev)];218 }219 220 dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);221 222 pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);223 if (!pl172)224 return -ENOMEM;225 226 pl172->clk = devm_clk_get_enabled(dev, "mpmcclk");227 if (IS_ERR(pl172->clk))228 return dev_err_probe(dev, PTR_ERR(pl172->clk),229 "no mpmcclk provided clock\n");230 231 pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;232 if (!pl172->rate)233 return dev_err_probe(dev, -EINVAL,234 "unable to get mpmcclk clock rate\n");235 236 ret = amba_request_regions(adev, NULL);237 if (ret) {238 dev_err(dev, "unable to request AMBA regions\n");239 return ret;240 }241 242 ret = devm_add_action_or_reset(dev, pl172_amba_release_regions, adev);243 if (ret)244 return ret;245 246 pl172->base = devm_ioremap(dev, adev->res.start,247 resource_size(&adev->res));248 if (!pl172->base)249 return dev_err_probe(dev, -ENOMEM, "ioremap failed\n");250 251 amba_set_drvdata(adev, pl172);252 253 /*254 * Loop through each child node, which represent a chip select, and255 * configure parameters and timing. If successful; populate devices256 * under that node.257 */258 for_each_available_child_of_node(np, child_np) {259 ret = pl172_parse_cs_config(adev, child_np);260 if (ret)261 continue;262 263 of_platform_populate(child_np, NULL, NULL, dev);264 }265 266 return 0;267}268 269static const struct amba_id pl172_ids[] = {270 /* PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */271 {272 .id = 0x07041172,273 .mask = 0x3f0fffff,274 },275 /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */276 {277 .id = 0x07041175,278 .mask = 0x3f0fffff,279 },280 /* PrimeCell MPMC PL176 */281 {282 .id = 0x89041176,283 .mask = 0xff0fffff,284 },285 { 0, 0 },286};287MODULE_DEVICE_TABLE(amba, pl172_ids);288 289static struct amba_driver pl172_driver = {290 .drv = {291 .name = "memory-pl172",292 },293 .probe = pl172_probe,294 .id_table = pl172_ids,295};296module_amba_driver(pl172_driver);297 298MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");299MODULE_DESCRIPTION("PL172 Memory Controller Driver");300MODULE_LICENSE("GPL v2");301