1017 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.4 */5 6#ifndef TEGRA210_EMC_H7#define TEGRA210_EMC_H8 9#include <linux/clk.h>10#include <linux/clk/tegra.h>11#include <linux/io.h>12#include <linux/platform_device.h>13 14#define DVFS_FGCG_HIGH_SPEED_THRESHOLD 100015#define IOBRICK_DCC_THRESHOLD 240016#define DVFS_FGCG_MID_SPEED_THRESHOLD 60017 18#define EMC_STATUS_UPDATE_TIMEOUT 100019 20/* register definitions */21#define EMC_INTSTATUS 0x022#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)23#define EMC_DBG 0x824#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)25#define EMC_DBG_WRITE_ACTIVE_ONLY BIT(30)26#define EMC_CFG 0xc27#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)28#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)29#define EMC_CFG_DRAM_ACPD BIT(29)30#define EMC_CFG_DYN_SELF_REF BIT(28)31#define EMC_PIN 0x2432#define EMC_PIN_PIN_CKE BIT(0)33#define EMC_PIN_PIN_CKEB BIT(1)34#define EMC_PIN_PIN_CKE_PER_DEV BIT(2)35#define EMC_TIMING_CONTROL 0x2836#define EMC_RC 0x2c37#define EMC_RFC 0x3038#define EMC_RAS 0x3439#define EMC_RP 0x3840#define EMC_R2W 0x3c41#define EMC_W2R 0x4042#define EMC_R2P 0x4443#define EMC_W2P 0x4844#define EMC_RD_RCD 0x4c45#define EMC_WR_RCD 0x5046#define EMC_RRD 0x5447#define EMC_REXT 0x5848#define EMC_WDV 0x5c49#define EMC_QUSE 0x6050#define EMC_QRST 0x6451#define EMC_QSAFE 0x6852#define EMC_RDV 0x6c53#define EMC_REFRESH 0x7054#define EMC_BURST_REFRESH_NUM 0x7455#define EMC_PDEX2WR 0x7856#define EMC_PDEX2RD 0x7c57#define EMC_PCHG2PDEN 0x8058#define EMC_ACT2PDEN 0x8459#define EMC_AR2PDEN 0x8860#define EMC_RW2PDEN 0x8c61#define EMC_TXSR 0x9062#define EMC_TCKE 0x9463#define EMC_TFAW 0x9864#define EMC_TRPAB 0x9c65#define EMC_TCLKSTABLE 0xa066#define EMC_TCLKSTOP 0xa467#define EMC_TREFBW 0xa868#define EMC_TPPD 0xac69#define EMC_ODT_WRITE 0xb070#define EMC_PDEX2MRR 0xb471#define EMC_WEXT 0xb872#define EMC_RFC_SLR 0xc073#define EMC_MRS_WAIT_CNT2 0xc474#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT 1675#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 076#define EMC_MRS_WAIT_CNT 0xc877#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 078#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \79 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)80 81#define EMC_MRS 0xcc82#define EMC_EMRS 0xd083#define EMC_EMRS_USE_EMRS_LONG_CNT BIT(26)84#define EMC_REF 0xd485#define EMC_REF_REF_CMD BIT(0)86#define EMC_SELF_REF 0xe087#define EMC_MRW 0xe888#define EMC_MRW_MRW_OP_SHIFT 089#define EMC_MRW_MRW_OP_MASK \90 (0xff << EMC_MRW_MRW_OP_SHIFT)91#define EMC_MRW_MRW_MA_SHIFT 1692#define EMC_MRW_USE_MRW_EXT_CNT 2793#define EMC_MRW_MRW_DEV_SELECTN_SHIFT 3094 95#define EMC_MRR 0xec96#define EMC_MRR_DEV_SEL_SHIFT 3097#define EMC_MRR_DEV_SEL_MASK 0x398#define EMC_MRR_MA_SHIFT 1699#define EMC_MRR_MA_MASK 0xff100#define EMC_MRR_DATA_SHIFT 0101#define EMC_MRR_DATA_MASK 0xffff102 103#define EMC_FBIO_SPARE 0x100104#define EMC_FBIO_CFG5 0x104105#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0106#define EMC_FBIO_CFG5_DRAM_TYPE_MASK \107 (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT)108#define EMC_FBIO_CFG5_CMD_TX_DIS BIT(8)109 110#define EMC_PDEX2CKE 0x118111#define EMC_CKE2PDEN 0x11c112#define EMC_MPC 0x128113#define EMC_EMRS2 0x12c114#define EMC_EMRS2_USE_EMRS2_LONG_CNT BIT(26)115#define EMC_MRW2 0x134116#define EMC_MRW3 0x138117#define EMC_MRW4 0x13c118#define EMC_R2R 0x144119#define EMC_EINPUT 0x14c120#define EMC_EINPUT_DURATION 0x150121#define EMC_PUTERM_EXTRA 0x154122#define EMC_TCKESR 0x158123#define EMC_TPD 0x15c124#define EMC_AUTO_CAL_CONFIG 0x2a4125#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START BIT(0)126#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL BIT(9)127#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL BIT(10)128#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE BIT(29)129#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)130#define EMC_EMC_STATUS 0x2b4131#define EMC_EMC_STATUS_MRR_DIVLD BIT(20)132#define EMC_EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)133#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT 4134#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK \135 (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT)136#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT 8137#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK \138 (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT)139 140#define EMC_CFG_2 0x2b8141#define EMC_CFG_DIG_DLL 0x2bc142#define EMC_CFG_DIG_DLL_CFG_DLL_EN BIT(0)143#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK BIT(1)144#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC BIT(3)145#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK BIT(4)146#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6147#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \148 (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT)149#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8150#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \151 (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT)152 153#define EMC_CFG_DIG_DLL_PERIOD 0x2c0154#define EMC_DIG_DLL_STATUS 0x2c4155#define EMC_DIG_DLL_STATUS_DLL_LOCK BIT(15)156#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED BIT(17)157#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0158#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \159 (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT)160 161#define EMC_CFG_DIG_DLL_1 0x2c8162#define EMC_RDV_MASK 0x2cc163#define EMC_WDV_MASK 0x2d0164#define EMC_RDV_EARLY_MASK 0x2d4165#define EMC_RDV_EARLY 0x2d8166#define EMC_AUTO_CAL_CONFIG8 0x2dc167#define EMC_ZCAL_INTERVAL 0x2e0168#define EMC_ZCAL_WAIT_CNT 0x2e4169#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff170#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0171 172#define EMC_ZQ_CAL 0x2ec173#define EMC_ZQ_CAL_DEV_SEL_SHIFT 30174#define EMC_ZQ_CAL_LONG BIT(4)175#define EMC_ZQ_CAL_ZQ_LATCH_CMD BIT(1)176#define EMC_ZQ_CAL_ZQ_CAL_CMD BIT(0)177#define EMC_FDPD_CTRL_DQ 0x310178#define EMC_FDPD_CTRL_CMD 0x314179#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318180#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c181#define EMC_PMACRO_BRICK_CTRL_RFU1 0x330182#define EMC_PMACRO_BRICK_CTRL_RFU2 0x334183#define EMC_TR_TIMING_0 0x3b4184#define EMC_TR_CTRL_1 0x3bc185#define EMC_TR_RDV 0x3c4186#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc187#define EMC_SEL_DPD_CTRL 0x3d8188#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN BIT(8)189#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN BIT(5)190#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN BIT(4)191#define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN BIT(3)192#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN BIT(2)193#define EMC_PRE_REFRESH_REQ_CNT 0x3dc194#define EMC_DYN_SELF_REF_CONTROL 0x3e0195#define EMC_TXSRDLL 0x3e4196#define EMC_CCFIFO_ADDR 0x3e8197#define EMC_CCFIFO_ADDR_STALL_BY_1 (1 << 31)198#define EMC_CCFIFO_ADDR_STALL(x) (((x) & 0x7fff) << 16)199#define EMC_CCFIFO_ADDR_OFFSET(x) ((x) & 0xffff)200#define EMC_CCFIFO_DATA 0x3ec201#define EMC_TR_QPOP 0x3f4202#define EMC_TR_RDV_MASK 0x3f8203#define EMC_TR_QSAFE 0x3fc204#define EMC_TR_QRST 0x400205#define EMC_ISSUE_QRST 0x428206#define EMC_AUTO_CAL_CONFIG2 0x458207#define EMC_AUTO_CAL_CONFIG3 0x45c208#define EMC_TR_DVFS 0x460209#define EMC_AUTO_CAL_CHANNEL 0x464210#define EMC_IBDLY 0x468211#define EMC_OBDLY 0x46c212#define EMC_TXDSRVTTGEN 0x480213#define EMC_WE_DURATION 0x48c214#define EMC_WS_DURATION 0x490215#define EMC_WEV 0x494216#define EMC_WSV 0x498217#define EMC_CFG_3 0x49c218#define EMC_MRW6 0x4a4219#define EMC_MRW7 0x4a8220#define EMC_MRW8 0x4ac221#define EMC_MRW9 0x4b0222#define EMC_MRW10 0x4b4223#define EMC_MRW11 0x4b8224#define EMC_MRW12 0x4bc225#define EMC_MRW13 0x4c0226#define EMC_MRW14 0x4c4227#define EMC_MRW15 0x4d0228#define EMC_CFG_SYNC 0x4d4229#define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8230#define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE BIT(0)231#define EMC_WDV_CHK 0x4e0232#define EMC_CFG_PIPE_2 0x554233#define EMC_CFG_PIPE_CLK 0x558234#define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON BIT(0)235#define EMC_CFG_PIPE_1 0x55c236#define EMC_CFG_PIPE 0x560237#define EMC_QPOP 0x564238#define EMC_QUSE_WIDTH 0x568239#define EMC_PUTERM_WIDTH 0x56c240#define EMC_AUTO_CAL_CONFIG7 0x574241#define EMC_REFCTRL2 0x580242#define EMC_FBIO_CFG7 0x584243#define EMC_FBIO_CFG7_CH0_ENABLE BIT(1)244#define EMC_FBIO_CFG7_CH1_ENABLE BIT(2)245#define EMC_DATA_BRLSHFT_0 0x588246#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21247#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \248 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT)249#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18250#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \251 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT)252#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15253#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \254 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT)255#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12256#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \257 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT)258#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9259#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \260 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT)261#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6262#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \263 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT)264#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3265#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \266 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT)267#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0268#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \269 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT)270 271#define EMC_DATA_BRLSHFT_1 0x58c272#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21273#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \274 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT)275#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18276#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \277 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT)278#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15279#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \280 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT)281#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12282#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \283 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT)284#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9285#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \286 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT)287#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6288#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \289 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT)290#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3291#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \292 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT)293#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0294#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \295 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT)296 297#define EMC_RFCPB 0x590298#define EMC_DQS_BRLSHFT_0 0x594299#define EMC_DQS_BRLSHFT_1 0x598300#define EMC_CMD_BRLSHFT_0 0x59c301#define EMC_CMD_BRLSHFT_1 0x5a0302#define EMC_CMD_BRLSHFT_2 0x5a4303#define EMC_CMD_BRLSHFT_3 0x5a8304#define EMC_QUSE_BRLSHFT_0 0x5ac305#define EMC_AUTO_CAL_CONFIG4 0x5b0306#define EMC_AUTO_CAL_CONFIG5 0x5b4307#define EMC_QUSE_BRLSHFT_1 0x5b8308#define EMC_QUSE_BRLSHFT_2 0x5bc309#define EMC_CCDMW 0x5c0310#define EMC_QUSE_BRLSHFT_3 0x5c4311#define EMC_AUTO_CAL_CONFIG6 0x5cc312#define EMC_DLL_CFG_0 0x5e4313#define EMC_DLL_CFG_1 0x5e8314#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10315#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \316 (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT)317 318#define EMC_CONFIG_SAMPLE_DELAY 0x5f0319#define EMC_CFG_UPDATE 0x5f4320#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT 9321#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK \322 (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT)323 324#define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600325#define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604326#define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608327#define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c328#define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610329#define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614330#define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620331#define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624332#define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628333#define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c334#define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630335#define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634336#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640337#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \338 16339#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \340 (0x3ff << \341 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT)342#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \343 0344#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \345 (0x3ff << \346 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT)347 348#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644349#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \350 16351#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \352 (0x3ff << \353 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT)354#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \355 0356#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \357 (0x3ff << \358 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT)359 360#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648361#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \362 16363#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \364 (0x3ff << \365 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT)366#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \367 0368#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \369 (0x3ff << \370 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT)371 372#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c373#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \374 16375#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \376 (0x3ff << \377 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT)378#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \379 0380#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \381 (0x3ff << \382 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT)383 384#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650385#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654386#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660387#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \388 16389#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \390 (0x3ff << \391 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT)392#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \393 0394#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \395 (0x3ff << \396 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT)397 398#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664399#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \400 16401#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \402 (0x3ff << \403 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT)404#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \405 0406#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \407 (0x3ff << \408 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT)409 410#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668411#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \412 16413#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \414 (0x3ff << \415 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT)416#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \417 0418#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \419 (0x3ff << \420 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT)421 422#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c423#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \424 16425#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \426 (0x3ff << \427 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT)428#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \429 0430#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \431 (0x3ff << \432 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT)433 434#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670435#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674436#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680437#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684438#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688439#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c440#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690441#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694442#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0443#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4444#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8445#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac446#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0447#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4448#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0449#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4450#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8451#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc452#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0453#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4454#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8455#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec456#define EMC_PMACRO_TX_PWRD_0 0x720457#define EMC_PMACRO_TX_PWRD_1 0x724458#define EMC_PMACRO_TX_PWRD_2 0x728459#define EMC_PMACRO_TX_PWRD_3 0x72c460#define EMC_PMACRO_TX_PWRD_4 0x730461#define EMC_PMACRO_TX_PWRD_5 0x734462#define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740463#define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744464#define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c465#define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748466#define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750467#define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754468#define EMC_PMACRO_DDLL_BYPASS 0x760469#define EMC_PMACRO_DDLL_PWRD_0 0x770470#define EMC_PMACRO_DDLL_PWRD_1 0x774471#define EMC_PMACRO_DDLL_PWRD_2 0x778472#define EMC_PMACRO_CMD_CTRL_0 0x780473#define EMC_PMACRO_CMD_CTRL_1 0x784474#define EMC_PMACRO_CMD_CTRL_2 0x788475#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800476#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804477#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808478#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c479#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810480#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814481#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818482#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c483#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820484#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824485#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828486#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c487#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830488#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834489#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838490#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c491#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840492#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844493#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848494#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c495#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850496#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854497#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858498#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c499#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860500#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864501#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868502#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c503#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870504#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874505#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878506#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c507#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880508#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884509#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888510#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c511#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890512#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894513#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898514#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c515#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0516#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4517#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8518#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac519#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0520#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4521#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8522#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc523#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900524#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904525#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908526#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c527#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910528#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914529#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918530#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c531#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920532#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924533#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928534#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c535#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930536#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934537#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938538#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c539#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940540#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944541#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948542#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c543#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950544#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954545#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958546#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c547#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960548#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964549#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968550#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c551#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970552#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974553#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978554#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c555#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980556#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984557#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988558#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c559#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990560#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994561#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998562#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c563#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0564#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4565#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8566#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac567#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0568#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4569#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8570#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc571#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00572#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04573#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08574#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10575#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14576#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18577#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20578#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24579#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28580#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30581#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34582#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38583#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40584#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44585#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48586#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50587#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54588#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58589#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60590#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64591#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68592#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70593#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74594#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78595#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00596#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04597#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08598#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10599#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14600#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18601#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20602#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24603#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28604#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30605#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34606#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38607#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40608#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44609#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48610#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50611#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54612#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58613#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60614#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64615#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68616#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70617#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74618#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78619#define EMC_PMACRO_IB_VREF_DQ_0 0xbe0620#define EMC_PMACRO_IB_VREF_DQ_1 0xbe4621#define EMC_PMACRO_IB_VREF_DQS_0 0xbf0622#define EMC_PMACRO_IB_VREF_DQS_1 0xbf4623#define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00624#define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04625#define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08626#define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c627#define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10628#define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14629#define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20630#define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24631#define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28632#define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30633#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 BIT(16)634#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 BIT(17)635#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 BIT(18)636#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 BIT(19)637#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 BIT(20)638#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 BIT(21)639#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 BIT(22)640#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 BIT(23)641#define EMC_PMACRO_VTTGEN_CTRL_0 0xc34642#define EMC_PMACRO_VTTGEN_CTRL_1 0xc38643#define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c644#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD BIT(0)645#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD BIT(2)646#define EMC_PMACRO_PAD_CFG_CTRL 0xc40647#define EMC_PMACRO_ZCTRL 0xc44648#define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50649#define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54650#define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58651#define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c652#define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60653#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC BIT(1)654#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC BIT(9)655#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC BIT(16)656#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC BIT(24)657#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON BIT(26)658 659#define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64660#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF BIT(0)661#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC BIT(1)662#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF BIT(8)663#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC BIT(9)664#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC BIT(16)665#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC BIT(24)666 667#define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68668#define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78669#define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS BIT(16)670#define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0671#define EMC_PMACRO_IB_RXRT 0xcf4672#define EMC_PMACRO_TRAINING_CTRL_0 0xcf8673#define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR BIT(3)674#define EMC_PMACRO_TRAINING_CTRL_1 0xcfc675#define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR BIT(3)676#define EMC_TRAINING_CTRL 0xe04677#define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c678#define EMC_TRAINING_QUSE_FINE_CTRL 0xe10679#define EMC_TRAINING_QUSE_CTRL_MISC 0xe14680#define EMC_TRAINING_WRITE_FINE_CTRL 0xe18681#define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c682#define EMC_TRAINING_WRITE_VREF_CTRL 0xe20683#define EMC_TRAINING_READ_FINE_CTRL 0xe24684#define EMC_TRAINING_READ_CTRL_MISC 0xe28685#define EMC_TRAINING_READ_VREF_CTRL 0xe2c686#define EMC_TRAINING_CA_FINE_CTRL 0xe30687#define EMC_TRAINING_CA_CTRL_MISC 0xe34688#define EMC_TRAINING_CA_CTRL_MISC1 0xe38689#define EMC_TRAINING_CA_VREF_CTRL 0xe3c690#define EMC_TRAINING_SETTLE 0xe44691#define EMC_TRAINING_MPC 0xe5c692#define EMC_TRAINING_VREF_SETTLE 0xe6c693#define EMC_TRAINING_QUSE_VREF_CTRL 0xed0694#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4695#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8696 697#define EMC_COPY_TABLE_PARAM_PERIODIC_FIELDS BIT(0)698#define EMC_COPY_TABLE_PARAM_TRIM_REGS BIT(1)699 700enum burst_regs_list {701 EMC_RP_INDEX = 6,702 EMC_R2P_INDEX = 9,703 EMC_W2P_INDEX,704 EMC_MRW6_INDEX = 31,705 EMC_REFRESH_INDEX = 41,706 EMC_PRE_REFRESH_REQ_CNT_INDEX = 43,707 EMC_TRPAB_INDEX = 59,708 EMC_MRW7_INDEX = 62,709 EMC_FBIO_CFG5_INDEX = 65,710 EMC_FBIO_CFG7_INDEX,711 EMC_CFG_DIG_DLL_INDEX,712 EMC_ZCAL_INTERVAL_INDEX = 139,713 EMC_ZCAL_WAIT_CNT_INDEX,714 EMC_MRS_WAIT_CNT_INDEX = 141,715 EMC_DLL_CFG_0_INDEX = 144,716 EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX = 146,717 EMC_CFG_INDEX = 148,718 EMC_DYN_SELF_REF_CONTROL_INDEX = 150,719 EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX = 161,720 EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX,721 EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX,722 EMC_PMACRO_BRICK_CTRL_RFU1_INDEX = 167,723 EMC_PMACRO_BG_BIAS_CTRL_0_INDEX = 171,724 EMC_MRW14_INDEX = 199,725 EMC_MRW15_INDEX = 220,726};727 728enum trim_regs_list {729 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_INDEX = 60,730 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_INDEX,731 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_INDEX,732 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_INDEX,733 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_INDEX,734 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_INDEX,735 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_INDEX,736 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_INDEX,737 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_INDEX,738 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_INDEX,739};740 741enum burst_mc_regs_list {742 MC_EMEM_ARB_MISC0_INDEX = 20,743};744 745enum {746 T_RP,747 T_FC_LPDDR4,748 T_RFC,749 T_PDEX,750 RL,751};752 753enum {754 AUTO_PD = 0,755 MAN_SR = 2,756};757 758enum {759 ASSEMBLY = 0,760 ACTIVE,761};762 763enum {764 C0D0U0,765 C0D0U1,766 C0D1U0,767 C0D1U1,768 C1D0U0,769 C1D0U1,770 C1D1U0,771 C1D1U1,772 DRAM_CLKTREE_NUM,773};774 775#define VREF_REGS_PER_CHANNEL_SIZE 4776#define DRAM_TIMINGS_NUM 5777#define BURST_REGS_PER_CHANNEL_SIZE 8778#define TRIM_REGS_PER_CHANNEL_SIZE 10779#define PTFV_ARRAY_SIZE 12780#define SAVE_RESTORE_MOD_REGS_SIZE 12781#define TRAINING_MOD_REGS_SIZE 20782#define BURST_UP_DOWN_REGS_SIZE 24783#define BURST_MC_REGS_SIZE 33784#define TRIM_REGS_SIZE 138785#define BURST_REGS_SIZE 221786 787struct tegra210_emc_per_channel_regs {788 u16 bank;789 u16 offset;790};791 792struct tegra210_emc_table_register_offsets {793 u16 burst[BURST_REGS_SIZE];794 u16 trim[TRIM_REGS_SIZE];795 u16 burst_mc[BURST_MC_REGS_SIZE];796 u16 la_scale[BURST_UP_DOWN_REGS_SIZE];797 struct tegra210_emc_per_channel_regs burst_per_channel[BURST_REGS_PER_CHANNEL_SIZE];798 struct tegra210_emc_per_channel_regs trim_per_channel[TRIM_REGS_PER_CHANNEL_SIZE];799 struct tegra210_emc_per_channel_regs vref_per_channel[VREF_REGS_PER_CHANNEL_SIZE];800};801 802struct tegra210_emc_timing {803 u32 revision;804 const char dvfs_ver[60];805 u32 rate;806 u32 min_volt;807 u32 gpu_min_volt;808 const char clock_src[32];809 u32 clk_src_emc;810 u32 needs_training;811 u32 training_pattern;812 u32 trained;813 814 u32 periodic_training;815 u32 trained_dram_clktree[DRAM_CLKTREE_NUM];816 u32 current_dram_clktree[DRAM_CLKTREE_NUM];817 u32 run_clocks;818 u32 tree_margin;819 820 u32 num_burst;821 u32 num_burst_per_ch;822 u32 num_trim;823 u32 num_trim_per_ch;824 u32 num_mc_regs;825 u32 num_up_down;826 u32 vref_num;827 u32 training_mod_num;828 u32 dram_timing_num;829 830 u32 ptfv_list[PTFV_ARRAY_SIZE];831 832 u32 burst_regs[BURST_REGS_SIZE];833 u32 burst_reg_per_ch[BURST_REGS_PER_CHANNEL_SIZE];834 u32 shadow_regs_ca_train[BURST_REGS_SIZE];835 u32 shadow_regs_quse_train[BURST_REGS_SIZE];836 u32 shadow_regs_rdwr_train[BURST_REGS_SIZE];837 838 u32 trim_regs[TRIM_REGS_SIZE];839 u32 trim_perch_regs[TRIM_REGS_PER_CHANNEL_SIZE];840 841 u32 vref_perch_regs[VREF_REGS_PER_CHANNEL_SIZE];842 843 u32 dram_timings[DRAM_TIMINGS_NUM];844 u32 training_mod_regs[TRAINING_MOD_REGS_SIZE];845 u32 save_restore_mod_regs[SAVE_RESTORE_MOD_REGS_SIZE];846 u32 burst_mc_regs[BURST_MC_REGS_SIZE];847 u32 la_scale_regs[BURST_UP_DOWN_REGS_SIZE];848 849 u32 min_mrs_wait;850 u32 emc_mrw;851 u32 emc_mrw2;852 u32 emc_mrw3;853 u32 emc_mrw4;854 u32 emc_mrw9;855 u32 emc_mrs;856 u32 emc_emrs;857 u32 emc_emrs2;858 u32 emc_auto_cal_config;859 u32 emc_auto_cal_config2;860 u32 emc_auto_cal_config3;861 u32 emc_auto_cal_config4;862 u32 emc_auto_cal_config5;863 u32 emc_auto_cal_config6;864 u32 emc_auto_cal_config7;865 u32 emc_auto_cal_config8;866 u32 emc_cfg_2;867 u32 emc_sel_dpd_ctrl;868 u32 emc_fdpd_ctrl_cmd_no_ramp;869 u32 dll_clk_src;870 u32 clk_out_enb_x_0_clk_enb_emc_dll;871 u32 latency;872};873 874enum tegra210_emc_refresh {875 TEGRA210_EMC_REFRESH_NOMINAL = 0,876 TEGRA210_EMC_REFRESH_2X,877 TEGRA210_EMC_REFRESH_4X,878 TEGRA210_EMC_REFRESH_THROTTLE, /* 4x Refresh + derating. */879};880 881#define DRAM_TYPE_DDR3 0882#define DRAM_TYPE_LPDDR4 1883#define DRAM_TYPE_LPDDR2 2884#define DRAM_TYPE_DDR2 3885 886struct tegra210_emc {887 struct tegra_mc *mc;888 struct device *dev;889 struct clk *clk;890 891 /* nominal EMC frequency table */892 struct tegra210_emc_timing *nominal;893 /* derated EMC frequency table */894 struct tegra210_emc_timing *derated;895 896 /* currently selected table (nominal or derated) */897 struct tegra210_emc_timing *timings;898 unsigned int num_timings;899 900 const struct tegra210_emc_table_register_offsets *offsets;901 902 const struct tegra210_emc_sequence *sequence;903 spinlock_t lock;904 905 void __iomem *regs, *channel[2];906 unsigned int num_channels;907 unsigned int num_devices;908 unsigned int dram_type;909 910 struct tegra210_emc_timing *last;911 struct tegra210_emc_timing *next;912 913 unsigned int training_interval;914 struct timer_list training;915 916 enum tegra210_emc_refresh refresh;917 unsigned int refresh_poll_interval;918 struct timer_list refresh_timer;919 unsigned int temperature;920 atomic_t refresh_poll;921 922 ktime_t clkchange_time;923 int clkchange_delay;924 925 unsigned long resume_rate;926 927 struct {928 struct dentry *root;929 unsigned long min_rate;930 unsigned long max_rate;931 unsigned int temperature;932 } debugfs;933 934 struct tegra210_clk_emc_provider provider;935};936 937struct tegra210_emc_sequence {938 u8 revision;939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);940 u32 (*periodic_compensation)(struct tegra210_emc *emc);941};942 943static inline void emc_writel(struct tegra210_emc *emc, u32 value,944 unsigned int offset)945{946 writel_relaxed(value, emc->regs + offset);947}948 949static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset)950{951 return readl_relaxed(emc->regs + offset);952}953 954static inline void emc_channel_writel(struct tegra210_emc *emc,955 unsigned int channel,956 u32 value, unsigned int offset)957{958 writel_relaxed(value, emc->channel[channel] + offset);959}960 961static inline u32 emc_channel_readl(struct tegra210_emc *emc,962 unsigned int channel, unsigned int offset)963{964 return readl_relaxed(emc->channel[channel] + offset);965}966 967static inline void ccfifo_writel(struct tegra210_emc *emc, u32 value,968 unsigned int offset, u32 delay)969{970 writel_relaxed(value, emc->regs + EMC_CCFIFO_DATA);971 972 value = EMC_CCFIFO_ADDR_STALL_BY_1 | EMC_CCFIFO_ADDR_STALL(delay) |973 EMC_CCFIFO_ADDR_OFFSET(offset);974 writel_relaxed(value, emc->regs + EMC_CCFIFO_ADDR);975}976 977static inline u32 div_o3(u32 a, u32 b)978{979 u32 result = a / b;980 981 if ((b * result) < a)982 return result + 1;983 984 return result;985}986 987/* from tegra210-emc-r21021.c */988extern const struct tegra210_emc_sequence tegra210_emc_r21021;989 990int tegra210_emc_set_refresh(struct tegra210_emc *emc,991 enum tegra210_emc_refresh refresh);992u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip,993 unsigned int address);994void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc);995void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set);996void tegra210_emc_timing_update(struct tegra210_emc *emc);997u32 tegra210_emc_get_dll_state(struct tegra210_emc_timing *next);998struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc,999 unsigned long rate);1000void tegra210_emc_adjust_timing(struct tegra210_emc *emc,1001 struct tegra210_emc_timing *timing);1002int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel,1003 unsigned int offset, u32 bit_mask, bool state);1004unsigned long tegra210_emc_actual_osc_clocks(u32 in);1005u32 tegra210_emc_compensate(struct tegra210_emc_timing *next, u32 offset);1006void tegra210_emc_dll_disable(struct tegra210_emc *emc);1007void tegra210_emc_dll_enable(struct tegra210_emc *emc);1008u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc);1009u32 tegra210_emc_dvfs_power_ramp_down(struct tegra210_emc *emc, u32 clk,1010 bool flip_backward);1011u32 tegra210_emc_dvfs_power_ramp_up(struct tegra210_emc *emc, u32 clk,1012 bool flip_backward);1013void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing);1014void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc);1015 1016#endif1017