51 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.4 */5 6#ifndef TEGRA210_MC_H7#define TEGRA210_MC_H8 9#include "mc.h"10 11/* register definitions */12#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e413#define MC_LATENCY_ALLOWANCE_HC_0 0x31014#define MC_LATENCY_ALLOWANCE_HC_1 0x31415#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x32016#define MC_LATENCY_ALLOWANCE_NVENC_0 0x32817#define MC_LATENCY_ALLOWANCE_PPCS_0 0x34418#define MC_LATENCY_ALLOWANCE_PPCS_1 0x34819#define MC_LATENCY_ALLOWANCE_ISP2_0 0x37020#define MC_LATENCY_ALLOWANCE_ISP2_1 0x37421#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c22#define MC_LATENCY_ALLOWANCE_XUSB_1 0x38023#define MC_LATENCY_ALLOWANCE_TSEC_0 0x39024#define MC_LATENCY_ALLOWANCE_VIC_0 0x39425#define MC_LATENCY_ALLOWANCE_VI2_0 0x39826#define MC_LATENCY_ALLOWANCE_GPU_0 0x3ac27#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b828#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3bc29#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c030#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c431#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3e832#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d833#define MC_MLL_MPCORER_PTSA_RATE 0x44c34#define MC_FTOP_PTSA_RATE 0x50c35#define MC_EMEM_ARB_TIMING_RFCPB 0x6c036#define MC_EMEM_ARB_TIMING_CCDMW 0x6c437#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f038#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f439#define MC_PTSA_GRANT_DECREMENT 0x96040#define MC_EMEM_ARB_DHYST_CTRL 0xbcc41#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd042#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd443#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd844#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc45#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe046#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe447#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe848#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec49 50#endif51