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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2000-2008 LSI Corporation.4 *5 *6 * Name: mpi_cnfg.h7 * Title: MPI Config message, structures, and Pages8 * Creation Date: July 27, 20009 *10 * mpi_cnfg.h Version: 01.05.1811 *12 * Version History13 * ---------------14 *15 * Date Version Description16 * -------- -------- ------------------------------------------------------17 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.18 * 06-06-00 01.00.01 Update version number for 1.0 release.19 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.20 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved221 * fields to FC_DEVICE_0 page, updated the page version.22 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in23 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages24 * and updated the page versions.25 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_126 * page and updated the page version.27 * Added Information field and _INFO_PARAMS_NEGOTIATED28 * definitionto SCSI_DEVICE_0 page.29 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the30 * page version.31 * Added BucketsRemaining to LAN_1 page, redefined the32 * state values, and updated the page version.33 * Revised bus width definitions in SCSI_PORT_0,34 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.35 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page36 * version.37 * Moved FC_DEVICE_0 PageAddress description to spec.38 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field39 * widths in IOC_0 page and updated the page version.40 * 11-02-00 01.01.01 Original release for post 1.0 work41 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI42 * Port Page 2, FC Port Page 4, FC Port Page 543 * 11-15-00 01.01.02 Interim changes to match proposals44 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.45 * 12-05-00 01.01.04 Modified config page actions.46 * 01-09-01 01.01.05 Added defines for page address formats.47 * Data size for Manufacturing pages 2 and 3 no longer48 * defined here.49 * Io Unit Page 2 size is fixed at 4 adapters and some50 * flags were changed.51 * SCSI Port Page 2 Device Settings modified.52 * New fields added to FC Port Page 0 and some flags53 * cleaned up.54 * Removed impedance flash from FC Port Page 1.55 * Added FC Port pages 6 and 7.56 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.57 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.58 * Added some LinkType defines for FcPortPage0.59 * 02-20-01 01.01.08 Started using MPI_POINTER.60 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with61 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.62 * Added definitions and structures for IOC Page 2 and63 * RAID Volume Page 2.64 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.65 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.66 * Added VendorId and ProductRevLevel fields to67 * RAIDVOL2_IM_PHYS_ID struct.68 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_69 * defines to make them compatible to MPI version 1.0.70 * Added structure offset comments.71 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and72 * removed some obsolete ones.73 * Added IO Unit Page 3.74 * Modified defines for Scsi Port Page 2.75 * Modified RAID Volume Pages.76 * 08-08-01 01.02.01 Original release for v1.2 work.77 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.78 * Added defines for the SEP bits in RVP2 VolumeSettings.79 * Modified the DeviceSettings field in RVP2 to use the80 * proper structure.81 * Added defines for SES, SAF-TE, and cross channel for82 * IOCPage2 CapabilitiesFlags.83 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.84 * Removed define for85 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.86 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.87 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.88 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY89 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.90 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,91 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and92 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and93 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.94 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED95 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.96 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.97 * Added rejected bits to SCSI Device Page 0 Information.98 * Increased size of ALPA array in FC Port Page 2 by one99 * and removed a one byte reserved field.100 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in101 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.102 * Added structures for Manufacturing Page 4, IO Unit103 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and104 * RAID PhysDisk Page 0.105 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.106 * Modified some of the new defines to make them 32107 * character unique.108 * Modified how variable length pages (arrays) are defined.109 * Added generic defines for hot spare pools and RAID110 * volume types.111 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.112 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with113 * related define, and bumped the page version define.114 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a115 * reserved byte and added a define.116 * Added define for117 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.118 * Added new config page: CONFIG_PAGE_IOC_5.119 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases120 * fields to CONFIG_PAGE_FC_PORT_0.121 * Added AltConnector and NumRequestedAliases fields to122 * CONFIG_PAGE_FC_PORT_1.123 * Added new config page: CONFIG_PAGE_FC_PORT_10.124 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.125 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.126 * Added more MPI_SCSIDEVPAGE1_RP_ defines.127 * Added define for128 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.129 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.130 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.131 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.132 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.133 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.134 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.135 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for136 * CONFIG_PAGE_FC_PORT_1.137 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable138 * an alias.139 * Added more device id defines.140 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.141 * Added TargetConfig and IDConfig fields to142 * CONFIG_PAGE_SCSI_PORT_1.143 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2144 * to control DV.145 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.146 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field147 * with ADISCHardALPA.148 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.149 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout150 * fields and related defines to CONFIG_PAGE_FC_PORT_1.151 * Added define for152 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.153 * Added new fields to the substructures of154 * CONFIG_PAGE_FC_PORT_10.155 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,156 * CONFIG_PAGE_SCSI_DEVICE_0, and157 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for158 * these pages.159 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.160 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config161 * pages.162 * Added a new structure for extended config page header.163 * Added new extended config pages types and structures for164 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.165 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4166 * to add a Flags field.167 * Two new Manufacturing config pages (5 and 6).168 * Two new bits defined for IO Unit Page 1 Flags field.169 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields170 * to specify the BIOS boot device.171 * Four new Flags bits defined for IO Unit Page 2.172 * Added IO Unit Page 4.173 * Added EEDP Flags settings to IOC Page 1.174 * Added new BIOS Page 1 config page.175 * 10-05-04 01.05.02 Added define for176 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.177 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and178 * associated defines.179 * Added more defines for SAS IO Unit Page 0180 * DiscoveryStatus field.181 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK182 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.183 * Added defines for Physical Mapping Modes to SAS IO Unit184 * Page 2.185 * Added define for186 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.187 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.188 * Added defines for MaxTargetSpinUp to BIOS Page 1.189 * Added 5 new ControlFlags defines for SAS IO Unit190 * Page 1.191 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit192 * Page 2.193 * Added AccessStatus field to SAS Device Page 0 and added194 * new Flags bits for supported SATA features.195 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID196 * Volume Page 1, and RAID Physical Disk Page 1.197 * Replaced IO Unit Page 1 BootTargetID,BootBus, and198 * BootAdapterNum with reserved field.199 * Added DataScrubRate and ResyncRate to RAID Volume200 * Page 0.201 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT202 * define.203 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1204 * Flags field.205 * Added Auto Port Config flag define for SAS IOUNIT206 * Page 1 ControlFlags.207 * Added Disabled bad Phy define to Expander Page 1208 * Discovery Info field.209 * Added SAS/SATA device support to SAS IOUnit Page 1210 * ControlFlags.211 * Added Unsupported device to SAS Dev Page 0 Flags field212 * Added disable use SATA Hash Address for SAS IOUNIT213 * page 1 in ControlFields.214 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to215 * Manufacturing Page 4.216 * Added new defines for BIOS Page 1 IOCSettings field.217 * Added ExtDiskIdentifier field to RAID Physical Disk218 * Page 0.219 * Added new defines for SAS IO Unit Page 1 ControlFlags220 * and to SAS Device Page 0 Flags to control SATA devices.221 * Added defines and structures for the new Log Page 0, a222 * new type of configuration page.223 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.224 * Added WWID field to RAID Volume Page 1.225 * Added PhysicalPort field to SAS Expander pages 0 and 1.226 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.227 * Added Enclosure/Slot boot device format to BIOS Page 2.228 * New status value for RAID Volume Page 0 VolumeStatus229 * (VolumeState subfield).230 * New value for RAID Physical Page 0 InactiveStatus.231 * Added Inactive Volume Member flag RAID Physical Disk232 * Page 0 PhysDiskStatus field.233 * New physical mapping mode in SAS IO Unit Page 2.234 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.235 * Added Slot and Enclosure fields to SAS Device Page 0.236 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.237 * Added more RAID type defines to IOC Page 2.238 * Added Port Enable Delay settings to BIOS Page 1.239 * Added Bad Block Table Full define to RAID Volume Page 0.240 * Added Previous State defines to RAID Physical Disk241 * Page 0.242 * Added Max Sata Targets define for DiscoveryStatus field243 * of SAS IO Unit Page 0.244 * Added Device Self Test to Control Flags of SAS IO Unit245 * Page 1.246 * Added Direct Attach Starting Slot Number define for SAS247 * IO Unit Page 2.248 * Added new fields in SAS Device Page 2 for enclosure249 * mapping.250 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.251 * Added IOC GPIO Flags define to SAS Enclosure Page 0.252 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.253 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from254 * Manufacturing Page 4.255 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit.256 * Added NumDevsPerEnclosure field to SAS IO Unit page 2.257 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP258 * define.259 * Added EnclosureHandle field to SAS Expander page 0.260 * Removed redundant NumTableEntriesProg field from SAS261 * Expander Page 1.262 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for263 * SAS1078.264 * Added more defines for Manufacturing Page 4 Flags field.265 * Added more defines for IOCSettings and added266 * ExpanderSpinup field to Bios Page 1.267 * Added postpone SATA Init bit to SAS IO Unit Page 1268 * ControlFlags.269 * Changed LogEntry format for Log Page 0.270 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4.271 * Added Manufacturing Page 7.272 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING.273 * Added IOC Page 6.274 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2.275 * Added MaxLBAHigh field to RAID Volume Page 0.276 * Added Nvdata version fields to SAS IO Unit Page 0.277 * Added AdditionalControlFlags, MaxTargetPortConnectTime,278 * ReportDeviceMissingDelay, and IODeviceMissingDelay279 * fields to SAS IO Unit Page 1.280 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to281 * Manufacturing Page 5.282 * Added Manufacturing pages 8 through 10.283 * Added defines for supported metadata size bits in284 * CapabilitiesFlags field of IOC Page 6.285 * Added defines for metadata size bits in VolumeSettings286 * field of RAID Volume Page 0.287 * Added SATA Link Reset settings, Enable SATA Asynchronous288 * Notification bit, and HideNonZeroAttachedPhyIdentifiers289 * bit to AdditionalControlFlags field of SAS IO Unit290 * Page 1.291 * Added defines for Enclosure Devices Unmapped and292 * Device Limit Exceeded bits in Status field of SAS IO293 * Unit Page 2.294 * Added more AccessStatus values for SAS Device Page 0.295 * Added bit for SATA Asynchronous Notification Support in296 * Flags field of SAS Device Page 0.297 * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4.298 * Added Disable SMART Polling for CapabilitiesFlags of299 * IOC Page 6.300 * Added Disable SMART Polling to DeviceSettings of BIOS301 * Page 1.302 * Added Multi-Port Domain bit for DiscoveryStatus field303 * of SAS IO Unit Page.304 * Added Multi-Port Domain Illegal flag for SAS IO Unit305 * Page 1 AdditionalControlFlags field.306 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID307 * Metadata bit to Manufacturing Page 4 ExtFlags field.308 * Added Internal Connector to End Device Present bit to309 * Expander Page 0 Flags field.310 * Fixed define for311 * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED.312 * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT313 * define.314 * Added BIOS Page 4 structure.315 * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID316 * Physical Disk Page 1.317 * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of318 * Manufacturing Page 4.319 * Added Solid State Drives Supported bit to IOC Page 6320 * Capabilities Flags.321 * Added new value for AccessStatus field of SAS Device322 * Page 0 (_SATA_NEEDS_INITIALIZATION).323 * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field324 * to control coercion size and the mixing of SAS and SATA325 * SSD drives.326 * --------------------------------------------------------------------------327 */328 329#ifndef MPI_CNFG_H330#define MPI_CNFG_H331 332 333/*****************************************************************************334*335* C o n f i g M e s s a g e a n d S t r u c t u r e s336*337*****************************************************************************/338 339typedef struct _CONFIG_PAGE_HEADER340{341 U8 PageVersion; /* 00h */342 U8 PageLength; /* 01h */343 U8 PageNumber; /* 02h */344 U8 PageType; /* 03h */345} CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,346 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;347 348typedef union _CONFIG_PAGE_HEADER_UNION349{350 ConfigPageHeader_t Struct;351 U8 Bytes[4];352 U16 Word16[2];353 U32 Word32;354} ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,355 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;356 357typedef struct _CONFIG_EXTENDED_PAGE_HEADER358{359 U8 PageVersion; /* 00h */360 U8 Reserved1; /* 01h */361 U8 PageNumber; /* 02h */362 U8 PageType; /* 03h */363 U16 ExtPageLength; /* 04h */364 U8 ExtPageType; /* 06h */365 U8 Reserved2; /* 07h */366} CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,367 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;368 369 370 371/****************************************************************************372* PageType field values373****************************************************************************/374#define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)375#define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)376#define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)377#define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)378#define MPI_CONFIG_PAGEATTR_MASK (0xF0)379 380#define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)381#define MPI_CONFIG_PAGETYPE_IOC (0x01)382#define MPI_CONFIG_PAGETYPE_BIOS (0x02)383#define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)384#define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)385#define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)386#define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)387#define MPI_CONFIG_PAGETYPE_LAN (0x07)388#define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)389#define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)390#define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)391#define MPI_CONFIG_PAGETYPE_INBAND (0x0B)392#define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)393#define MPI_CONFIG_PAGETYPE_MASK (0x0F)394 395#define MPI_CONFIG_TYPENUM_MASK (0x0FFF)396 397 398/****************************************************************************399* ExtPageType field values400****************************************************************************/401#define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)402#define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)403#define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)404#define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)405#define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)406#define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)407 408 409/****************************************************************************410* PageAddress field values411****************************************************************************/412#define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)413 414#define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)415#define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)416#define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)417#define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)418#define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)419#define MPI_SCSI_DEVICE_BUS_SHIFT (8)420#define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)421#define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)422#define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)423#define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)424#define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)425#define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)426#define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)427 428#define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)429#define MPI_FC_PORT_PGAD_PORT_SHIFT (28)430#define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)431#define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)432#define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)433#define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)434 435#define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)436#define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)437#define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)438#define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)439#define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)440#define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)441#define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)442#define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)443#define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)444#define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)445#define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)446#define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)447#define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)448 449#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)450#define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)451 452#define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)453#define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)454#define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)455#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)456#define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)457#define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)458#define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)459#define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)460#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)461#define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)462#define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)463#define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)464#define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)465 466#define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)467#define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)468#define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)469#define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)470#define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)471#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)472#define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)473#define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)474#define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)475#define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)476#define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)477#define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)478#define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)479 480#define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)481#define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)482#define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)483#define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)484#define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)485#define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)486#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)487#define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)488 489#define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)490#define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)491#define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)492#define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)493#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)494#define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)495#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)496#define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)497 498 499 500/****************************************************************************501* Config Request Message502****************************************************************************/503typedef struct _MSG_CONFIG504{505 U8 Action; /* 00h */506 U8 Reserved; /* 01h */507 U8 ChainOffset; /* 02h */508 U8 Function; /* 03h */509 U16 ExtPageLength; /* 04h */510 U8 ExtPageType; /* 06h */511 U8 MsgFlags; /* 07h */512 U32 MsgContext; /* 08h */513 U8 Reserved2[8]; /* 0Ch */514 CONFIG_PAGE_HEADER Header; /* 14h */515 U32 PageAddress; /* 18h */516 SGE_IO_UNION PageBufferSGE; /* 1Ch */517} MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,518 Config_t, MPI_POINTER pConfig_t;519 520 521/****************************************************************************522* Action field values523****************************************************************************/524#define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)525#define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)526#define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)527#define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)528#define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)529#define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)530#define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)531 532 533/* Config Reply Message */534typedef struct _MSG_CONFIG_REPLY535{536 U8 Action; /* 00h */537 U8 Reserved; /* 01h */538 U8 MsgLength; /* 02h */539 U8 Function; /* 03h */540 U16 ExtPageLength; /* 04h */541 U8 ExtPageType; /* 06h */542 U8 MsgFlags; /* 07h */543 U32 MsgContext; /* 08h */544 U8 Reserved2[2]; /* 0Ch */545 U16 IOCStatus; /* 0Eh */546 U32 IOCLogInfo; /* 10h */547 CONFIG_PAGE_HEADER Header; /* 14h */548} MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,549 ConfigReply_t, MPI_POINTER pConfigReply_t;550 551 552 553/*****************************************************************************554*555* C o n f i g u r a t i o n P a g e s556*557*****************************************************************************/558 559/****************************************************************************560* Manufacturing Config pages561****************************************************************************/562#define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)563/* Fibre Channel */564#define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)565#define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)566#define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)567#define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)568#define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)569#define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)570#define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)571#define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646)572/* SCSI */573#define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)574#define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)575#define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)576#define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)577#define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)578#define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)579/* SAS */580#define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)581#define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)582#define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)583#define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)584#define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)585#define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)586#define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)587#define MPI_MANUFACTPAGE_DEVID_SAS1068_820XELP (0x0059)588#define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062)589 590 591typedef struct _CONFIG_PAGE_MANUFACTURING_0592{593 CONFIG_PAGE_HEADER Header; /* 00h */594 U8 ChipName[16]; /* 04h */595 U8 ChipRevision[8]; /* 14h */596 U8 BoardName[16]; /* 1Ch */597 U8 BoardAssembly[16]; /* 2Ch */598 U8 BoardTracerNumber[16]; /* 3Ch */599 600} CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,601 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;602 603#define MPI_MANUFACTURING0_PAGEVERSION (0x00)604 605 606typedef struct _CONFIG_PAGE_MANUFACTURING_1607{608 CONFIG_PAGE_HEADER Header; /* 00h */609 U8 VPD[256]; /* 04h */610} CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,611 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;612 613#define MPI_MANUFACTURING1_PAGEVERSION (0x00)614 615 616typedef struct _MPI_CHIP_REVISION_ID617{618 U16 DeviceID; /* 00h */619 U8 PCIRevisionID; /* 02h */620 U8 Reserved; /* 03h */621} MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,622 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;623 624 625/*626 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to627 * one and check Header.PageLength at runtime.628 */629#ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS630#define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)631#endif632 633typedef struct _CONFIG_PAGE_MANUFACTURING_2634{635 CONFIG_PAGE_HEADER Header; /* 00h */636 MPI_CHIP_REVISION_ID ChipId; /* 04h */637 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */638} CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,639 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;640 641#define MPI_MANUFACTURING2_PAGEVERSION (0x00)642 643 644/*645 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to646 * one and check Header.PageLength at runtime.647 */648#ifndef MPI_MAN_PAGE_3_INFO_WORDS649#define MPI_MAN_PAGE_3_INFO_WORDS (1)650#endif651 652typedef struct _CONFIG_PAGE_MANUFACTURING_3653{654 CONFIG_PAGE_HEADER Header; /* 00h */655 MPI_CHIP_REVISION_ID ChipId; /* 04h */656 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */657} CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,658 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;659 660#define MPI_MANUFACTURING3_PAGEVERSION (0x00)661 662 663typedef struct _CONFIG_PAGE_MANUFACTURING_4664{665 CONFIG_PAGE_HEADER Header; /* 00h */666 U32 Reserved1; /* 04h */667 U8 InfoOffset0; /* 08h */668 U8 InfoSize0; /* 09h */669 U8 InfoOffset1; /* 0Ah */670 U8 InfoSize1; /* 0Bh */671 U8 InquirySize; /* 0Ch */672 U8 Flags; /* 0Dh */673 U16 ExtFlags; /* 0Eh */674 U8 InquiryData[56]; /* 10h */675 U32 ISVolumeSettings; /* 48h */676 U32 IMEVolumeSettings; /* 4Ch */677 U32 IMVolumeSettings; /* 50h */678 U32 Reserved3; /* 54h */679 U32 Reserved4; /* 58h */680 U32 Reserved5; /* 5Ch */681 U8 IMEDataScrubRate; /* 60h */682 U8 IMEResyncRate; /* 61h */683 U16 Reserved6; /* 62h */684 U8 IMDataScrubRate; /* 64h */685 U8 IMResyncRate; /* 65h */686 U16 Reserved7; /* 66h */687 U32 Reserved8; /* 68h */688 U32 Reserved9; /* 6Ch */689} CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,690 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;691 692#define MPI_MANUFACTURING4_PAGEVERSION (0x05)693 694/* defines for the Flags field */695#define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80)696#define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40)697#define MPI_MANPAGE4_IME_DISABLE (0x20)698#define MPI_MANPAGE4_IM_DISABLE (0x10)699#define MPI_MANPAGE4_IS_DISABLE (0x08)700#define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04)701#define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02)702#define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)703 704/* defines for the ExtFlags field */705#define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180)706#define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7)707#define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0)708#define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1)709 710#define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040)711#define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020)712#define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010)713#define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008)714#define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004)715#define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002)716#define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001)717 718 719#ifndef MPI_MANPAGE5_NUM_FORCEWWID720#define MPI_MANPAGE5_NUM_FORCEWWID (1)721#endif722 723typedef struct _CONFIG_PAGE_MANUFACTURING_5724{725 CONFIG_PAGE_HEADER Header; /* 00h */726 U64 BaseWWID; /* 04h */727 U8 Flags; /* 0Ch */728 U8 NumForceWWID; /* 0Dh */729 U16 Reserved2; /* 0Eh */730 U32 Reserved3; /* 10h */731 U32 Reserved4; /* 14h */732 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */733} CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,734 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;735 736#define MPI_MANUFACTURING5_PAGEVERSION (0x02)737 738/* defines for the Flags field */739#define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)740 741 742typedef struct _CONFIG_PAGE_MANUFACTURING_6743{744 CONFIG_PAGE_HEADER Header; /* 00h */745 U32 ProductSpecificInfo;/* 04h */746} CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,747 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;748 749#define MPI_MANUFACTURING6_PAGEVERSION (0x00)750 751 752typedef struct _MPI_MANPAGE7_CONNECTOR_INFO753{754 U32 Pinout; /* 00h */755 U8 Connector[16]; /* 04h */756 U8 Location; /* 14h */757 U8 Reserved1; /* 15h */758 U16 Slot; /* 16h */759 U32 Reserved2; /* 18h */760} MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO,761 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t;762 763/* defines for the Pinout field */764#define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000)765#define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000)766#define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000)767#define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000)768#define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800)769#define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400)770#define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200)771#define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100)772#define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002)773#define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001)774 775/* defines for the Location field */776#define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01)777#define MPI_MANPAGE7_LOCATION_INTERNAL (0x02)778#define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04)779#define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08)780#define MPI_MANPAGE7_LOCATION_AUTO (0x10)781#define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20)782#define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)783 784/*785 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to786 * one and check NumPhys at runtime.787 */788#ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX789#define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1)790#endif791 792typedef struct _CONFIG_PAGE_MANUFACTURING_7793{794 CONFIG_PAGE_HEADER Header; /* 00h */795 U32 Reserved1; /* 04h */796 U32 Reserved2; /* 08h */797 U32 Flags; /* 0Ch */798 U8 EnclosureName[16]; /* 10h */799 U8 NumPhys; /* 20h */800 U8 Reserved3; /* 21h */801 U16 Reserved4; /* 22h */802 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */803} CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7,804 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t;805 806#define MPI_MANUFACTURING7_PAGEVERSION (0x00)807 808/* defines for the Flags field */809#define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)810 811 812typedef struct _CONFIG_PAGE_MANUFACTURING_8813{814 CONFIG_PAGE_HEADER Header; /* 00h */815 U32 ProductSpecificInfo;/* 04h */816} CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8,817 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t;818 819#define MPI_MANUFACTURING8_PAGEVERSION (0x00)820 821 822typedef struct _CONFIG_PAGE_MANUFACTURING_9823{824 CONFIG_PAGE_HEADER Header; /* 00h */825 U32 ProductSpecificInfo;/* 04h */826} CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9,827 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t;828 829#define MPI_MANUFACTURING9_PAGEVERSION (0x00)830 831 832typedef struct _CONFIG_PAGE_MANUFACTURING_10833{834 CONFIG_PAGE_HEADER Header; /* 00h */835 U32 ProductSpecificInfo;/* 04h */836} CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10,837 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t;838 839#define MPI_MANUFACTURING10_PAGEVERSION (0x00)840 841 842/****************************************************************************843* IO Unit Config Pages844****************************************************************************/845 846typedef struct _CONFIG_PAGE_IO_UNIT_0847{848 CONFIG_PAGE_HEADER Header; /* 00h */849 U64 UniqueValue; /* 04h */850} CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,851 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;852 853#define MPI_IOUNITPAGE0_PAGEVERSION (0x00)854 855 856typedef struct _CONFIG_PAGE_IO_UNIT_1857{858 CONFIG_PAGE_HEADER Header; /* 00h */859 U32 Flags; /* 04h */860} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,861 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;862 863#define MPI_IOUNITPAGE1_PAGEVERSION (0x02)864 865/* IO Unit Page 1 Flags defines */866#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)867#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)868#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)869#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)870#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)871#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)872#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)873#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)874#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)875#define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)876 877typedef struct _MPI_ADAPTER_INFO878{879 U8 PciBusNumber; /* 00h */880 U8 PciDeviceAndFunctionNumber; /* 01h */881 U16 AdapterFlags; /* 02h */882} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,883 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;884 885#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)886#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)887 888typedef struct _CONFIG_PAGE_IO_UNIT_2889{890 CONFIG_PAGE_HEADER Header; /* 00h */891 U32 Flags; /* 04h */892 U32 BiosVersion; /* 08h */893 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */894 U32 Reserved1; /* 1Ch */895} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,896 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;897 898#define MPI_IOUNITPAGE2_PAGEVERSION (0x02)899 900#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)901#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)902#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)903#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)904 905#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)906#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)907#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)908#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)909 910 911/*912 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to913 * one and check Header.PageLength at runtime.914 */915#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX916#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)917#endif918 919typedef struct _CONFIG_PAGE_IO_UNIT_3920{921 CONFIG_PAGE_HEADER Header; /* 00h */922 U8 GPIOCount; /* 04h */923 U8 Reserved1; /* 05h */924 U16 Reserved2; /* 06h */925 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */926} CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,927 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;928 929#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)930 931#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)932#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)933#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)934#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)935 936 937typedef struct _CONFIG_PAGE_IO_UNIT_4938{939 CONFIG_PAGE_HEADER Header; /* 00h */940 U32 Reserved1; /* 04h */941 SGE_SIMPLE_UNION FWImageSGE; /* 08h */942} CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,943 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;944 945#define MPI_IOUNITPAGE4_PAGEVERSION (0x00)946 947 948/****************************************************************************949* IOC Config Pages950****************************************************************************/951 952typedef struct _CONFIG_PAGE_IOC_0953{954 CONFIG_PAGE_HEADER Header; /* 00h */955 U32 TotalNVStore; /* 04h */956 U32 FreeNVStore; /* 08h */957 U16 VendorID; /* 0Ch */958 U16 DeviceID; /* 0Eh */959 U8 RevisionID; /* 10h */960 U8 Reserved[3]; /* 11h */961 U32 ClassCode; /* 14h */962 U16 SubsystemVendorID; /* 18h */963 U16 SubsystemID; /* 1Ah */964} CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,965 IOCPage0_t, MPI_POINTER pIOCPage0_t;966 967#define MPI_IOCPAGE0_PAGEVERSION (0x01)968 969 970typedef struct _CONFIG_PAGE_IOC_1971{972 CONFIG_PAGE_HEADER Header; /* 00h */973 U32 Flags; /* 04h */974 U32 CoalescingTimeout; /* 08h */975 U8 CoalescingDepth; /* 0Ch */976 U8 PCISlotNum; /* 0Dh */977 U8 Reserved[2]; /* 0Eh */978} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,979 IOCPage1_t, MPI_POINTER pIOCPage1_t;980 981#define MPI_IOCPAGE1_PAGEVERSION (0x03)982 983/* defines for the Flags field */984#define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)985#define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)986#define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)987#define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)988#define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)989#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)990 991#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)992 993 994typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL995{996 U8 VolumeID; /* 00h */997 U8 VolumeBus; /* 01h */998 U8 VolumeIOC; /* 02h */999 U8 VolumePageNumber; /* 03h */1000 U8 VolumeType; /* 04h */1001 U8 Flags; /* 05h */1002 U16 Reserved3; /* 06h */1003} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,1004 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;1005 1006/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */1007 1008#define MPI_RAID_VOL_TYPE_IS (0x00)1009#define MPI_RAID_VOL_TYPE_IME (0x01)1010#define MPI_RAID_VOL_TYPE_IM (0x02)1011#define MPI_RAID_VOL_TYPE_RAID_5 (0x03)1012#define MPI_RAID_VOL_TYPE_RAID_6 (0x04)1013#define MPI_RAID_VOL_TYPE_RAID_10 (0x05)1014#define MPI_RAID_VOL_TYPE_RAID_50 (0x06)1015#define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)1016 1017/* IOC Page 2 Volume Flags values */1018 1019#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)1020 1021typedef struct _CONFIG_PAGE_IOC_21022{1023 CONFIG_PAGE_HEADER Header; /* 00h */1024 U32 CapabilitiesFlags; /* 04h */1025 U8 NumActiveVolumes; /* 08h */1026 U8 MaxVolumes; /* 09h */1027 U8 NumActivePhysDisks; /* 0Ah */1028 U8 MaxPhysDisks; /* 0Bh */1029 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[] __counted_by(NumActiveVolumes); /* 0Ch */1030} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,1031 IOCPage2_t, MPI_POINTER pIOCPage2_t;1032 1033#define MPI_IOCPAGE2_PAGEVERSION (0x04)1034 1035/* IOC Page 2 Capabilities flags */1036 1037#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)1038#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)1039#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)1040#define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)1041#define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)1042#define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)1043#define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)1044#define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000)1045#define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)1046#define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)1047#define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)1048 1049 1050typedef struct _IOC_3_PHYS_DISK1051{1052 U8 PhysDiskID; /* 00h */1053 U8 PhysDiskBus; /* 01h */1054 U8 PhysDiskIOC; /* 02h */1055 U8 PhysDiskNum; /* 03h */1056} IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,1057 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;1058 1059typedef struct _CONFIG_PAGE_IOC_31060{1061 CONFIG_PAGE_HEADER Header; /* 00h */1062 U8 NumPhysDisks; /* 04h */1063 U8 Reserved1; /* 05h */1064 U16 Reserved2; /* 06h */1065 IOC_3_PHYS_DISK PhysDisk[] __counted_by(NumPhysDisks); /* 08h */1066} CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,1067 IOCPage3_t, MPI_POINTER pIOCPage3_t;1068 1069#define MPI_IOCPAGE3_PAGEVERSION (0x00)1070 1071 1072typedef struct _IOC_4_SEP1073{1074 U8 SEPTargetID; /* 00h */1075 U8 SEPBus; /* 01h */1076 U16 Reserved; /* 02h */1077} IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,1078 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;1079 1080typedef struct _CONFIG_PAGE_IOC_41081{1082 CONFIG_PAGE_HEADER Header; /* 00h */1083 U8 ActiveSEP; /* 04h */1084 U8 MaxSEP; /* 05h */1085 U16 Reserved1; /* 06h */1086 IOC_4_SEP SEP[] __counted_by(ActiveSEP); /* 08h */1087} CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,1088 IOCPage4_t, MPI_POINTER pIOCPage4_t;1089 1090#define MPI_IOCPAGE4_PAGEVERSION (0x00)1091 1092 1093typedef struct _IOC_5_HOT_SPARE1094{1095 U8 PhysDiskNum; /* 00h */1096 U8 Reserved; /* 01h */1097 U8 HotSparePool; /* 02h */1098 U8 Flags; /* 03h */1099} IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,1100 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;1101 1102/* IOC Page 5 HotSpare Flags */1103#define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)1104 1105/*1106 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to1107 * one and check Header.PageLength at runtime.1108 */1109#ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX1110#define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)1111#endif1112 1113typedef struct _CONFIG_PAGE_IOC_51114{1115 CONFIG_PAGE_HEADER Header; /* 00h */1116 U32 Reserved1; /* 04h */1117 U8 NumHotSpares; /* 08h */1118 U8 Reserved2; /* 09h */1119 U16 Reserved3; /* 0Ah */1120 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */1121} CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,1122 IOCPage5_t, MPI_POINTER pIOCPage5_t;1123 1124#define MPI_IOCPAGE5_PAGEVERSION (0x00)1125 1126typedef struct _CONFIG_PAGE_IOC_61127{1128 CONFIG_PAGE_HEADER Header; /* 00h */1129 U32 CapabilitiesFlags; /* 04h */1130 U8 MaxDrivesIS; /* 08h */1131 U8 MaxDrivesIM; /* 09h */1132 U8 MaxDrivesIME; /* 0Ah */1133 U8 Reserved1; /* 0Bh */1134 U8 MinDrivesIS; /* 0Ch */1135 U8 MinDrivesIM; /* 0Dh */1136 U8 MinDrivesIME; /* 0Eh */1137 U8 Reserved2; /* 0Fh */1138 U8 MaxGlobalHotSpares; /* 10h */1139 U8 Reserved3; /* 11h */1140 U16 Reserved4; /* 12h */1141 U32 Reserved5; /* 14h */1142 U32 SupportedStripeSizeMapIS; /* 18h */1143 U32 SupportedStripeSizeMapIME; /* 1Ch */1144 U32 Reserved6; /* 20h */1145 U8 MetadataSize; /* 24h */1146 U8 Reserved7; /* 25h */1147 U16 Reserved8; /* 26h */1148 U16 MaxBadBlockTableEntries; /* 28h */1149 U16 Reserved9; /* 2Ah */1150 U16 IRNvsramUsage; /* 2Ch */1151 U16 Reserved10; /* 2Eh */1152 U32 IRNvsramVersion; /* 30h */1153 U32 Reserved11; /* 34h */1154 U32 Reserved12; /* 38h */1155} CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6,1156 IOCPage6_t, MPI_POINTER pIOCPage6_t;1157 1158#define MPI_IOCPAGE6_PAGEVERSION (0x01)1159 1160/* IOC Page 6 Capabilities Flags */1161 1162#define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020)1163#define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010)1164#define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008)1165 1166#define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006)1167#define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000)1168#define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002)1169 1170#define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)1171 1172 1173/****************************************************************************1174* BIOS Config Pages1175****************************************************************************/1176 1177typedef struct _CONFIG_PAGE_BIOS_11178{1179 CONFIG_PAGE_HEADER Header; /* 00h */1180 U32 BiosOptions; /* 04h */1181 U32 IOCSettings; /* 08h */1182 U32 Reserved1; /* 0Ch */1183 U32 DeviceSettings; /* 10h */1184 U16 NumberOfDevices; /* 14h */1185 U8 ExpanderSpinup; /* 16h */1186 U8 Reserved2; /* 17h */1187 U16 IOTimeoutBlockDevicesNonRM; /* 18h */1188 U16 IOTimeoutSequential; /* 1Ah */1189 U16 IOTimeoutOther; /* 1Ch */1190 U16 IOTimeoutBlockDevicesRM; /* 1Eh */1191} CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,1192 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;1193 1194#define MPI_BIOSPAGE1_PAGEVERSION (0x03)1195 1196/* values for the BiosOptions field */1197#define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)1198#define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)1199#define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)1200#define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)1201 1202/* values for the IOCSettings field */1203#define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000)1204#define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24)1205 1206#define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)1207#define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)1208 1209#define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000)1210#define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000)1211 1212#define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)1213#define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)1214#define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)1215 1216#define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)1217#define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)1218 1219#define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)1220#define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)1221 1222#define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)1223#define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)1224#define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)1225#define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)1226 1227#define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)1228#define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)1229#define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)1230#define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)1231#define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)1232 1233#define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)1234 1235/* values for the DeviceSettings field */1236#define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)1237#define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)1238#define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)1239#define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)1240#define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)1241 1242/* defines for the ExpanderSpinup field */1243#define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0)1244#define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4)1245#define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F)1246 1247typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER1248{1249 U32 Reserved1; /* 00h */1250 U32 Reserved2; /* 04h */1251 U32 Reserved3; /* 08h */1252 U32 Reserved4; /* 0Ch */1253 U32 Reserved5; /* 10h */1254 U32 Reserved6; /* 14h */1255 U32 Reserved7; /* 18h */1256 U32 Reserved8; /* 1Ch */1257 U32 Reserved9; /* 20h */1258 U32 Reserved10; /* 24h */1259 U32 Reserved11; /* 28h */1260 U32 Reserved12; /* 2Ch */1261 U32 Reserved13; /* 30h */1262 U32 Reserved14; /* 34h */1263 U32 Reserved15; /* 38h */1264 U32 Reserved16; /* 3Ch */1265 U32 Reserved17; /* 40h */1266} MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;1267 1268typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER1269{1270 U8 TargetID; /* 00h */1271 U8 Bus; /* 01h */1272 U8 AdapterNumber; /* 02h */1273 U8 Reserved1; /* 03h */1274 U32 Reserved2; /* 04h */1275 U32 Reserved3; /* 08h */1276 U32 Reserved4; /* 0Ch */1277 U8 LUN[8]; /* 10h */1278 U32 Reserved5; /* 18h */1279 U32 Reserved6; /* 1Ch */1280 U32 Reserved7; /* 20h */1281 U32 Reserved8; /* 24h */1282 U32 Reserved9; /* 28h */1283 U32 Reserved10; /* 2Ch */1284 U32 Reserved11; /* 30h */1285 U32 Reserved12; /* 34h */1286 U32 Reserved13; /* 38h */1287 U32 Reserved14; /* 3Ch */1288 U32 Reserved15; /* 40h */1289} MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;1290 1291typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS1292{1293 U8 TargetID; /* 00h */1294 U8 Bus; /* 01h */1295 U16 PCIAddress; /* 02h */1296 U32 Reserved1; /* 04h */1297 U32 Reserved2; /* 08h */1298 U32 Reserved3; /* 0Ch */1299 U8 LUN[8]; /* 10h */1300 U32 Reserved4; /* 18h */1301 U32 Reserved5; /* 1Ch */1302 U32 Reserved6; /* 20h */1303 U32 Reserved7; /* 24h */1304 U32 Reserved8; /* 28h */1305 U32 Reserved9; /* 2Ch */1306 U32 Reserved10; /* 30h */1307 U32 Reserved11; /* 34h */1308 U32 Reserved12; /* 38h */1309 U32 Reserved13; /* 3Ch */1310 U32 Reserved14; /* 40h */1311} MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;1312 1313typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER1314{1315 U8 TargetID; /* 00h */1316 U8 Bus; /* 01h */1317 U8 PCISlotNumber; /* 02h */1318 U8 Reserved1; /* 03h */1319 U32 Reserved2; /* 04h */1320 U32 Reserved3; /* 08h */1321 U32 Reserved4; /* 0Ch */1322 U8 LUN[8]; /* 10h */1323 U32 Reserved5; /* 18h */1324 U32 Reserved6; /* 1Ch */1325 U32 Reserved7; /* 20h */1326 U32 Reserved8; /* 24h */1327 U32 Reserved9; /* 28h */1328 U32 Reserved10; /* 2Ch */1329 U32 Reserved11; /* 30h */1330 U32 Reserved12; /* 34h */1331 U32 Reserved13; /* 38h */1332 U32 Reserved14; /* 3Ch */1333 U32 Reserved15; /* 40h */1334} MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;1335 1336typedef struct _MPI_BOOT_DEVICE_FC_WWN1337{1338 U64 WWPN; /* 00h */1339 U32 Reserved1; /* 08h */1340 U32 Reserved2; /* 0Ch */1341 U8 LUN[8]; /* 10h */1342 U32 Reserved3; /* 18h */1343 U32 Reserved4; /* 1Ch */1344 U32 Reserved5; /* 20h */1345 U32 Reserved6; /* 24h */1346 U32 Reserved7; /* 28h */1347 U32 Reserved8; /* 2Ch */1348 U32 Reserved9; /* 30h */1349 U32 Reserved10; /* 34h */1350 U32 Reserved11; /* 38h */1351 U32 Reserved12; /* 3Ch */1352 U32 Reserved13; /* 40h */1353} MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;1354 1355typedef struct _MPI_BOOT_DEVICE_SAS_WWN1356{1357 U64 SASAddress; /* 00h */1358 U32 Reserved1; /* 08h */1359 U32 Reserved2; /* 0Ch */1360 U8 LUN[8]; /* 10h */1361 U32 Reserved3; /* 18h */1362 U32 Reserved4; /* 1Ch */1363 U32 Reserved5; /* 20h */1364 U32 Reserved6; /* 24h */1365 U32 Reserved7; /* 28h */1366 U32 Reserved8; /* 2Ch */1367 U32 Reserved9; /* 30h */1368 U32 Reserved10; /* 34h */1369 U32 Reserved11; /* 38h */1370 U32 Reserved12; /* 3Ch */1371 U32 Reserved13; /* 40h */1372} MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;1373 1374typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT1375{1376 U64 EnclosureLogicalID; /* 00h */1377 U32 Reserved1; /* 08h */1378 U32 Reserved2; /* 0Ch */1379 U8 LUN[8]; /* 10h */1380 U16 SlotNumber; /* 18h */1381 U16 Reserved3; /* 1Ah */1382 U32 Reserved4; /* 1Ch */1383 U32 Reserved5; /* 20h */1384 U32 Reserved6; /* 24h */1385 U32 Reserved7; /* 28h */1386 U32 Reserved8; /* 2Ch */1387 U32 Reserved9; /* 30h */1388 U32 Reserved10; /* 34h */1389 U32 Reserved11; /* 38h */1390 U32 Reserved12; /* 3Ch */1391 U32 Reserved13; /* 40h */1392} MPI_BOOT_DEVICE_ENCLOSURE_SLOT,1393 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;1394 1395typedef union _MPI_BIOSPAGE2_BOOT_DEVICE1396{1397 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;1398 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;1399 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;1400 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;1401 MPI_BOOT_DEVICE_FC_WWN FcWwn;1402 MPI_BOOT_DEVICE_SAS_WWN SasWwn;1403 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;1404} MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;1405 1406typedef struct _CONFIG_PAGE_BIOS_21407{1408 CONFIG_PAGE_HEADER Header; /* 00h */1409 U32 Reserved1; /* 04h */1410 U32 Reserved2; /* 08h */1411 U32 Reserved3; /* 0Ch */1412 U32 Reserved4; /* 10h */1413 U32 Reserved5; /* 14h */1414 U32 Reserved6; /* 18h */1415 U8 BootDeviceForm; /* 1Ch */1416 U8 PrevBootDeviceForm; /* 1Ch */1417 U16 Reserved8; /* 1Eh */1418 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */1419} CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,1420 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;1421 1422#define MPI_BIOSPAGE2_PAGEVERSION (0x02)1423 1424#define MPI_BIOSPAGE2_FORM_MASK (0x0F)1425#define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)1426#define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)1427#define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)1428#define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)1429#define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)1430#define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)1431#define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)1432 1433typedef struct _CONFIG_PAGE_BIOS_41434{1435 CONFIG_PAGE_HEADER Header; /* 00h */1436 U64 ReassignmentBaseWWID; /* 04h */1437} CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4,1438 BIOSPage4_t, MPI_POINTER pBIOSPage4_t;1439 1440#define MPI_BIOSPAGE4_PAGEVERSION (0x00)1441 1442 1443/****************************************************************************1444* SCSI Port Config Pages1445****************************************************************************/1446 1447typedef struct _CONFIG_PAGE_SCSI_PORT_01448{1449 CONFIG_PAGE_HEADER Header; /* 00h */1450 U32 Capabilities; /* 04h */1451 U32 PhysicalInterface; /* 08h */1452} CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,1453 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;1454 1455#define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)1456 1457#define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)1458#define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)1459#define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)1460#define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)1461#define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)1462#define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)1463#define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)1464#define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)1465#define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)1466#define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)1467#define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)1468#define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)1469#define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)1470 1471#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)1472#define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \1473 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \1474 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \1475 )1476#define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)1477#define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)1478#define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \1479 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \1480 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \1481 )1482#define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)1483#define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)1484#define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)1485 1486#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)1487#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)1488#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)1489#define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)1490#define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)1491#define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)1492#define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)1493#define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)1494 1495 1496typedef struct _CONFIG_PAGE_SCSI_PORT_11497{1498 CONFIG_PAGE_HEADER Header; /* 00h */1499 U32 Configuration; /* 04h */1500 U32 OnBusTimerValue; /* 08h */1501 U8 TargetConfig; /* 0Ch */1502 U8 Reserved1; /* 0Dh */1503 U16 IDConfig; /* 0Eh */1504} CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,1505 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;1506 1507#define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)1508 1509/* Configuration values */1510#define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)1511#define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)1512#define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)1513 1514/* TargetConfig values */1515#define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)1516#define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)1517 1518 1519typedef struct _MPI_DEVICE_INFO1520{1521 U8 Timeout; /* 00h */1522 U8 SyncFactor; /* 01h */1523 U16 DeviceFlags; /* 02h */1524} MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,1525 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;1526 1527typedef struct _CONFIG_PAGE_SCSI_PORT_21528{1529 CONFIG_PAGE_HEADER Header; /* 00h */1530 U32 PortFlags; /* 04h */1531 U32 PortSettings; /* 08h */1532 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */1533} CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,1534 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;1535 1536#define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)1537 1538/* PortFlags values */1539#define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)1540#define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)1541#define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)1542#define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)1543 1544#define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)1545#define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)1546#define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)1547#define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)1548 1549 1550/* PortSettings values */1551#define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)1552#define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)1553#define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)1554#define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)1555#define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)1556#define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)1557#define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)1558#define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)1559#define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)1560#define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)1561#define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)1562#define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)1563#define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)1564#define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)1565#define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)1566#define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)1567 1568#define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)1569#define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)1570#define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)1571#define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)1572#define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)1573#define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)1574 1575 1576/****************************************************************************1577* SCSI Target Device Config Pages1578****************************************************************************/1579 1580typedef struct _CONFIG_PAGE_SCSI_DEVICE_01581{1582 CONFIG_PAGE_HEADER Header; /* 00h */1583 U32 NegotiatedParameters; /* 04h */1584 U32 Information; /* 08h */1585} CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,1586 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;1587 1588#define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)1589 1590#define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)1591#define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)1592#define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)1593#define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)1594#define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)1595#define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)1596#define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)1597#define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)1598#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)1599#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)1600#define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)1601#define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)1602#define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)1603#define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)1604#define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)1605 1606#define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)1607#define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)1608#define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)1609#define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)1610 1611 1612typedef struct _CONFIG_PAGE_SCSI_DEVICE_11613{1614 CONFIG_PAGE_HEADER Header; /* 00h */1615 U32 RequestedParameters; /* 04h */1616 U32 Reserved; /* 08h */1617 U32 Configuration; /* 0Ch */1618} CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,1619 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;1620 1621#define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)1622 1623#define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)1624#define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)1625#define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)1626#define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)1627#define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)1628#define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)1629#define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)1630#define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)1631#define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)1632#define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)1633#define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)1634#define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)1635#define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)1636#define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)1637#define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)1638 1639#define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)1640#define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)1641#define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)1642#define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)1643 1644 1645typedef struct _CONFIG_PAGE_SCSI_DEVICE_21646{1647 CONFIG_PAGE_HEADER Header; /* 00h */1648 U32 DomainValidation; /* 04h */1649 U32 ParityPipeSelect; /* 08h */1650 U32 DataPipeSelect; /* 0Ch */1651} CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,1652 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;1653 1654#define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)1655 1656#define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)1657#define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)1658#define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)1659#define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)1660#define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)1661#define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)1662#define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)1663#define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)1664#define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)1665 1666#define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)1667 1668#define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)1669#define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)1670#define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)1671#define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)1672#define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)1673#define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)1674#define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)1675#define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)1676#define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)1677#define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)1678#define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)1679#define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)1680#define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)1681#define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)1682#define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)1683#define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)1684 1685 1686typedef struct _CONFIG_PAGE_SCSI_DEVICE_31687{1688 CONFIG_PAGE_HEADER Header; /* 00h */1689 U16 MsgRejectCount; /* 04h */1690 U16 PhaseErrorCount; /* 06h */1691 U16 ParityErrorCount; /* 08h */1692 U16 Reserved; /* 0Ah */1693} CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,1694 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;1695 1696#define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)1697 1698#define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)1699#define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)1700 1701 1702/****************************************************************************1703* FC Port Config Pages1704****************************************************************************/1705 1706typedef struct _CONFIG_PAGE_FC_PORT_01707{1708 CONFIG_PAGE_HEADER Header; /* 00h */1709 U32 Flags; /* 04h */1710 U8 MPIPortNumber; /* 08h */1711 U8 LinkType; /* 09h */1712 U8 PortState; /* 0Ah */1713 U8 Reserved; /* 0Bh */1714 U32 PortIdentifier; /* 0Ch */1715 U64 WWNN; /* 10h */1716 U64 WWPN; /* 18h */1717 U32 SupportedServiceClass; /* 20h */1718 U32 SupportedSpeeds; /* 24h */1719 U32 CurrentSpeed; /* 28h */1720 U32 MaxFrameSize; /* 2Ch */1721 U64 FabricWWNN; /* 30h */1722 U64 FabricWWPN; /* 38h */1723 U32 DiscoveredPortsCount; /* 40h */1724 U32 MaxInitiators; /* 44h */1725 U8 MaxAliasesSupported; /* 48h */1726 U8 MaxHardAliasesSupported; /* 49h */1727 U8 NumCurrentAliases; /* 4Ah */1728 U8 Reserved1; /* 4Bh */1729} CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,1730 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;1731 1732#define MPI_FCPORTPAGE0_PAGEVERSION (0x02)1733 1734#define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)1735#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)1736#define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)1737#define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)1738#define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)1739 1740#define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)1741#define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)1742#define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)1743 1744#define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)1745#define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)1746#define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)1747#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)1748#define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)1749#define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)1750 1751#define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)1752#define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)1753#define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)1754#define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)1755#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)1756#define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)1757#define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)1758#define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)1759#define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)1760#define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)1761#define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)1762#define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)1763#define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)1764#define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)1765#define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)1766#define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)1767 1768#define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */1769#define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */1770#define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */1771#define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */1772#define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */1773#define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */1774#define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */1775#define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */1776 1777#define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)1778#define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)1779#define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)1780 1781#define MPI_FCPORTPAGE0_SUPPORT_SPEED_UNKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */1782#define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */1783#define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */1784#define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */1785#define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */1786 1787#define MPI_FCPORTPAGE0_CURRENT_SPEED_UNKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UNKNOWN1788#define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED1789#define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED1790#define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED1791#define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED1792#define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */1793 1794 1795typedef struct _CONFIG_PAGE_FC_PORT_11796{1797 CONFIG_PAGE_HEADER Header; /* 00h */1798 U32 Flags; /* 04h */1799 U64 NoSEEPROMWWNN; /* 08h */1800 U64 NoSEEPROMWWPN; /* 10h */1801 U8 HardALPA; /* 18h */1802 U8 LinkConfig; /* 19h */1803 U8 TopologyConfig; /* 1Ah */1804 U8 AltConnector; /* 1Bh */1805 U8 NumRequestedAliases; /* 1Ch */1806 U8 RR_TOV; /* 1Dh */1807 U8 InitiatorDeviceTimeout; /* 1Eh */1808 U8 InitiatorIoPendTimeout; /* 1Fh */1809} CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,1810 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;1811 1812#define MPI_FCPORTPAGE1_PAGEVERSION (0x06)1813 1814#define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)1815#define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)1816#define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)1817#define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)1818#define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)1819#define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)1820#define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)1821#define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)1822#define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)1823#define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)1824#define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)1825#define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)1826#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)1827#define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)1828 1829#define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)1830#define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)1831#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)1832#define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)1833#define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)1834#define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)1835 1836#define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)1837#define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)1838#define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)1839#define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)1840 1841#define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)1842 1843#define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)1844#define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)1845#define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)1846#define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)1847#define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)1848#define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)1849 1850#define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)1851#define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)1852#define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)1853#define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)1854 1855#define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)1856 1857#define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)1858#define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)1859 1860 1861typedef struct _CONFIG_PAGE_FC_PORT_21862{1863 CONFIG_PAGE_HEADER Header; /* 00h */1864 U8 NumberActive; /* 04h */1865 U8 ALPA[127]; /* 05h */1866} CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,1867 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;1868 1869#define MPI_FCPORTPAGE2_PAGEVERSION (0x01)1870 1871 1872typedef struct _WWN_FORMAT1873{1874 U64 WWNN; /* 00h */1875 U64 WWPN; /* 08h */1876} WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,1877 WWNFormat, MPI_POINTER pWWNFormat;1878 1879typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID1880{1881 WWN_FORMAT WWN;1882 U32 Did;1883} FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,1884 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;1885 1886typedef struct _FC_PORT_PERSISTENT1887{1888 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */1889 U8 TargetID; /* 10h */1890 U8 Bus; /* 11h */1891 U16 Flags; /* 12h */1892} FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,1893 PersistentData_t, MPI_POINTER pPersistentData_t;1894 1895#define MPI_PERSISTENT_FLAGS_SHIFT (16)1896#define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)1897#define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)1898#define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)1899#define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)1900#define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)1901 1902/*1903 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to1904 * one and check Header.PageLength at runtime.1905 */1906#ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX1907#define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)1908#endif1909 1910typedef struct _CONFIG_PAGE_FC_PORT_31911{1912 CONFIG_PAGE_HEADER Header; /* 00h */1913 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */1914} CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,1915 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;1916 1917#define MPI_FCPORTPAGE3_PAGEVERSION (0x01)1918 1919 1920typedef struct _CONFIG_PAGE_FC_PORT_41921{1922 CONFIG_PAGE_HEADER Header; /* 00h */1923 U32 PortFlags; /* 04h */1924 U32 PortSettings; /* 08h */1925} CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,1926 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;1927 1928#define MPI_FCPORTPAGE4_PAGEVERSION (0x00)1929 1930#define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)1931 1932#define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)1933#define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)1934#define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)1935#define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)1936#define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)1937#define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)1938#define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)1939 1940 1941typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO1942{1943 U8 Flags; /* 00h */1944 U8 AliasAlpa; /* 01h */1945 U16 Reserved; /* 02h */1946 U64 AliasWWNN; /* 04h */1947 U64 AliasWWPN; /* 0Ch */1948} CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,1949 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,1950 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;1951 1952typedef struct _CONFIG_PAGE_FC_PORT_51953{1954 CONFIG_PAGE_HEADER Header; /* 00h */1955 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */1956} CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,1957 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;1958 1959#define MPI_FCPORTPAGE5_PAGEVERSION (0x02)1960 1961#define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)1962#define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)1963#define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)1964#define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)1965#define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)1966 1967typedef struct _CONFIG_PAGE_FC_PORT_61968{1969 CONFIG_PAGE_HEADER Header; /* 00h */1970 U32 Reserved; /* 04h */1971 U64 TimeSinceReset; /* 08h */1972 U64 TxFrames; /* 10h */1973 U64 RxFrames; /* 18h */1974 U64 TxWords; /* 20h */1975 U64 RxWords; /* 28h */1976 U64 LipCount; /* 30h */1977 U64 NosCount; /* 38h */1978 U64 ErrorFrames; /* 40h */1979 U64 DumpedFrames; /* 48h */1980 U64 LinkFailureCount; /* 50h */1981 U64 LossOfSyncCount; /* 58h */1982 U64 LossOfSignalCount; /* 60h */1983 U64 PrimitiveSeqErrCount; /* 68h */1984 U64 InvalidTxWordCount; /* 70h */1985 U64 InvalidCrcCount; /* 78h */1986 U64 FcpInitiatorIoCount; /* 80h */1987} CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,1988 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;1989 1990#define MPI_FCPORTPAGE6_PAGEVERSION (0x00)1991 1992 1993typedef struct _CONFIG_PAGE_FC_PORT_71994{1995 CONFIG_PAGE_HEADER Header; /* 00h */1996 U32 Reserved; /* 04h */1997 U8 PortSymbolicName[256]; /* 08h */1998} CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,1999 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;2000 2001#define MPI_FCPORTPAGE7_PAGEVERSION (0x00)2002 2003 2004typedef struct _CONFIG_PAGE_FC_PORT_82005{2006 CONFIG_PAGE_HEADER Header; /* 00h */2007 U32 BitVector[8]; /* 04h */2008} CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,2009 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;2010 2011#define MPI_FCPORTPAGE8_PAGEVERSION (0x00)2012 2013 2014typedef struct _CONFIG_PAGE_FC_PORT_92015{2016 CONFIG_PAGE_HEADER Header; /* 00h */2017 U32 Reserved; /* 04h */2018 U64 GlobalWWPN; /* 08h */2019 U64 GlobalWWNN; /* 10h */2020 U32 UnitType; /* 18h */2021 U32 PhysicalPortNumber; /* 1Ch */2022 U32 NumAttachedNodes; /* 20h */2023 U16 IPVersion; /* 24h */2024 U16 UDPPortNumber; /* 26h */2025 U8 IPAddress[16]; /* 28h */2026 U16 Reserved1; /* 38h */2027 U16 TopologyDiscoveryFlags; /* 3Ah */2028} CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,2029 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;2030 2031#define MPI_FCPORTPAGE9_PAGEVERSION (0x00)2032 2033 2034typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA2035{2036 U8 Id; /* 10h */2037 U8 ExtId; /* 11h */2038 U8 Connector; /* 12h */2039 U8 Transceiver[8]; /* 13h */2040 U8 Encoding; /* 1Bh */2041 U8 BitRate_100mbs; /* 1Ch */2042 U8 Reserved1; /* 1Dh */2043 U8 Length9u_km; /* 1Eh */2044 U8 Length9u_100m; /* 1Fh */2045 U8 Length50u_10m; /* 20h */2046 U8 Length62p5u_10m; /* 21h */2047 U8 LengthCopper_m; /* 22h */2048 U8 Reseverved2; /* 22h */2049 U8 VendorName[16]; /* 24h */2050 U8 Reserved3; /* 34h */2051 U8 VendorOUI[3]; /* 35h */2052 U8 VendorPN[16]; /* 38h */2053 U8 VendorRev[4]; /* 48h */2054 U16 Wavelength; /* 4Ch */2055 U8 Reserved4; /* 4Eh */2056 U8 CC_BASE; /* 4Fh */2057} CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,2058 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,2059 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;2060 2061#define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)2062#define MPI_FCPORT10_BASE_ID_GBIC (0x01)2063#define MPI_FCPORT10_BASE_ID_FIXED (0x02)2064#define MPI_FCPORT10_BASE_ID_SFP (0x03)2065#define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)2066#define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)2067#define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)2068 2069#define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)2070#define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)2071#define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)2072#define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)2073#define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)2074#define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)2075#define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)2076#define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)2077#define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)2078 2079#define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)2080#define MPI_FCPORT10_BASE_CONN_SC (0x01)2081#define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)2082#define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)2083#define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)2084#define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)2085#define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)2086#define MPI_FCPORT10_BASE_CONN_LC (0x07)2087#define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)2088#define MPI_FCPORT10_BASE_CONN_MU (0x09)2089#define MPI_FCPORT10_BASE_CONN_SG (0x0A)2090#define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)2091#define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)2092#define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)2093#define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)2094#define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)2095#define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)2096#define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)2097#define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)2098 2099#define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)2100#define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)2101#define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)2102#define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)2103#define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)2104 2105 2106typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA2107{2108 U8 Options[2]; /* 50h */2109 U8 BitRateMax; /* 52h */2110 U8 BitRateMin; /* 53h */2111 U8 VendorSN[16]; /* 54h */2112 U8 DateCode[8]; /* 64h */2113 U8 DiagMonitoringType; /* 6Ch */2114 U8 EnhancedOptions; /* 6Dh */2115 U8 SFF8472Compliance; /* 6Eh */2116 U8 CC_EXT; /* 6Fh */2117} CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,2118 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,2119 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;2120 2121#define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)2122#define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)2123#define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)2124#define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)2125#define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)2126 2127 2128typedef struct _CONFIG_PAGE_FC_PORT_102129{2130 CONFIG_PAGE_HEADER Header; /* 00h */2131 U8 Flags; /* 04h */2132 U8 Reserved1; /* 05h */2133 U16 Reserved2; /* 06h */2134 U32 HwConfig1; /* 08h */2135 U32 HwConfig2; /* 0Ch */2136 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */2137 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */2138 U8 VendorSpecific[32]; /* 70h */2139} CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,2140 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;2141 2142#define MPI_FCPORTPAGE10_PAGEVERSION (0x01)2143 2144/* standard MODDEF pin definitions (from GBIC spec.) */2145#define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)2146#define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)2147#define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)2148#define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)2149#define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)2150#define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)2151#define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)2152#define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)2153#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)2154#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)2155#define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)2156#define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)2157 2158#define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)2159#define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)2160 2161 2162/****************************************************************************2163* FC Device Config Pages2164****************************************************************************/2165 2166typedef struct _CONFIG_PAGE_FC_DEVICE_02167{2168 CONFIG_PAGE_HEADER Header; /* 00h */2169 U64 WWNN; /* 04h */2170 U64 WWPN; /* 0Ch */2171 U32 PortIdentifier; /* 14h */2172 U8 Protocol; /* 18h */2173 U8 Flags; /* 19h */2174 U16 BBCredit; /* 1Ah */2175 U16 MaxRxFrameSize; /* 1Ch */2176 U8 ADISCHardALPA; /* 1Eh */2177 U8 PortNumber; /* 1Fh */2178 U8 FcPhLowestVersion; /* 20h */2179 U8 FcPhHighestVersion; /* 21h */2180 U8 CurrentTargetID; /* 22h */2181 U8 CurrentBus; /* 23h */2182} CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,2183 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;2184 2185#define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)2186 2187#define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)2188#define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)2189#define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)2190 2191#define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)2192#define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)2193#define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)2194#define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)2195 2196#define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)2197#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)2198#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)2199#define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)2200#define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)2201#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)2202#define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)2203#define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)2204 2205#define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)2206 2207/****************************************************************************2208* RAID Volume Config Pages2209****************************************************************************/2210 2211typedef struct _RAID_VOL0_PHYS_DISK2212{2213 U16 Reserved; /* 00h */2214 U8 PhysDiskMap; /* 02h */2215 U8 PhysDiskNum; /* 03h */2216} RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,2217 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;2218 2219#define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)2220#define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)2221 2222typedef struct _RAID_VOL0_STATUS2223{2224 U8 Flags; /* 00h */2225 U8 State; /* 01h */2226 U16 Reserved; /* 02h */2227} RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,2228 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;2229 2230/* RAID Volume Page 0 VolumeStatus defines */2231#define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)2232#define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)2233#define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)2234#define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)2235#define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)2236 2237#define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)2238#define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)2239#define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)2240#define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)2241 2242typedef struct _RAID_VOL0_SETTINGS2243{2244 U16 Settings; /* 00h */2245 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */2246 U8 Reserved; /* 02h */2247} RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,2248 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;2249 2250/* RAID Volume Page 0 VolumeSettings defines */2251#define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)2252#define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)2253#define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)2254#define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)2255#define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */2256 2257#define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0)2258#define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000)2259#define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040)2260 2261#define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)2262#define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)2263 2264/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */2265#define MPI_RAID_HOT_SPARE_POOL_0 (0x01)2266#define MPI_RAID_HOT_SPARE_POOL_1 (0x02)2267#define MPI_RAID_HOT_SPARE_POOL_2 (0x04)2268#define MPI_RAID_HOT_SPARE_POOL_3 (0x08)2269#define MPI_RAID_HOT_SPARE_POOL_4 (0x10)2270#define MPI_RAID_HOT_SPARE_POOL_5 (0x20)2271#define MPI_RAID_HOT_SPARE_POOL_6 (0x40)2272#define MPI_RAID_HOT_SPARE_POOL_7 (0x80)2273 2274typedef struct _CONFIG_PAGE_RAID_VOL_02275{2276 CONFIG_PAGE_HEADER Header; /* 00h */2277 U8 VolumeID; /* 04h */2278 U8 VolumeBus; /* 05h */2279 U8 VolumeIOC; /* 06h */2280 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */2281 RAID_VOL0_STATUS VolumeStatus; /* 08h */2282 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */2283 U32 MaxLBA; /* 10h */2284 U32 MaxLBAHigh; /* 14h */2285 U32 StripeSize; /* 18h */2286 U32 Reserved2; /* 1Ch */2287 U32 Reserved3; /* 20h */2288 U8 NumPhysDisks; /* 24h */2289 U8 DataScrubRate; /* 25h */2290 U8 ResyncRate; /* 26h */2291 U8 InactiveStatus; /* 27h */2292 RAID_VOL0_PHYS_DISK PhysDisk[] __counted_by(NumPhysDisks); /* 28h */2293} CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,2294 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;2295 2296#define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07)2297 2298/* values for RAID Volume Page 0 InactiveStatus field */2299#define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)2300#define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)2301#define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)2302#define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)2303#define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)2304#define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)2305#define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)2306 2307 2308typedef struct _CONFIG_PAGE_RAID_VOL_12309{2310 CONFIG_PAGE_HEADER Header; /* 00h */2311 U8 VolumeID; /* 04h */2312 U8 VolumeBus; /* 05h */2313 U8 VolumeIOC; /* 06h */2314 U8 Reserved0; /* 07h */2315 U8 GUID[24]; /* 08h */2316 U8 Name[32]; /* 20h */2317 U64 WWID; /* 40h */2318 U32 Reserved1; /* 48h */2319 U32 Reserved2; /* 4Ch */2320} CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,2321 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;2322 2323#define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)2324 2325 2326/****************************************************************************2327* RAID Physical Disk Config Pages2328****************************************************************************/2329 2330typedef struct _RAID_PHYS_DISK0_ERROR_DATA2331{2332 U8 ErrorCdbByte; /* 00h */2333 U8 ErrorSenseKey; /* 01h */2334 U16 Reserved; /* 02h */2335 U16 ErrorCount; /* 04h */2336 U8 ErrorASC; /* 06h */2337 U8 ErrorASCQ; /* 07h */2338 U16 SmartCount; /* 08h */2339 U8 SmartASC; /* 0Ah */2340 U8 SmartASCQ; /* 0Bh */2341} RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,2342 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;2343 2344typedef struct _RAID_PHYS_DISK_INQUIRY_DATA2345{2346 U8 VendorID[8]; /* 00h */2347 U8 ProductID[16]; /* 08h */2348 U8 ProductRevLevel[4]; /* 18h */2349 U8 Info[32]; /* 1Ch */2350} RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,2351 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;2352 2353typedef struct _RAID_PHYS_DISK0_SETTINGS2354{2355 U8 SepID; /* 00h */2356 U8 SepBus; /* 01h */2357 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */2358 U8 PhysDiskSettings; /* 03h */2359} RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,2360 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;2361 2362typedef struct _RAID_PHYS_DISK0_STATUS2363{2364 U8 Flags; /* 00h */2365 U8 State; /* 01h */2366 U16 Reserved; /* 02h */2367} RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,2368 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;2369 2370/* RAID Physical Disk PhysDiskStatus flags */2371 2372#define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)2373#define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)2374#define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)2375#define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)2376#define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)2377 2378#define MPI_PHYSDISK0_STATUS_ONLINE (0x00)2379#define MPI_PHYSDISK0_STATUS_MISSING (0x01)2380#define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)2381#define MPI_PHYSDISK0_STATUS_FAILED (0x03)2382#define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)2383#define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)2384#define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)2385#define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)2386 2387typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_02388{2389 CONFIG_PAGE_HEADER Header; /* 00h */2390 U8 PhysDiskID; /* 04h */2391 U8 PhysDiskBus; /* 05h */2392 U8 PhysDiskIOC; /* 06h */2393 U8 PhysDiskNum; /* 07h */2394 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */2395 U32 Reserved1; /* 0Ch */2396 U8 ExtDiskIdentifier[8]; /* 10h */2397 U8 DiskIdentifier[16]; /* 18h */2398 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */2399 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */2400 U32 MaxLBA; /* 68h */2401 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */2402} CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,2403 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;2404 2405#define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)2406 2407 2408typedef struct _RAID_PHYS_DISK1_PATH2409{2410 U8 PhysDiskID; /* 00h */2411 U8 PhysDiskBus; /* 01h */2412 U16 Reserved1; /* 02h */2413 U64 WWID; /* 04h */2414 U64 OwnerWWID; /* 0Ch */2415 U8 OwnerIdentifier; /* 14h */2416 U8 Reserved2; /* 15h */2417 U16 Flags; /* 16h */2418} RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,2419 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;2420 2421/* RAID Physical Disk Page 1 Flags field defines */2422#define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)2423#define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)2424 2425 2426typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_12427{2428 CONFIG_PAGE_HEADER Header; /* 00h */2429 U8 NumPhysDiskPaths; /* 04h */2430 U8 PhysDiskNum; /* 05h */2431 U16 Reserved2; /* 06h */2432 U32 Reserved1; /* 08h */2433 RAID_PHYS_DISK1_PATH Path[] __counted_by(NumPhysDiskPaths);/* 0Ch */2434} CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,2435 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;2436 2437#define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)2438 2439 2440/****************************************************************************2441* LAN Config Pages2442****************************************************************************/2443 2444typedef struct _CONFIG_PAGE_LAN_02445{2446 ConfigPageHeader_t Header; /* 00h */2447 U16 TxRxModes; /* 04h */2448 U16 Reserved; /* 06h */2449 U32 PacketPrePad; /* 08h */2450} CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,2451 LANPage0_t, MPI_POINTER pLANPage0_t;2452 2453#define MPI_LAN_PAGE0_PAGEVERSION (0x01)2454 2455#define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)2456#define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)2457#define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)2458 2459typedef struct _CONFIG_PAGE_LAN_12460{2461 ConfigPageHeader_t Header; /* 00h */2462 U16 Reserved; /* 04h */2463 U8 CurrentDeviceState; /* 06h */2464 U8 Reserved1; /* 07h */2465 U32 MinPacketSize; /* 08h */2466 U32 MaxPacketSize; /* 0Ch */2467 U32 HardwareAddressLow; /* 10h */2468 U32 HardwareAddressHigh; /* 14h */2469 U32 MaxWireSpeedLow; /* 18h */2470 U32 MaxWireSpeedHigh; /* 1Ch */2471 U32 BucketsRemaining; /* 20h */2472 U32 MaxReplySize; /* 24h */2473 U32 NegWireSpeedLow; /* 28h */2474 U32 NegWireSpeedHigh; /* 2Ch */2475} CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,2476 LANPage1_t, MPI_POINTER pLANPage1_t;2477 2478#define MPI_LAN_PAGE1_PAGEVERSION (0x03)2479 2480#define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)2481#define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)2482 2483 2484/****************************************************************************2485* Inband Config Pages2486****************************************************************************/2487 2488typedef struct _CONFIG_PAGE_INBAND_02489{2490 CONFIG_PAGE_HEADER Header; /* 00h */2491 MPI_VERSION_FORMAT InbandVersion; /* 04h */2492 U16 MaximumBuffers; /* 08h */2493 U16 Reserved1; /* 0Ah */2494} CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,2495 InbandPage0_t, MPI_POINTER pInbandPage0_t;2496 2497#define MPI_INBAND_PAGEVERSION (0x00)2498 2499 2500 2501/****************************************************************************2502* SAS IO Unit Config Pages2503****************************************************************************/2504 2505typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA2506{2507 U8 Port; /* 00h */2508 U8 PortFlags; /* 01h */2509 U8 PhyFlags; /* 02h */2510 U8 NegotiatedLinkRate; /* 03h */2511 U32 ControllerPhyDeviceInfo;/* 04h */2512 U16 AttachedDeviceHandle; /* 08h */2513 U16 ControllerDevHandle; /* 0Ah */2514 U32 DiscoveryStatus; /* 0Ch */2515} MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,2516 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;2517 2518typedef struct _CONFIG_PAGE_SAS_IO_UNIT_02519{2520 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2521 U16 NvdataVersionDefault; /* 08h */2522 U16 NvdataVersionPersistent; /* 0Ah */2523 U8 NumPhys; /* 0Ch */2524 U8 Reserved2; /* 0Dh */2525 U16 Reserved3; /* 0Eh */2526 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[] __counted_by(NumPhys); /* 10h */2527} CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,2528 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;2529 2530#define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04)2531 2532/* values for SAS IO Unit Page 0 PortFlags */2533#define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)2534#define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)2535#define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)2536#define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)2537 2538/* values for SAS IO Unit Page 0 PhyFlags */2539#define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)2540#define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)2541#define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)2542 2543/* values for SAS IO Unit Page 0 NegotiatedLinkRate */2544#define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)2545#define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)2546#define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)2547#define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)2548#define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)2549#define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)2550#define MPI_SAS_IOUNIT0_RATE_6_0 (0x0A)2551 2552/* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */2553 2554/* values for SAS IO Unit Page 0 DiscoveryStatus */2555#define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)2556#define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)2557#define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)2558#define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)2559#define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)2560#define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)2561#define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)2562#define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)2563#define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)2564#define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)2565#define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)2566#define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)2567#define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)2568#define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)2569 2570 2571typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA2572{2573 U8 Port; /* 00h */2574 U8 PortFlags; /* 01h */2575 U8 PhyFlags; /* 02h */2576 U8 MaxMinLinkRate; /* 03h */2577 U32 ControllerPhyDeviceInfo; /* 04h */2578 U16 MaxTargetPortConnectTime; /* 08h */2579 U16 Reserved1; /* 0Ah */2580} MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,2581 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;2582 2583/*2584 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to2585 * one and check Header.PageLength at runtime.2586 */2587#ifndef MPI_SAS_IOUNIT1_PHY_MAX2588#define MPI_SAS_IOUNIT1_PHY_MAX (1)2589#endif2590 2591typedef struct _CONFIG_PAGE_SAS_IO_UNIT_12592{2593 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2594 U16 ControlFlags; /* 08h */2595 U16 MaxNumSATATargets; /* 0Ah */2596 U16 AdditionalControlFlags; /* 0Ch */2597 U16 Reserved1; /* 0Eh */2598 U8 NumPhys; /* 10h */2599 U8 SATAMaxQDepth; /* 11h */2600 U8 ReportDeviceMissingDelay; /* 12h */2601 U8 IODeviceMissingDelay; /* 13h */2602 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */2603} CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,2604 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;2605 2606#define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07)2607 2608/* values for SAS IO Unit Page 1 ControlFlags */2609#define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)2610#define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)2611#define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)2612#define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)2613#define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)2614 2615#define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)2616#define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)2617#define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)2618#define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)2619#define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)2620 2621#define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100)2622#define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)2623#define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)2624#define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)2625#define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)2626#define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)2627#define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)2628#define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)2629#define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)2630 2631/* values for SAS IO Unit Page 1 AdditionalControlFlags */2632#define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)2633#define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)2634#define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020)2635#define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)2636#define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)2637#define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)2638#define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)2639#define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)2640 2641/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */2642#define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)2643#define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80)2644 2645/* values for SAS IO Unit Page 1 PortFlags */2646#define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)2647#define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)2648#define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)2649 2650/* values for SAS IO Unit Page 0 PhyFlags */2651#define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)2652#define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)2653#define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)2654 2655/* values for SAS IO Unit Page 0 MaxMinLinkRate */2656#define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)2657#define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)2658#define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)2659#define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)2660#define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)2661#define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)2662 2663/* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */2664 2665 2666typedef struct _CONFIG_PAGE_SAS_IO_UNIT_22667{2668 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2669 U8 NumDevsPerEnclosure; /* 08h */2670 U8 Reserved1; /* 09h */2671 U16 Reserved2; /* 0Ah */2672 U16 MaxPersistentIDs; /* 0Ch */2673 U16 NumPersistentIDsUsed; /* 0Eh */2674 U8 Status; /* 10h */2675 U8 Flags; /* 11h */2676 U16 MaxNumPhysicalMappedIDs;/* 12h */2677} CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,2678 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;2679 2680#define MPI_SASIOUNITPAGE2_PAGEVERSION (0x06)2681 2682/* values for SAS IO Unit Page 2 Status field */2683#define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08)2684#define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04)2685#define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)2686#define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)2687 2688/* values for SAS IO Unit Page 2 Flags field */2689#define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)2690/* Physical Mapping Modes */2691#define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)2692#define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)2693#define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)2694#define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)2695#define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)2696#define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07)2697 2698#define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)2699#define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)2700 2701 2702typedef struct _CONFIG_PAGE_SAS_IO_UNIT_32703{2704 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2705 U32 Reserved1; /* 08h */2706 U32 MaxInvalidDwordCount; /* 0Ch */2707 U32 InvalidDwordCountTime; /* 10h */2708 U32 MaxRunningDisparityErrorCount; /* 14h */2709 U32 RunningDisparityErrorTime; /* 18h */2710 U32 MaxLossDwordSynchCount; /* 1Ch */2711 U32 LossDwordSynchCountTime; /* 20h */2712 U32 MaxPhyResetProblemCount; /* 24h */2713 U32 PhyResetProblemTime; /* 28h */2714} CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,2715 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;2716 2717#define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)2718 2719 2720/****************************************************************************2721* SAS Expander Config Pages2722****************************************************************************/2723 2724typedef struct _CONFIG_PAGE_SAS_EXPANDER_02725{2726 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2727 U8 PhysicalPort; /* 08h */2728 U8 Reserved1; /* 09h */2729 U16 EnclosureHandle; /* 0Ah */2730 U64 SASAddress; /* 0Ch */2731 U32 DiscoveryStatus; /* 14h */2732 U16 DevHandle; /* 18h */2733 U16 ParentDevHandle; /* 1Ah */2734 U16 ExpanderChangeCount; /* 1Ch */2735 U16 ExpanderRouteIndexes; /* 1Eh */2736 U8 NumPhys; /* 20h */2737 U8 SASLevel; /* 21h */2738 U8 Flags; /* 22h */2739 U8 Reserved3; /* 23h */2740} CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,2741 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;2742 2743#define MPI_SASEXPANDER0_PAGEVERSION (0x03)2744 2745/* values for SAS Expander Page 0 DiscoveryStatus field */2746#define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)2747#define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)2748#define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)2749#define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)2750#define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)2751#define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)2752#define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)2753#define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)2754#define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)2755#define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)2756#define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)2757#define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)2758 2759/* values for SAS Expander Page 0 Flags field */2760#define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04)2761#define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)2762#define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)2763 2764 2765typedef struct _CONFIG_PAGE_SAS_EXPANDER_12766{2767 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2768 U8 PhysicalPort; /* 08h */2769 U8 Reserved1; /* 09h */2770 U16 Reserved2; /* 0Ah */2771 U8 NumPhys; /* 0Ch */2772 U8 Phy; /* 0Dh */2773 U16 NumTableEntriesProgrammed; /* 0Eh */2774 U8 ProgrammedLinkRate; /* 10h */2775 U8 HwLinkRate; /* 11h */2776 U16 AttachedDevHandle; /* 12h */2777 U32 PhyInfo; /* 14h */2778 U32 AttachedDeviceInfo; /* 18h */2779 U16 OwnerDevHandle; /* 1Ch */2780 U8 ChangeCount; /* 1Eh */2781 U8 NegotiatedLinkRate; /* 1Fh */2782 U8 PhyIdentifier; /* 20h */2783 U8 AttachedPhyIdentifier; /* 21h */2784 U8 Reserved3; /* 22h */2785 U8 DiscoveryInfo; /* 23h */2786 U32 Reserved4; /* 24h */2787} CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,2788 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;2789 2790#define MPI_SASEXPANDER1_PAGEVERSION (0x01)2791 2792/* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */2793 2794/* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */2795 2796/* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */2797 2798/* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */2799 2800/* values for SAS Expander Page 1 DiscoveryInfo field */2801#define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)2802#define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)2803#define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)2804 2805/* values for SAS Expander Page 1 NegotiatedLinkRate field */2806#define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)2807#define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)2808#define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)2809#define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)2810#define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)2811#define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)2812 2813 2814/****************************************************************************2815* SAS Device Config Pages2816****************************************************************************/2817 2818typedef struct _CONFIG_PAGE_SAS_DEVICE_02819{2820 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2821 U16 Slot; /* 08h */2822 U16 EnclosureHandle; /* 0Ah */2823 U64 SASAddress; /* 0Ch */2824 U16 ParentDevHandle; /* 14h */2825 U8 PhyNum; /* 16h */2826 U8 AccessStatus; /* 17h */2827 U16 DevHandle; /* 18h */2828 U8 TargetID; /* 1Ah */2829 U8 Bus; /* 1Bh */2830 U32 DeviceInfo; /* 1Ch */2831 U16 Flags; /* 20h */2832 U8 PhysicalPort; /* 22h */2833 U8 Reserved2; /* 23h */2834} CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,2835 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;2836 2837#define MPI_SASDEVICE0_PAGEVERSION (0x05)2838 2839/* values for SAS Device Page 0 AccessStatus field */2840#define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)2841#define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)2842#define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)2843#define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)2844#define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)2845/* specific values for SATA Init failures */2846#define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)2847#define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)2848#define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)2849#define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)2850#define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)2851#define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)2852#define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)2853#define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)2854#define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)2855#define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)2856#define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)2857 2858/* values for SAS Device Page 0 Flags field */2859#define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)2860#define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)2861#define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)2862#define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)2863#define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)2864#define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)2865#define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)2866#define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)2867#define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)2868#define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)2869#define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)2870 2871/* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */2872 2873 2874typedef struct _CONFIG_PAGE_SAS_DEVICE_12875{2876 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2877 U32 Reserved1; /* 08h */2878 U64 SASAddress; /* 0Ch */2879 U32 Reserved2; /* 14h */2880 U16 DevHandle; /* 18h */2881 U8 TargetID; /* 1Ah */2882 U8 Bus; /* 1Bh */2883 U8 InitialRegDeviceFIS[20];/* 1Ch */2884} CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,2885 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;2886 2887#define MPI_SASDEVICE1_PAGEVERSION (0x00)2888 2889 2890typedef struct _CONFIG_PAGE_SAS_DEVICE_22891{2892 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2893 U64 PhysicalIdentifier; /* 08h */2894 U32 EnclosureMapping; /* 10h */2895} CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,2896 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;2897 2898#define MPI_SASDEVICE2_PAGEVERSION (0x01)2899 2900/* defines for SAS Device Page 2 EnclosureMapping field */2901#define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)2902#define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)2903#define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)2904#define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)2905#define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)2906#define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)2907 2908 2909/****************************************************************************2910* SAS PHY Config Pages2911****************************************************************************/2912 2913typedef struct _CONFIG_PAGE_SAS_PHY_02914{2915 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2916 U16 OwnerDevHandle; /* 08h */2917 U16 Reserved1; /* 0Ah */2918 U64 SASAddress; /* 0Ch */2919 U16 AttachedDevHandle; /* 14h */2920 U8 AttachedPhyIdentifier; /* 16h */2921 U8 Reserved2; /* 17h */2922 U32 AttachedDeviceInfo; /* 18h */2923 U8 ProgrammedLinkRate; /* 1Ch */2924 U8 HwLinkRate; /* 1Dh */2925 U8 ChangeCount; /* 1Eh */2926 U8 Flags; /* 1Fh */2927 U32 PhyInfo; /* 20h */2928} CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,2929 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;2930 2931#define MPI_SASPHY0_PAGEVERSION (0x01)2932 2933/* values for SAS PHY Page 0 ProgrammedLinkRate field */2934#define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)2935#define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)2936#define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)2937#define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)2938#define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)2939#define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)2940#define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)2941#define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)2942 2943/* values for SAS PHY Page 0 HwLinkRate field */2944#define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)2945#define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)2946#define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)2947#define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)2948#define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)2949#define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)2950 2951/* values for SAS PHY Page 0 Flags field */2952#define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)2953 2954/* values for SAS PHY Page 0 PhyInfo field */2955#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)2956#define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)2957#define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)2958 2959#define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)2960#define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)2961 2962#define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)2963#define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)2964#define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)2965#define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)2966 2967#define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)2968#define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)2969#define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)2970#define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)2971#define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)2972#define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)2973#define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)2974 2975 2976typedef struct _CONFIG_PAGE_SAS_PHY_12977{2978 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2979 U32 Reserved1; /* 08h */2980 U32 InvalidDwordCount; /* 0Ch */2981 U32 RunningDisparityErrorCount; /* 10h */2982 U32 LossDwordSynchCount; /* 14h */2983 U32 PhyResetProblemCount; /* 18h */2984} CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,2985 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;2986 2987#define MPI_SASPHY1_PAGEVERSION (0x00)2988 2989 2990/****************************************************************************2991* SAS Enclosure Config Pages2992****************************************************************************/2993 2994typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_02995{2996 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */2997 U32 Reserved1; /* 08h */2998 U64 EnclosureLogicalID; /* 0Ch */2999 U16 Flags; /* 14h */3000 U16 EnclosureHandle; /* 16h */3001 U16 NumSlots; /* 18h */3002 U16 StartSlot; /* 1Ah */3003 U8 StartTargetID; /* 1Ch */3004 U8 StartBus; /* 1Dh */3005 U8 SEPTargetID; /* 1Eh */3006 U8 SEPBus; /* 1Fh */3007 U32 Reserved2; /* 20h */3008 U32 Reserved3; /* 24h */3009} CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,3010 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;3011 3012#define MPI_SASENCLOSURE0_PAGEVERSION (0x01)3013 3014/* values for SAS Enclosure Page 0 Flags field */3015#define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)3016#define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)3017 3018#define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)3019#define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)3020#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)3021#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)3022#define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)3023#define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)3024#define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)3025 3026 3027/****************************************************************************3028* Log Config Pages3029****************************************************************************/3030/*3031 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to3032 * one and check NumLogEntries at runtime.3033 */3034#ifndef MPI_LOG_0_NUM_LOG_ENTRIES3035#define MPI_LOG_0_NUM_LOG_ENTRIES (1)3036#endif3037 3038#define MPI_LOG_0_LOG_DATA_LENGTH (0x1C)3039 3040typedef struct _MPI_LOG_0_ENTRY3041{3042 U32 TimeStamp; /* 00h */3043 U32 Reserved1; /* 04h */3044 U16 LogSequence; /* 08h */3045 U16 LogEntryQualifier; /* 0Ah */3046 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */3047} MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,3048 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;3049 3050/* values for Log Page 0 LogEntry LogEntryQualifier field */3051#define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)3052#define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)3053 3054typedef struct _CONFIG_PAGE_LOG_03055{3056 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */3057 U32 Reserved1; /* 08h */3058 U32 Reserved2; /* 0Ch */3059 U16 NumLogEntries; /* 10h */3060 U16 Reserved3; /* 12h */3061 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */3062} CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,3063 LogPage0_t, MPI_POINTER pLogPage0_t;3064 3065#define MPI_LOG_0_PAGEVERSION (0x01)3066 3067 3068#endif3069 3070