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1// SPDX-License-Identifier: GPL-2.02/*3 * MFD core driver for Intel Broxton Whiskey Cove PMIC4 *5 * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.6 */7 8#include <linux/acpi.h>9#include <linux/bits.h>10#include <linux/delay.h>11#include <linux/err.h>12#include <linux/interrupt.h>13#include <linux/kernel.h>14#include <linux/mfd/core.h>15#include <linux/mfd/intel_soc_pmic.h>16#include <linux/mfd/intel_soc_pmic_bxtwc.h>17#include <linux/module.h>18#include <linux/platform_data/x86/intel_scu_ipc.h>19 20/* PMIC device registers */21#define REG_ADDR_MASK GENMASK(15, 8)22#define REG_ADDR_SHIFT 823#define REG_OFFSET_MASK GENMASK(7, 0)24 25/* Interrupt Status Registers */26#define BXTWC_IRQLVL1 0x4E0227 28#define BXTWC_PWRBTNIRQ 0x4E0329#define BXTWC_THRM0IRQ 0x4E0430#define BXTWC_THRM1IRQ 0x4E0531#define BXTWC_THRM2IRQ 0x4E0632#define BXTWC_BCUIRQ 0x4E0733#define BXTWC_ADCIRQ 0x4E0834#define BXTWC_CHGR0IRQ 0x4E0935#define BXTWC_CHGR1IRQ 0x4E0A36#define BXTWC_GPIOIRQ0 0x4E0B37#define BXTWC_GPIOIRQ1 0x4E0C38#define BXTWC_CRITIRQ 0x4E0D39#define BXTWC_TMUIRQ 0x4FB640 41/* Interrupt MASK Registers */42#define BXTWC_MIRQLVL1 0x4E0E43#define BXTWC_MIRQLVL1_MCHGR BIT(5)44 45#define BXTWC_MPWRBTNIRQ 0x4E0F46#define BXTWC_MTHRM0IRQ 0x4E1247#define BXTWC_MTHRM1IRQ 0x4E1348#define BXTWC_MTHRM2IRQ 0x4E1449#define BXTWC_MBCUIRQ 0x4E1550#define BXTWC_MADCIRQ 0x4E1651#define BXTWC_MCHGR0IRQ 0x4E1752#define BXTWC_MCHGR1IRQ 0x4E1853#define BXTWC_MGPIO0IRQ 0x4E1954#define BXTWC_MGPIO1IRQ 0x4E1A55#define BXTWC_MCRITIRQ 0x4E1B56#define BXTWC_MTMUIRQ 0x4FB757 58/* Whiskey Cove PMIC share same ACPI ID between different platforms */59#define BROXTON_PMIC_WC_HRV 460 61#define PMC_PMIC_ACCESS 0xFF62#define PMC_PMIC_READ 0x063#define PMC_PMIC_WRITE 0x164 65enum bxtwc_irqs {66 BXTWC_PWRBTN_LVL1_IRQ = 0,67 BXTWC_TMU_LVL1_IRQ,68 BXTWC_THRM_LVL1_IRQ,69 BXTWC_BCU_LVL1_IRQ,70 BXTWC_ADC_LVL1_IRQ,71 BXTWC_CHGR_LVL1_IRQ,72 BXTWC_GPIO_LVL1_IRQ,73 BXTWC_CRIT_LVL1_IRQ,74};75 76enum bxtwc_irqs_pwrbtn {77 BXTWC_PWRBTN_IRQ = 0,78 BXTWC_UIBTN_IRQ,79};80 81enum bxtwc_irqs_bcu {82 BXTWC_BCU_IRQ = 0,83};84 85enum bxtwc_irqs_adc {86 BXTWC_ADC_IRQ = 0,87};88 89enum bxtwc_irqs_chgr {90 BXTWC_USBC_IRQ = 0,91 BXTWC_CHGR0_IRQ,92 BXTWC_CHGR1_IRQ,93};94 95enum bxtwc_irqs_tmu {96 BXTWC_TMU_IRQ = 0,97};98 99enum bxtwc_irqs_crit {100 BXTWC_CRIT_IRQ = 0,101};102 103static const struct regmap_irq bxtwc_regmap_irqs[] = {104 REGMAP_IRQ_REG(BXTWC_PWRBTN_LVL1_IRQ, 0, BIT(0)),105 REGMAP_IRQ_REG(BXTWC_TMU_LVL1_IRQ, 0, BIT(1)),106 REGMAP_IRQ_REG(BXTWC_THRM_LVL1_IRQ, 0, BIT(2)),107 REGMAP_IRQ_REG(BXTWC_BCU_LVL1_IRQ, 0, BIT(3)),108 REGMAP_IRQ_REG(BXTWC_ADC_LVL1_IRQ, 0, BIT(4)),109 REGMAP_IRQ_REG(BXTWC_CHGR_LVL1_IRQ, 0, BIT(5)),110 REGMAP_IRQ_REG(BXTWC_GPIO_LVL1_IRQ, 0, BIT(6)),111 REGMAP_IRQ_REG(BXTWC_CRIT_LVL1_IRQ, 0, BIT(7)),112};113 114static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {115 REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)),116};117 118static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {119 REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),120};121 122static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {123 REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),124};125 126static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {127 REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),128 REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),129 REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),130};131 132static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {133 REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),134};135 136static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {137 REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),138};139 140static const struct regmap_irq_chip bxtwc_regmap_irq_chip = {141 .name = "bxtwc_irq_chip",142 .status_base = BXTWC_IRQLVL1,143 .mask_base = BXTWC_MIRQLVL1,144 .irqs = bxtwc_regmap_irqs,145 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs),146 .num_regs = 1,147};148 149static const struct regmap_irq_chip bxtwc_regmap_irq_chip_pwrbtn = {150 .name = "bxtwc_irq_chip_pwrbtn",151 .status_base = BXTWC_PWRBTNIRQ,152 .mask_base = BXTWC_MPWRBTNIRQ,153 .irqs = bxtwc_regmap_irqs_pwrbtn,154 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_pwrbtn),155 .num_regs = 1,156};157 158static const struct regmap_irq_chip bxtwc_regmap_irq_chip_tmu = {159 .name = "bxtwc_irq_chip_tmu",160 .status_base = BXTWC_TMUIRQ,161 .mask_base = BXTWC_MTMUIRQ,162 .irqs = bxtwc_regmap_irqs_tmu,163 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_tmu),164 .num_regs = 1,165};166 167static const struct regmap_irq_chip bxtwc_regmap_irq_chip_bcu = {168 .name = "bxtwc_irq_chip_bcu",169 .status_base = BXTWC_BCUIRQ,170 .mask_base = BXTWC_MBCUIRQ,171 .irqs = bxtwc_regmap_irqs_bcu,172 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_bcu),173 .num_regs = 1,174};175 176static const struct regmap_irq_chip bxtwc_regmap_irq_chip_adc = {177 .name = "bxtwc_irq_chip_adc",178 .status_base = BXTWC_ADCIRQ,179 .mask_base = BXTWC_MADCIRQ,180 .irqs = bxtwc_regmap_irqs_adc,181 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_adc),182 .num_regs = 1,183};184 185static const struct regmap_irq_chip bxtwc_regmap_irq_chip_chgr = {186 .name = "bxtwc_irq_chip_chgr",187 .status_base = BXTWC_CHGR0IRQ,188 .mask_base = BXTWC_MCHGR0IRQ,189 .irqs = bxtwc_regmap_irqs_chgr,190 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_chgr),191 .num_regs = 2,192};193 194static const struct regmap_irq_chip bxtwc_regmap_irq_chip_crit = {195 .name = "bxtwc_irq_chip_crit",196 .status_base = BXTWC_CRITIRQ,197 .mask_base = BXTWC_MCRITIRQ,198 .irqs = bxtwc_regmap_irqs_crit,199 .num_irqs = ARRAY_SIZE(bxtwc_regmap_irqs_crit),200 .num_regs = 1,201};202 203static const struct resource gpio_resources[] = {204 DEFINE_RES_IRQ_NAMED(BXTWC_GPIO_LVL1_IRQ, "GPIO"),205};206 207static const struct resource adc_resources[] = {208 DEFINE_RES_IRQ_NAMED(BXTWC_ADC_IRQ, "ADC"),209};210 211static const struct resource usbc_resources[] = {212 DEFINE_RES_IRQ(BXTWC_USBC_IRQ),213};214 215static const struct resource charger_resources[] = {216 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR0_IRQ, "CHARGER"),217 DEFINE_RES_IRQ_NAMED(BXTWC_CHGR1_IRQ, "CHARGER1"),218};219 220static const struct resource thermal_resources[] = {221 DEFINE_RES_IRQ(BXTWC_THRM_LVL1_IRQ),222};223 224static const struct resource bcu_resources[] = {225 DEFINE_RES_IRQ_NAMED(BXTWC_BCU_IRQ, "BCU"),226};227 228static const struct resource tmu_resources[] = {229 DEFINE_RES_IRQ_NAMED(BXTWC_TMU_IRQ, "TMU"),230};231 232static struct mfd_cell bxt_wc_dev[] = {233 {234 .name = "bxt_wcove_gpadc",235 .num_resources = ARRAY_SIZE(adc_resources),236 .resources = adc_resources,237 },238 {239 .name = "bxt_wcove_thermal",240 .num_resources = ARRAY_SIZE(thermal_resources),241 .resources = thermal_resources,242 },243 {244 .name = "bxt_wcove_usbc",245 .num_resources = ARRAY_SIZE(usbc_resources),246 .resources = usbc_resources,247 },248 {249 .name = "bxt_wcove_ext_charger",250 .num_resources = ARRAY_SIZE(charger_resources),251 .resources = charger_resources,252 },253 {254 .name = "bxt_wcove_bcu",255 .num_resources = ARRAY_SIZE(bcu_resources),256 .resources = bcu_resources,257 },258 {259 .name = "bxt_wcove_tmu",260 .num_resources = ARRAY_SIZE(tmu_resources),261 .resources = tmu_resources,262 },263 264 {265 .name = "bxt_wcove_gpio",266 .num_resources = ARRAY_SIZE(gpio_resources),267 .resources = gpio_resources,268 },269 {270 .name = "bxt_wcove_region",271 },272};273 274static int regmap_ipc_byte_reg_read(void *context, unsigned int reg,275 unsigned int *val)276{277 int ret;278 int i2c_addr;279 u8 ipc_in[2];280 u8 ipc_out[4];281 struct intel_soc_pmic *pmic = context;282 283 if (!pmic)284 return -EINVAL;285 286 if (reg & REG_ADDR_MASK)287 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;288 else289 i2c_addr = BXTWC_DEVICE1_ADDR;290 291 reg &= REG_OFFSET_MASK;292 293 ipc_in[0] = reg;294 ipc_in[1] = i2c_addr;295 ret = intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,296 PMC_PMIC_READ, ipc_in, sizeof(ipc_in),297 ipc_out, sizeof(ipc_out));298 if (ret)299 return ret;300 301 *val = ipc_out[0];302 303 return 0;304}305 306static int regmap_ipc_byte_reg_write(void *context, unsigned int reg,307 unsigned int val)308{309 int i2c_addr;310 u8 ipc_in[3];311 struct intel_soc_pmic *pmic = context;312 313 if (!pmic)314 return -EINVAL;315 316 if (reg & REG_ADDR_MASK)317 i2c_addr = (reg & REG_ADDR_MASK) >> REG_ADDR_SHIFT;318 else319 i2c_addr = BXTWC_DEVICE1_ADDR;320 321 reg &= REG_OFFSET_MASK;322 323 ipc_in[0] = reg;324 ipc_in[1] = i2c_addr;325 ipc_in[2] = val;326 return intel_scu_ipc_dev_command(pmic->scu, PMC_PMIC_ACCESS,327 PMC_PMIC_WRITE, ipc_in, sizeof(ipc_in),328 NULL, 0);329}330 331/* sysfs interfaces to r/w PMIC registers, required by initial script */332static unsigned long bxtwc_reg_addr;333static ssize_t addr_show(struct device *dev,334 struct device_attribute *attr, char *buf)335{336 return sysfs_emit(buf, "0x%lx\n", bxtwc_reg_addr);337}338 339static ssize_t addr_store(struct device *dev,340 struct device_attribute *attr, const char *buf, size_t count)341{342 int ret;343 344 ret = kstrtoul(buf, 0, &bxtwc_reg_addr);345 if (ret)346 return ret;347 348 return count;349}350 351static ssize_t val_show(struct device *dev,352 struct device_attribute *attr, char *buf)353{354 int ret;355 unsigned int val;356 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);357 358 ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);359 if (ret) {360 dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);361 return ret;362 }363 364 return sysfs_emit(buf, "0x%02x\n", val);365}366 367static ssize_t val_store(struct device *dev,368 struct device_attribute *attr, const char *buf, size_t count)369{370 int ret;371 unsigned int val;372 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);373 374 ret = kstrtouint(buf, 0, &val);375 if (ret)376 return ret;377 378 ret = regmap_write(pmic->regmap, bxtwc_reg_addr, val);379 if (ret) {380 dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",381 val, bxtwc_reg_addr);382 return ret;383 }384 return count;385}386 387static DEVICE_ATTR_ADMIN_RW(addr);388static DEVICE_ATTR_ADMIN_RW(val);389static struct attribute *bxtwc_attrs[] = {390 &dev_attr_addr.attr,391 &dev_attr_val.attr,392 NULL393};394 395static const struct attribute_group bxtwc_group = {396 .attrs = bxtwc_attrs,397};398 399static const struct attribute_group *bxtwc_groups[] = {400 &bxtwc_group,401 NULL402};403 404static const struct regmap_config bxtwc_regmap_config = {405 .reg_bits = 16,406 .val_bits = 8,407 .reg_write = regmap_ipc_byte_reg_write,408 .reg_read = regmap_ipc_byte_reg_read,409};410 411static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,412 struct regmap_irq_chip_data *pdata,413 int pirq, int irq_flags,414 const struct regmap_irq_chip *chip,415 struct regmap_irq_chip_data **data)416{417 int irq;418 419 irq = regmap_irq_get_virq(pdata, pirq);420 if (irq < 0)421 return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",422 pirq, chip->name);423 424 return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,425 0, chip, data);426}427 428static int bxtwc_probe(struct platform_device *pdev)429{430 struct device *dev = &pdev->dev;431 int ret;432 acpi_status status;433 unsigned long long hrv;434 struct intel_soc_pmic *pmic;435 436 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);437 if (ACPI_FAILURE(status))438 return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");439 if (hrv != BROXTON_PMIC_WC_HRV)440 return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);441 442 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);443 if (!pmic)444 return -ENOMEM;445 446 ret = platform_get_irq(pdev, 0);447 if (ret < 0)448 return ret;449 pmic->irq = ret;450 451 platform_set_drvdata(pdev, pmic);452 pmic->dev = dev;453 454 pmic->scu = devm_intel_scu_ipc_dev_get(dev);455 if (!pmic->scu)456 return -EPROBE_DEFER;457 458 pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config);459 if (IS_ERR(pmic->regmap))460 return dev_err_probe(dev, PTR_ERR(pmic->regmap), "Failed to initialise regmap\n");461 462 ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,463 IRQF_ONESHOT | IRQF_SHARED,464 0, &bxtwc_regmap_irq_chip,465 &pmic->irq_chip_data);466 if (ret)467 return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");468 469 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,470 BXTWC_PWRBTN_LVL1_IRQ,471 IRQF_ONESHOT,472 &bxtwc_regmap_irq_chip_pwrbtn,473 &pmic->irq_chip_data_pwrbtn);474 if (ret)475 return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");476 477 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,478 BXTWC_TMU_LVL1_IRQ,479 IRQF_ONESHOT,480 &bxtwc_regmap_irq_chip_tmu,481 &pmic->irq_chip_data_tmu);482 if (ret)483 return dev_err_probe(dev, ret, "Failed to add TMU IRQ chip\n");484 485 /* Add chained IRQ handler for BCU IRQs */486 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,487 BXTWC_BCU_LVL1_IRQ,488 IRQF_ONESHOT,489 &bxtwc_regmap_irq_chip_bcu,490 &pmic->irq_chip_data_bcu);491 if (ret)492 return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n");493 494 /* Add chained IRQ handler for ADC IRQs */495 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,496 BXTWC_ADC_LVL1_IRQ,497 IRQF_ONESHOT,498 &bxtwc_regmap_irq_chip_adc,499 &pmic->irq_chip_data_adc);500 if (ret)501 return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n");502 503 /* Add chained IRQ handler for CHGR IRQs */504 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,505 BXTWC_CHGR_LVL1_IRQ,506 IRQF_ONESHOT,507 &bxtwc_regmap_irq_chip_chgr,508 &pmic->irq_chip_data_chgr);509 if (ret)510 return dev_err_probe(dev, ret, "Failed to add CHGR IRQ chip\n");511 512 /* Add chained IRQ handler for CRIT IRQs */513 ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,514 BXTWC_CRIT_LVL1_IRQ,515 IRQF_ONESHOT,516 &bxtwc_regmap_irq_chip_crit,517 &pmic->irq_chip_data_crit);518 if (ret)519 return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");520 521 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),522 NULL, 0, NULL);523 if (ret)524 return dev_err_probe(dev, ret, "Failed to add devices\n");525 526 /*527 * There is a known H/W bug. Upon reset, BIT 5 of register528 * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,529 * later it's set to 1(masked) automatically by hardware. So we530 * place the software workaround here to unmask it again in order531 * to re-enable the charger interrupt.532 */533 regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, 0);534 535 return 0;536}537 538static void bxtwc_shutdown(struct platform_device *pdev)539{540 struct intel_soc_pmic *pmic = platform_get_drvdata(pdev);541 542 disable_irq(pmic->irq);543}544 545static int bxtwc_suspend(struct device *dev)546{547 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);548 549 disable_irq(pmic->irq);550 551 return 0;552}553 554static int bxtwc_resume(struct device *dev)555{556 struct intel_soc_pmic *pmic = dev_get_drvdata(dev);557 558 enable_irq(pmic->irq);559 return 0;560}561 562static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);563 564static const struct acpi_device_id bxtwc_acpi_ids[] = {565 { "INT34D3", },566 { }567};568MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);569 570static struct platform_driver bxtwc_driver = {571 .probe = bxtwc_probe,572 .shutdown = bxtwc_shutdown,573 .driver = {574 .name = "BXTWC PMIC",575 .pm = pm_sleep_ptr(&bxtwc_pm_ops),576 .acpi_match_table = bxtwc_acpi_ids,577 .dev_groups = bxtwc_groups,578 },579};580 581module_platform_driver(bxtwc_driver);582 583MODULE_DESCRIPTION("Intel Broxton Whiskey Cove PMIC MFD core driver");584MODULE_LICENSE("GPL v2");585MODULE_AUTHOR("Qipeng Zha <qipeng.zha@intel.com>");586