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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Maxim MAX77620 MFD Driver4 *5 * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.6 *7 * Author:8 * Laxman Dewangan <ldewangan@nvidia.com>9 * Chaitanya Bandi <bandik@nvidia.com>10 * Mallikarjun Kasoju <mkasoju@nvidia.com>11 */12 13/****************** Teminology used in driver ********************14 * Here are some terminology used from datasheet for quick reference:15 * Flexible Power Sequence (FPS):16 * The Flexible Power Sequencer (FPS) allows each regulator to power up under17 * hardware or software control. Additionally, each regulator can power on18 * independently or among a group of other regulators with an adjustable19 * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can20 * be programmed to be part of a sequence allowing external regulators to be21 * sequenced along with internal regulators. 32KHz clock can be programmed to22 * be part of a sequence.23 * There is 3 FPS confguration registers and all resources are configured to24 * any of these FPS or no FPS.25 */26 27#include <linux/i2c.h>28#include <linux/interrupt.h>29#include <linux/mfd/core.h>30#include <linux/mfd/max77620.h>31#include <linux/init.h>32#include <linux/of.h>33#include <linux/regmap.h>34#include <linux/slab.h>35 36static struct max77620_chip *max77620_scratch;37 38static const struct resource gpio_resources[] = {39 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),40};41 42static const struct resource power_resources[] = {43 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),44};45 46static const struct resource rtc_resources[] = {47 DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),48};49 50static const struct resource thermal_resources[] = {51 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),52 DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),53};54 55static const struct regmap_irq max77620_top_irqs[] = {56 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),57 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),58 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),59 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),60 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),61 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),62 REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),63 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),64 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),65 REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),66};67 68static const struct mfd_cell max77620_children[] = {69 { .name = "max77620-pinctrl", },70 { .name = "max77620-clock", },71 { .name = "max77620-pmic", },72 { .name = "max77620-watchdog", },73 {74 .name = "max77620-gpio",75 .resources = gpio_resources,76 .num_resources = ARRAY_SIZE(gpio_resources),77 }, {78 .name = "max77620-rtc",79 .resources = rtc_resources,80 .num_resources = ARRAY_SIZE(rtc_resources),81 }, {82 .name = "max77620-power",83 .resources = power_resources,84 .num_resources = ARRAY_SIZE(power_resources),85 }, {86 .name = "max77620-thermal",87 .resources = thermal_resources,88 .num_resources = ARRAY_SIZE(thermal_resources),89 },90};91 92static const struct mfd_cell max20024_children[] = {93 { .name = "max20024-pinctrl", },94 { .name = "max77620-clock", },95 { .name = "max20024-pmic", },96 { .name = "max77620-watchdog", },97 {98 .name = "max77620-gpio",99 .resources = gpio_resources,100 .num_resources = ARRAY_SIZE(gpio_resources),101 }, {102 .name = "max77620-rtc",103 .resources = rtc_resources,104 .num_resources = ARRAY_SIZE(rtc_resources),105 }, {106 .name = "max20024-power",107 .resources = power_resources,108 .num_resources = ARRAY_SIZE(power_resources),109 },110};111 112static const struct mfd_cell max77663_children[] = {113 { .name = "max77620-pinctrl", },114 { .name = "max77620-clock", },115 { .name = "max77663-pmic", },116 { .name = "max77620-watchdog", },117 {118 .name = "max77620-gpio",119 .resources = gpio_resources,120 .num_resources = ARRAY_SIZE(gpio_resources),121 }, {122 .name = "max77620-rtc",123 .resources = rtc_resources,124 .num_resources = ARRAY_SIZE(rtc_resources),125 }, {126 .name = "max77663-power",127 .resources = power_resources,128 .num_resources = ARRAY_SIZE(power_resources),129 },130};131 132static const struct regmap_range max77620_readable_ranges[] = {133 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),134};135 136static const struct regmap_access_table max77620_readable_table = {137 .yes_ranges = max77620_readable_ranges,138 .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),139};140 141static const struct regmap_range max20024_readable_ranges[] = {142 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),143 regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),144};145 146static const struct regmap_access_table max20024_readable_table = {147 .yes_ranges = max20024_readable_ranges,148 .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),149};150 151static const struct regmap_range max77620_writable_ranges[] = {152 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),153};154 155static const struct regmap_access_table max77620_writable_table = {156 .yes_ranges = max77620_writable_ranges,157 .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),158};159 160static const struct regmap_range max77620_cacheable_ranges[] = {161 regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),162 regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),163};164 165static const struct regmap_access_table max77620_volatile_table = {166 .no_ranges = max77620_cacheable_ranges,167 .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),168};169 170static const struct regmap_config max77620_regmap_config = {171 .name = "power-slave",172 .reg_bits = 8,173 .val_bits = 8,174 .max_register = MAX77620_REG_DVSSD4 + 1,175 .cache_type = REGCACHE_MAPLE,176 .rd_table = &max77620_readable_table,177 .wr_table = &max77620_writable_table,178 .volatile_table = &max77620_volatile_table,179 .use_single_write = true,180};181 182static const struct regmap_config max20024_regmap_config = {183 .name = "power-slave",184 .reg_bits = 8,185 .val_bits = 8,186 .max_register = MAX20024_REG_MAX_ADD + 1,187 .cache_type = REGCACHE_MAPLE,188 .rd_table = &max20024_readable_table,189 .wr_table = &max77620_writable_table,190 .volatile_table = &max77620_volatile_table,191};192 193static const struct regmap_range max77663_readable_ranges[] = {194 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),195};196 197static const struct regmap_access_table max77663_readable_table = {198 .yes_ranges = max77663_readable_ranges,199 .n_yes_ranges = ARRAY_SIZE(max77663_readable_ranges),200};201 202static const struct regmap_range max77663_writable_ranges[] = {203 regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_CID5),204};205 206static const struct regmap_access_table max77663_writable_table = {207 .yes_ranges = max77663_writable_ranges,208 .n_yes_ranges = ARRAY_SIZE(max77663_writable_ranges),209};210 211static const struct regmap_config max77663_regmap_config = {212 .name = "power-slave",213 .reg_bits = 8,214 .val_bits = 8,215 .max_register = MAX77620_REG_CID5 + 1,216 .cache_type = REGCACHE_MAPLE,217 .rd_table = &max77663_readable_table,218 .wr_table = &max77663_writable_table,219 .volatile_table = &max77620_volatile_table,220};221 222/*223 * MAX77620 and MAX20024 has the following steps of the interrupt handling224 * for TOP interrupts:225 * 1. When interrupt occurs from PMIC, mask the PMIC interrupt by setting GLBLM.226 * 2. Read IRQTOP and service the interrupt.227 * 3. Once all interrupts has been checked and serviced, the interrupt service228 * routine un-masks the hardware interrupt line by clearing GLBLM.229 */230static int max77620_irq_global_mask(void *irq_drv_data)231{232 struct max77620_chip *chip = irq_drv_data;233 int ret;234 235 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,236 MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK);237 if (ret < 0)238 dev_err(chip->dev, "Failed to set GLBLM: %d\n", ret);239 240 return ret;241}242 243static int max77620_irq_global_unmask(void *irq_drv_data)244{245 struct max77620_chip *chip = irq_drv_data;246 int ret;247 248 ret = regmap_update_bits(chip->rmap, MAX77620_REG_INTENLBT,249 MAX77620_GLBLM_MASK, 0);250 if (ret < 0)251 dev_err(chip->dev, "Failed to reset GLBLM: %d\n", ret);252 253 return ret;254}255 256static struct regmap_irq_chip max77620_top_irq_chip = {257 .name = "max77620-top",258 .irqs = max77620_top_irqs,259 .num_irqs = ARRAY_SIZE(max77620_top_irqs),260 .num_regs = 2,261 .status_base = MAX77620_REG_IRQTOP,262 .mask_base = MAX77620_REG_IRQTOPM,263 .handle_pre_irq = max77620_irq_global_mask,264 .handle_post_irq = max77620_irq_global_unmask,265};266 267/* max77620_get_fps_period_reg_value: Get FPS bit field value from268 * requested periods.269 * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560270 * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,271 * 160, 320, 540, 1280 and 2560 microseconds.272 * The FPS register has 3 bits field to set the FPS period as273 * bits max77620 max20024274 * 000 40 20275 * 001 80 40276 * :::277*/278static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,279 int tperiod)280{281 int fps_min_period;282 int i;283 284 switch (chip->chip_id) {285 case MAX20024:286 fps_min_period = MAX20024_FPS_PERIOD_MIN_US;287 break;288 case MAX77620:289 fps_min_period = MAX77620_FPS_PERIOD_MIN_US;290 break;291 case MAX77663:292 fps_min_period = MAX20024_FPS_PERIOD_MIN_US;293 break;294 default:295 return -EINVAL;296 }297 298 for (i = 0; i < 7; i++) {299 if (fps_min_period >= tperiod)300 return i;301 fps_min_period *= 2;302 }303 304 return i;305}306 307/* max77620_config_fps: Configure FPS configuration registers308 * based on platform specific information.309 */310static int max77620_config_fps(struct max77620_chip *chip,311 struct device_node *fps_np)312{313 struct device *dev = chip->dev;314 unsigned int mask = 0, config = 0;315 u32 fps_max_period;316 u32 param_val;317 int tperiod, fps_id;318 int ret;319 char fps_name[10];320 321 switch (chip->chip_id) {322 case MAX20024:323 fps_max_period = MAX20024_FPS_PERIOD_MAX_US;324 break;325 case MAX77620:326 fps_max_period = MAX77620_FPS_PERIOD_MAX_US;327 break;328 case MAX77663:329 fps_max_period = MAX20024_FPS_PERIOD_MAX_US;330 break;331 default:332 return -EINVAL;333 }334 335 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {336 sprintf(fps_name, "fps%d", fps_id);337 if (of_node_name_eq(fps_np, fps_name))338 break;339 }340 341 if (fps_id == MAX77620_FPS_COUNT) {342 dev_err(dev, "FPS node name %pOFn is not valid\n", fps_np);343 return -EINVAL;344 }345 346 ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",347 ¶m_val);348 if (!ret) {349 mask |= MAX77620_FPS_TIME_PERIOD_MASK;350 chip->shutdown_fps_period[fps_id] = min(param_val,351 fps_max_period);352 tperiod = max77620_get_fps_period_reg_value(chip,353 chip->shutdown_fps_period[fps_id]);354 config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;355 }356 357 ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",358 ¶m_val);359 if (!ret)360 chip->suspend_fps_period[fps_id] = min(param_val,361 fps_max_period);362 363 ret = of_property_read_u32(fps_np, "maxim,fps-event-source",364 ¶m_val);365 if (!ret) {366 if (param_val > 2) {367 dev_err(dev, "FPS%d event-source invalid\n", fps_id);368 return -EINVAL;369 }370 mask |= MAX77620_FPS_EN_SRC_MASK;371 config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;372 if (param_val == 2) {373 mask |= MAX77620_FPS_ENFPS_SW_MASK;374 config |= MAX77620_FPS_ENFPS_SW;375 }376 }377 378 if (!chip->sleep_enable && !chip->enable_global_lpm) {379 ret = of_property_read_u32(fps_np,380 "maxim,device-state-on-disabled-event",381 ¶m_val);382 if (!ret) {383 if (param_val == 0)384 chip->sleep_enable = true;385 else if (param_val == 1)386 chip->enable_global_lpm = true;387 }388 }389 390 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,391 mask, config);392 if (ret < 0) {393 dev_err(dev, "Failed to update FPS CFG: %d\n", ret);394 return ret;395 }396 397 return 0;398}399 400static int max77620_initialise_fps(struct max77620_chip *chip)401{402 struct device *dev = chip->dev;403 struct device_node *fps_np;404 u8 config;405 int fps_id;406 int ret;407 408 for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {409 chip->shutdown_fps_period[fps_id] = -1;410 chip->suspend_fps_period[fps_id] = -1;411 }412 413 fps_np = of_get_child_by_name(dev->of_node, "fps");414 if (!fps_np)415 goto skip_fps;416 417 for_each_child_of_node_scoped(fps_np, fps_child) {418 ret = max77620_config_fps(chip, fps_child);419 if (ret < 0) {420 of_node_put(fps_np);421 return ret;422 }423 }424 of_node_put(fps_np);425 426 config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;427 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,428 MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);429 if (ret < 0) {430 dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);431 return ret;432 }433 434skip_fps:435 if (chip->chip_id == MAX77663)436 return 0;437 438 /* Enable wake on EN0 pin */439 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,440 MAX77620_ONOFFCNFG2_WK_EN0,441 MAX77620_ONOFFCNFG2_WK_EN0);442 if (ret < 0) {443 dev_err(dev, "Failed to update WK_EN0: %d\n", ret);444 return ret;445 }446 447 /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */448 if ((chip->chip_id == MAX20024) && chip->sleep_enable) {449 config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;450 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,451 config, config);452 if (ret < 0) {453 dev_err(dev, "Failed to update SLPEN: %d\n", ret);454 return ret;455 }456 }457 458 return 0;459}460 461static int max77620_read_es_version(struct max77620_chip *chip)462{463 unsigned int val;464 u8 cid_val[6];465 int i;466 int ret;467 468 for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {469 ret = regmap_read(chip->rmap, i, &val);470 if (ret < 0) {471 dev_err(chip->dev, "Failed to read CID: %d\n", ret);472 return ret;473 }474 dev_dbg(chip->dev, "CID%d: 0x%02x\n",475 i - MAX77620_REG_CID0, val);476 cid_val[i - MAX77620_REG_CID0] = val;477 }478 479 /* CID4 is OTP Version and CID5 is ES version */480 dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",481 cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));482 483 return ret;484}485 486static void max77620_pm_power_off(void)487{488 struct max77620_chip *chip = max77620_scratch;489 490 regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,491 MAX77620_ONOFFCNFG1_SFT_RST,492 MAX77620_ONOFFCNFG1_SFT_RST);493}494 495static int max77620_probe(struct i2c_client *client)496{497 const struct i2c_device_id *id = i2c_client_get_device_id(client);498 const struct regmap_config *rmap_config;499 struct max77620_chip *chip;500 const struct mfd_cell *mfd_cells;501 int n_mfd_cells;502 bool pm_off;503 int ret;504 505 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);506 if (!chip)507 return -ENOMEM;508 509 i2c_set_clientdata(client, chip);510 chip->dev = &client->dev;511 chip->chip_irq = client->irq;512 chip->chip_id = (enum max77620_chip_id)id->driver_data;513 514 switch (chip->chip_id) {515 case MAX77620:516 mfd_cells = max77620_children;517 n_mfd_cells = ARRAY_SIZE(max77620_children);518 rmap_config = &max77620_regmap_config;519 break;520 case MAX20024:521 mfd_cells = max20024_children;522 n_mfd_cells = ARRAY_SIZE(max20024_children);523 rmap_config = &max20024_regmap_config;524 break;525 case MAX77663:526 mfd_cells = max77663_children;527 n_mfd_cells = ARRAY_SIZE(max77663_children);528 rmap_config = &max77663_regmap_config;529 break;530 default:531 dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);532 return -EINVAL;533 }534 535 chip->rmap = devm_regmap_init_i2c(client, rmap_config);536 if (IS_ERR(chip->rmap)) {537 ret = PTR_ERR(chip->rmap);538 dev_err(chip->dev, "Failed to initialise regmap: %d\n", ret);539 return ret;540 }541 542 ret = max77620_read_es_version(chip);543 if (ret < 0)544 return ret;545 546 max77620_top_irq_chip.irq_drv_data = chip;547 ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,548 IRQF_ONESHOT | IRQF_SHARED, 0,549 &max77620_top_irq_chip,550 &chip->top_irq_data);551 if (ret < 0) {552 dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);553 return ret;554 }555 556 ret = max77620_initialise_fps(chip);557 if (ret < 0)558 return ret;559 560 ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,561 mfd_cells, n_mfd_cells, NULL, 0,562 regmap_irq_get_domain(chip->top_irq_data));563 if (ret < 0) {564 dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);565 return ret;566 }567 568 pm_off = of_device_is_system_power_controller(client->dev.of_node);569 if (pm_off && !pm_power_off) {570 max77620_scratch = chip;571 pm_power_off = max77620_pm_power_off;572 }573 574 return 0;575}576 577static int max77620_set_fps_period(struct max77620_chip *chip,578 int fps_id, int time_period)579{580 int period = max77620_get_fps_period_reg_value(chip, time_period);581 int ret;582 583 ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,584 MAX77620_FPS_TIME_PERIOD_MASK,585 period << MAX77620_FPS_TIME_PERIOD_SHIFT);586 if (ret < 0) {587 dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);588 return ret;589 }590 591 return 0;592}593 594static int max77620_i2c_suspend(struct device *dev)595{596 struct max77620_chip *chip = dev_get_drvdata(dev);597 struct i2c_client *client = to_i2c_client(dev);598 unsigned int config;599 int fps;600 int ret;601 602 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {603 if (chip->suspend_fps_period[fps] < 0)604 continue;605 606 ret = max77620_set_fps_period(chip, fps,607 chip->suspend_fps_period[fps]);608 if (ret < 0)609 return ret;610 }611 612 /*613 * For MAX20024: No need to configure SLPEN on suspend as614 * it will be configured on Init.615 */616 if (chip->chip_id == MAX20024)617 goto out;618 619 config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;620 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,621 MAX77620_ONOFFCNFG1_SLPEN,622 config);623 if (ret < 0) {624 dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);625 return ret;626 }627 628 if (chip->chip_id == MAX77663)629 goto out;630 631 /* Disable WK_EN0 */632 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,633 MAX77620_ONOFFCNFG2_WK_EN0, 0);634 if (ret < 0) {635 dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);636 return ret;637 }638 639out:640 disable_irq(client->irq);641 642 return 0;643}644 645static int max77620_i2c_resume(struct device *dev)646{647 struct max77620_chip *chip = dev_get_drvdata(dev);648 struct i2c_client *client = to_i2c_client(dev);649 int ret;650 int fps;651 652 for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {653 if (chip->shutdown_fps_period[fps] < 0)654 continue;655 656 ret = max77620_set_fps_period(chip, fps,657 chip->shutdown_fps_period[fps]);658 if (ret < 0)659 return ret;660 }661 662 /*663 * For MAX20024: No need to configure WKEN0 on resume as664 * it is configured on Init.665 */666 if (chip->chip_id == MAX20024 || chip->chip_id == MAX77663)667 goto out;668 669 /* Enable WK_EN0 */670 ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,671 MAX77620_ONOFFCNFG2_WK_EN0,672 MAX77620_ONOFFCNFG2_WK_EN0);673 if (ret < 0) {674 dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);675 return ret;676 }677 678out:679 enable_irq(client->irq);680 681 return 0;682}683 684static const struct i2c_device_id max77620_id[] = {685 {"max77620", MAX77620},686 {"max20024", MAX20024},687 {"max77663", MAX77663},688 {},689};690 691static DEFINE_SIMPLE_DEV_PM_OPS(max77620_pm_ops,692 max77620_i2c_suspend, max77620_i2c_resume);693 694static struct i2c_driver max77620_driver = {695 .driver = {696 .name = "max77620",697 .pm = pm_sleep_ptr(&max77620_pm_ops),698 },699 .probe = max77620_probe,700 .id_table = max77620_id,701};702builtin_i2c_driver(max77620_driver);703