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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2020 MediaTek Inc.4 *5 * Author: Gene Chen <gene_chen@richtek.com>6 */7 8#include <linux/cleanup.h>9#include <linux/crc8.h>10#include <linux/i2c.h>11#include <linux/init.h>12#include <linux/interrupt.h>13#include <linux/kernel.h>14#include <linux/mfd/core.h>15#include <linux/module.h>16#include <linux/regmap.h>17#include <linux/slab.h>18 19enum {20 MT6360_SLAVE_TCPC = 0,21 MT6360_SLAVE_PMIC,22 MT6360_SLAVE_LDO,23 MT6360_SLAVE_PMU,24 MT6360_SLAVE_MAX,25};26 27struct mt6360_ddata {28 struct i2c_client *i2c[MT6360_SLAVE_MAX];29 struct device *dev;30 struct regmap *regmap;31 struct regmap_irq_chip_data *irq_data;32 unsigned int chip_rev;33 u8 crc8_tbl[CRC8_TABLE_SIZE];34};35 36#define MT6360_TCPC_SLAVEID 0x4E37#define MT6360_PMIC_SLAVEID 0x1A38#define MT6360_LDO_SLAVEID 0x6439#define MT6360_PMU_SLAVEID 0x3440 41#define MT6360_REG_TCPCSTART 0x0042#define MT6360_REG_TCPCEND 0xFF43#define MT6360_REG_PMICSTART 0x10044#define MT6360_REG_PMICEND 0x13B45#define MT6360_REG_LDOSTART 0x20046#define MT6360_REG_LDOEND 0x21C47#define MT6360_REG_PMUSTART 0x30048#define MT6360_PMU_DEV_INFO 0x30049#define MT6360_PMU_CHG_IRQ1 0x3D050#define MT6360_PMU_CHG_MASK1 0x3F051#define MT6360_REG_PMUEND 0x3FF52 53#define MT6360_PMU_IRQ_REGNUM 1654 55#define CHIP_VEN_MASK 0xF056#define CHIP_VEN_MT6360 0x5057#define CHIP_REV_MASK 0x0F58 59#define MT6360_ADDRESS_MASK 0x3F60#define MT6360_DATA_SIZE_1_BYTE 0x0061#define MT6360_DATA_SIZE_2_BYTES 0x4062#define MT6360_DATA_SIZE_3_BYTES 0x8063#define MT6360_DATA_SIZE_4_BYTES 0xC064 65#define MT6360_CRC8_POLYNOMIAL 0x766 67#define MT6360_CRC_I2C_ADDR_SIZE 168#define MT6360_CRC_REG_ADDR_SIZE 169/* prealloca read size = i2c device addr + i2c reg addr + val ... + crc8 */70#define MT6360_ALLOC_READ_SIZE(_size) (_size + 3)71/* prealloca write size = i2c device addr + i2c reg addr + val ... + crc8 + dummy byte */72#define MT6360_ALLOC_WRITE_SIZE(_size) (_size + 4)73#define MT6360_CRC_PREDATA_OFFSET (MT6360_CRC_I2C_ADDR_SIZE + MT6360_CRC_REG_ADDR_SIZE)74#define MT6360_CRC_CRC8_SIZE 175#define MT6360_CRC_DUMMY_BYTE_SIZE 176#define MT6360_REGMAP_REG_BYTE_SIZE 277#define I2C_ADDR_XLATE_8BIT(_addr, _rw) (((_addr & 0x7F) << 1) + _rw)78 79/* reg 0 -> 0 ~ 7 */80#define MT6360_CHG_TREG_EVT 481#define MT6360_CHG_AICR_EVT 582#define MT6360_CHG_MIVR_EVT 683#define MT6360_PWR_RDY_EVT 784/* REG 1 -> 8 ~ 15 */85#define MT6360_CHG_BATSYSUV_EVT 986#define MT6360_FLED_CHG_VINOVP_EVT 1187#define MT6360_CHG_VSYSUV_EVT 1288#define MT6360_CHG_VSYSOV_EVT 1389#define MT6360_CHG_VBATOV_EVT 1490#define MT6360_CHG_VBUSOV_EVT 1591/* REG 2 -> 16 ~ 23 */92/* REG 3 -> 24 ~ 31 */93#define MT6360_WD_PMU_DET 2594#define MT6360_WD_PMU_DONE 2695#define MT6360_CHG_TMRI 2796#define MT6360_CHG_ADPBADI 2997#define MT6360_CHG_RVPI 3098#define MT6360_OTPI 3199/* REG 4 -> 32 ~ 39 */100#define MT6360_CHG_AICCMEASL 32101#define MT6360_CHGDET_DONEI 34102#define MT6360_WDTMRI 35103#define MT6360_SSFINISHI 36104#define MT6360_CHG_RECHGI 37105#define MT6360_CHG_TERMI 38106#define MT6360_CHG_IEOCI 39107/* REG 5 -> 40 ~ 47 */108#define MT6360_PUMPX_DONEI 40109#define MT6360_BAT_OVP_ADC_EVT 41110#define MT6360_TYPEC_OTP_EVT 42111#define MT6360_ADC_WAKEUP_EVT 43112#define MT6360_ADC_DONEI 44113#define MT6360_BST_BATUVI 45114#define MT6360_BST_VBUSOVI 46115#define MT6360_BST_OLPI 47116/* REG 6 -> 48 ~ 55 */117#define MT6360_ATTACH_I 48118#define MT6360_DETACH_I 49119#define MT6360_QC30_STPDONE 51120#define MT6360_QC_VBUSDET_DONE 52121#define MT6360_HVDCP_DET 53122#define MT6360_CHGDETI 54123#define MT6360_DCDTI 55124/* REG 7 -> 56 ~ 63 */125#define MT6360_FOD_DONE_EVT 56126#define MT6360_FOD_OV_EVT 57127#define MT6360_CHRDET_UVP_EVT 58128#define MT6360_CHRDET_OVP_EVT 59129#define MT6360_CHRDET_EXT_EVT 60130#define MT6360_FOD_LR_EVT 61131#define MT6360_FOD_HR_EVT 62132#define MT6360_FOD_DISCHG_FAIL_EVT 63133/* REG 8 -> 64 ~ 71 */134#define MT6360_USBID_EVT 64135#define MT6360_APWDTRST_EVT 65136#define MT6360_EN_EVT 66137#define MT6360_QONB_RST_EVT 67138#define MT6360_MRSTB_EVT 68139#define MT6360_OTP_EVT 69140#define MT6360_VDDAOV_EVT 70141#define MT6360_SYSUV_EVT 71142/* REG 9 -> 72 ~ 79 */143#define MT6360_FLED_STRBPIN_EVT 72144#define MT6360_FLED_TORPIN_EVT 73145#define MT6360_FLED_TX_EVT 74146#define MT6360_FLED_LVF_EVT 75147#define MT6360_FLED2_SHORT_EVT 78148#define MT6360_FLED1_SHORT_EVT 79149/* REG 10 -> 80 ~ 87 */150#define MT6360_FLED2_STRB_EVT 80151#define MT6360_FLED1_STRB_EVT 81152#define MT6360_FLED2_STRB_TO_EVT 82153#define MT6360_FLED1_STRB_TO_EVT 83154#define MT6360_FLED2_TOR_EVT 84155#define MT6360_FLED1_TOR_EVT 85156/* REG 11 -> 88 ~ 95 */157/* REG 12 -> 96 ~ 103 */158#define MT6360_BUCK1_PGB_EVT 96159#define MT6360_BUCK1_OC_EVT 100160#define MT6360_BUCK1_OV_EVT 101161#define MT6360_BUCK1_UV_EVT 102162/* REG 13 -> 104 ~ 111 */163#define MT6360_BUCK2_PGB_EVT 104164#define MT6360_BUCK2_OC_EVT 108165#define MT6360_BUCK2_OV_EVT 109166#define MT6360_BUCK2_UV_EVT 110167/* REG 14 -> 112 ~ 119 */168#define MT6360_LDO1_OC_EVT 113169#define MT6360_LDO2_OC_EVT 114170#define MT6360_LDO3_OC_EVT 115171#define MT6360_LDO5_OC_EVT 117172#define MT6360_LDO6_OC_EVT 118173#define MT6360_LDO7_OC_EVT 119174/* REG 15 -> 120 ~ 127 */175#define MT6360_LDO1_PGB_EVT 121176#define MT6360_LDO2_PGB_EVT 122177#define MT6360_LDO3_PGB_EVT 123178#define MT6360_LDO5_PGB_EVT 125179#define MT6360_LDO6_PGB_EVT 126180#define MT6360_LDO7_PGB_EVT 127181 182static const struct regmap_irq mt6360_irqs[] = {183 REGMAP_IRQ_REG_LINE(MT6360_CHG_TREG_EVT, 8),184 REGMAP_IRQ_REG_LINE(MT6360_CHG_AICR_EVT, 8),185 REGMAP_IRQ_REG_LINE(MT6360_CHG_MIVR_EVT, 8),186 REGMAP_IRQ_REG_LINE(MT6360_PWR_RDY_EVT, 8),187 REGMAP_IRQ_REG_LINE(MT6360_CHG_BATSYSUV_EVT, 8),188 REGMAP_IRQ_REG_LINE(MT6360_FLED_CHG_VINOVP_EVT, 8),189 REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSUV_EVT, 8),190 REGMAP_IRQ_REG_LINE(MT6360_CHG_VSYSOV_EVT, 8),191 REGMAP_IRQ_REG_LINE(MT6360_CHG_VBATOV_EVT, 8),192 REGMAP_IRQ_REG_LINE(MT6360_CHG_VBUSOV_EVT, 8),193 REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DET, 8),194 REGMAP_IRQ_REG_LINE(MT6360_WD_PMU_DONE, 8),195 REGMAP_IRQ_REG_LINE(MT6360_CHG_TMRI, 8),196 REGMAP_IRQ_REG_LINE(MT6360_CHG_ADPBADI, 8),197 REGMAP_IRQ_REG_LINE(MT6360_CHG_RVPI, 8),198 REGMAP_IRQ_REG_LINE(MT6360_OTPI, 8),199 REGMAP_IRQ_REG_LINE(MT6360_CHG_AICCMEASL, 8),200 REGMAP_IRQ_REG_LINE(MT6360_CHGDET_DONEI, 8),201 REGMAP_IRQ_REG_LINE(MT6360_WDTMRI, 8),202 REGMAP_IRQ_REG_LINE(MT6360_SSFINISHI, 8),203 REGMAP_IRQ_REG_LINE(MT6360_CHG_RECHGI, 8),204 REGMAP_IRQ_REG_LINE(MT6360_CHG_TERMI, 8),205 REGMAP_IRQ_REG_LINE(MT6360_CHG_IEOCI, 8),206 REGMAP_IRQ_REG_LINE(MT6360_PUMPX_DONEI, 8),207 REGMAP_IRQ_REG_LINE(MT6360_BAT_OVP_ADC_EVT, 8),208 REGMAP_IRQ_REG_LINE(MT6360_TYPEC_OTP_EVT, 8),209 REGMAP_IRQ_REG_LINE(MT6360_ADC_WAKEUP_EVT, 8),210 REGMAP_IRQ_REG_LINE(MT6360_ADC_DONEI, 8),211 REGMAP_IRQ_REG_LINE(MT6360_BST_BATUVI, 8),212 REGMAP_IRQ_REG_LINE(MT6360_BST_VBUSOVI, 8),213 REGMAP_IRQ_REG_LINE(MT6360_BST_OLPI, 8),214 REGMAP_IRQ_REG_LINE(MT6360_ATTACH_I, 8),215 REGMAP_IRQ_REG_LINE(MT6360_DETACH_I, 8),216 REGMAP_IRQ_REG_LINE(MT6360_QC30_STPDONE, 8),217 REGMAP_IRQ_REG_LINE(MT6360_QC_VBUSDET_DONE, 8),218 REGMAP_IRQ_REG_LINE(MT6360_HVDCP_DET, 8),219 REGMAP_IRQ_REG_LINE(MT6360_CHGDETI, 8),220 REGMAP_IRQ_REG_LINE(MT6360_DCDTI, 8),221 REGMAP_IRQ_REG_LINE(MT6360_FOD_DONE_EVT, 8),222 REGMAP_IRQ_REG_LINE(MT6360_FOD_OV_EVT, 8),223 REGMAP_IRQ_REG_LINE(MT6360_CHRDET_UVP_EVT, 8),224 REGMAP_IRQ_REG_LINE(MT6360_CHRDET_OVP_EVT, 8),225 REGMAP_IRQ_REG_LINE(MT6360_CHRDET_EXT_EVT, 8),226 REGMAP_IRQ_REG_LINE(MT6360_FOD_LR_EVT, 8),227 REGMAP_IRQ_REG_LINE(MT6360_FOD_HR_EVT, 8),228 REGMAP_IRQ_REG_LINE(MT6360_FOD_DISCHG_FAIL_EVT, 8),229 REGMAP_IRQ_REG_LINE(MT6360_USBID_EVT, 8),230 REGMAP_IRQ_REG_LINE(MT6360_APWDTRST_EVT, 8),231 REGMAP_IRQ_REG_LINE(MT6360_EN_EVT, 8),232 REGMAP_IRQ_REG_LINE(MT6360_QONB_RST_EVT, 8),233 REGMAP_IRQ_REG_LINE(MT6360_MRSTB_EVT, 8),234 REGMAP_IRQ_REG_LINE(MT6360_OTP_EVT, 8),235 REGMAP_IRQ_REG_LINE(MT6360_VDDAOV_EVT, 8),236 REGMAP_IRQ_REG_LINE(MT6360_SYSUV_EVT, 8),237 REGMAP_IRQ_REG_LINE(MT6360_FLED_STRBPIN_EVT, 8),238 REGMAP_IRQ_REG_LINE(MT6360_FLED_TORPIN_EVT, 8),239 REGMAP_IRQ_REG_LINE(MT6360_FLED_TX_EVT, 8),240 REGMAP_IRQ_REG_LINE(MT6360_FLED_LVF_EVT, 8),241 REGMAP_IRQ_REG_LINE(MT6360_FLED2_SHORT_EVT, 8),242 REGMAP_IRQ_REG_LINE(MT6360_FLED1_SHORT_EVT, 8),243 REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_EVT, 8),244 REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_EVT, 8),245 REGMAP_IRQ_REG_LINE(MT6360_FLED2_STRB_TO_EVT, 8),246 REGMAP_IRQ_REG_LINE(MT6360_FLED1_STRB_TO_EVT, 8),247 REGMAP_IRQ_REG_LINE(MT6360_FLED2_TOR_EVT, 8),248 REGMAP_IRQ_REG_LINE(MT6360_FLED1_TOR_EVT, 8),249 REGMAP_IRQ_REG_LINE(MT6360_BUCK1_PGB_EVT, 8),250 REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OC_EVT, 8),251 REGMAP_IRQ_REG_LINE(MT6360_BUCK1_OV_EVT, 8),252 REGMAP_IRQ_REG_LINE(MT6360_BUCK1_UV_EVT, 8),253 REGMAP_IRQ_REG_LINE(MT6360_BUCK2_PGB_EVT, 8),254 REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OC_EVT, 8),255 REGMAP_IRQ_REG_LINE(MT6360_BUCK2_OV_EVT, 8),256 REGMAP_IRQ_REG_LINE(MT6360_BUCK2_UV_EVT, 8),257 REGMAP_IRQ_REG_LINE(MT6360_LDO1_OC_EVT, 8),258 REGMAP_IRQ_REG_LINE(MT6360_LDO2_OC_EVT, 8),259 REGMAP_IRQ_REG_LINE(MT6360_LDO3_OC_EVT, 8),260 REGMAP_IRQ_REG_LINE(MT6360_LDO5_OC_EVT, 8),261 REGMAP_IRQ_REG_LINE(MT6360_LDO6_OC_EVT, 8),262 REGMAP_IRQ_REG_LINE(MT6360_LDO7_OC_EVT, 8),263 REGMAP_IRQ_REG_LINE(MT6360_LDO1_PGB_EVT, 8),264 REGMAP_IRQ_REG_LINE(MT6360_LDO2_PGB_EVT, 8),265 REGMAP_IRQ_REG_LINE(MT6360_LDO3_PGB_EVT, 8),266 REGMAP_IRQ_REG_LINE(MT6360_LDO5_PGB_EVT, 8),267 REGMAP_IRQ_REG_LINE(MT6360_LDO6_PGB_EVT, 8),268 REGMAP_IRQ_REG_LINE(MT6360_LDO7_PGB_EVT, 8),269};270 271static const struct regmap_irq_chip mt6360_irq_chip = {272 .name = "mt6360_irqs",273 .irqs = mt6360_irqs,274 .num_irqs = ARRAY_SIZE(mt6360_irqs),275 .num_regs = MT6360_PMU_IRQ_REGNUM,276 .mask_base = MT6360_PMU_CHG_MASK1,277 .status_base = MT6360_PMU_CHG_IRQ1,278 .ack_base = MT6360_PMU_CHG_IRQ1,279 .init_ack_masked = true,280 .use_ack = true,281};282 283static const struct resource mt6360_adc_resources[] = {284 DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"),285};286 287static const struct resource mt6360_chg_resources[] = {288 DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"),289 DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"),290 DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, "chg_batsysuv_evt"),291 DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"),292 DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"),293 DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"),294 DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"),295 DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"),296 DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"),297 DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"),298 DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"),299 DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"),300 DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"),301 DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"),302 DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"),303};304 305static const struct resource mt6360_led_resources[] = {306 DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, "fled_chg_vinovp_evt"),307 DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"),308 DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"),309 DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"),310 DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, "fled2_strb_to_evt"),311 DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"),312};313 314static const struct resource mt6360_regulator_resources[] = {315 DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"),316 DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"),317 DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"),318 DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"),319 DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"),320 DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"),321 DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"),322 DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"),323 DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"),324 DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"),325 DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"),326 DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"),327 DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"),328 DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"),329 DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"),330 DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"),331 DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"),332 DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"),333 DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"),334 DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"),335};336 337static const struct mfd_cell mt6360_devs[] = {338 MFD_CELL_OF("mt6360-adc", mt6360_adc_resources,339 NULL, 0, 0, "mediatek,mt6360-adc"),340 MFD_CELL_OF("mt6360-chg", mt6360_chg_resources,341 NULL, 0, 0, "mediatek,mt6360-chg"),342 MFD_CELL_OF("mt6360-led", mt6360_led_resources,343 NULL, 0, 0, "mediatek,mt6360-led"),344 MFD_CELL_RES("mt6360-regulator", mt6360_regulator_resources),345 MFD_CELL_OF("mt6360-tcpc", NULL,346 NULL, 0, 0, "mediatek,mt6360-tcpc"),347};348 349static int mt6360_check_vendor_info(struct mt6360_ddata *ddata)350{351 u32 info;352 int ret;353 354 ret = regmap_read(ddata->regmap, MT6360_PMU_DEV_INFO, &info);355 if (ret < 0)356 return ret;357 358 if ((info & CHIP_VEN_MASK) != CHIP_VEN_MT6360) {359 dev_err(ddata->dev, "Device not supported\n");360 return -ENODEV;361 }362 363 ddata->chip_rev = info & CHIP_REV_MASK;364 365 return 0;366}367 368static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = {369 MT6360_TCPC_SLAVEID,370 MT6360_PMIC_SLAVEID,371 MT6360_LDO_SLAVEID,372 MT6360_PMU_SLAVEID,373};374 375static int mt6360_xlate_pmicldo_addr(u8 *addr, int rw_size)376{377 /* Address is already in encoded [5:0] */378 *addr &= MT6360_ADDRESS_MASK;379 380 switch (rw_size) {381 case 1:382 *addr |= MT6360_DATA_SIZE_1_BYTE;383 break;384 case 2:385 *addr |= MT6360_DATA_SIZE_2_BYTES;386 break;387 case 3:388 *addr |= MT6360_DATA_SIZE_3_BYTES;389 break;390 case 4:391 *addr |= MT6360_DATA_SIZE_4_BYTES;392 break;393 default:394 return -EINVAL;395 }396 397 return 0;398}399 400static int mt6360_regmap_read(void *context, const void *reg, size_t reg_size,401 void *val, size_t val_size)402{403 struct mt6360_ddata *ddata = context;404 u8 bank = *(u8 *)reg;405 u8 reg_addr = *(u8 *)(reg + 1);406 struct i2c_client *i2c;407 bool crc_needed = false;408 int buf_len = MT6360_ALLOC_READ_SIZE(val_size);409 int read_size = val_size;410 u8 crc;411 int ret;412 413 if (bank >= MT6360_SLAVE_MAX)414 return -EINVAL;415 416 i2c = ddata->i2c[bank];417 418 if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {419 crc_needed = true;420 ret = mt6360_xlate_pmicldo_addr(®_addr, val_size);421 if (ret < 0)422 return ret;423 read_size += MT6360_CRC_CRC8_SIZE;424 }425 426 u8 *buf __free(kfree) = kzalloc(buf_len, GFP_KERNEL);427 if (!buf)428 return -ENOMEM;429 430 buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_READ);431 buf[1] = reg_addr;432 433 ret = i2c_smbus_read_i2c_block_data(i2c, reg_addr, read_size,434 buf + MT6360_CRC_PREDATA_OFFSET);435 if (ret < 0)436 return ret;437 else if (ret != read_size)438 return -EIO;439 440 if (crc_needed) {441 crc = crc8(ddata->crc8_tbl, buf, val_size + MT6360_CRC_PREDATA_OFFSET, 0);442 if (crc != buf[val_size + MT6360_CRC_PREDATA_OFFSET])443 return -EIO;444 }445 446 memcpy(val, buf + MT6360_CRC_PREDATA_OFFSET, val_size);447 448 return 0;449}450 451static int mt6360_regmap_write(void *context, const void *val, size_t val_size)452{453 struct mt6360_ddata *ddata = context;454 u8 bank = *(u8 *)val;455 u8 reg_addr = *(u8 *)(val + 1);456 struct i2c_client *i2c;457 bool crc_needed = false;458 u8 *buf;459 int buf_len = MT6360_ALLOC_WRITE_SIZE(val_size);460 int write_size = val_size - MT6360_REGMAP_REG_BYTE_SIZE;461 int ret;462 463 if (bank >= MT6360_SLAVE_MAX)464 return -EINVAL;465 466 i2c = ddata->i2c[bank];467 468 if (bank == MT6360_SLAVE_PMIC || bank == MT6360_SLAVE_LDO) {469 crc_needed = true;470 ret = mt6360_xlate_pmicldo_addr(®_addr, val_size - MT6360_REGMAP_REG_BYTE_SIZE);471 if (ret < 0)472 return ret;473 }474 475 buf = kzalloc(buf_len, GFP_KERNEL);476 if (!buf)477 return -ENOMEM;478 479 buf[0] = I2C_ADDR_XLATE_8BIT(i2c->addr, I2C_SMBUS_WRITE);480 buf[1] = reg_addr;481 memcpy(buf + MT6360_CRC_PREDATA_OFFSET, val + MT6360_REGMAP_REG_BYTE_SIZE, write_size);482 483 if (crc_needed) {484 buf[val_size] = crc8(ddata->crc8_tbl, buf, val_size, 0);485 write_size += (MT6360_CRC_CRC8_SIZE + MT6360_CRC_DUMMY_BYTE_SIZE);486 }487 488 ret = i2c_smbus_write_i2c_block_data(i2c, reg_addr, write_size,489 buf + MT6360_CRC_PREDATA_OFFSET);490 491 kfree(buf);492 return ret;493}494 495static const struct regmap_bus mt6360_regmap_bus = {496 .read = mt6360_regmap_read,497 .write = mt6360_regmap_write,498 499 /* Due to PMIC and LDO CRC access size limit */500 .max_raw_read = 4,501 .max_raw_write = 4,502};503 504static bool mt6360_is_readwrite_reg(struct device *dev, unsigned int reg)505{506 switch (reg) {507 case MT6360_REG_TCPCSTART ... MT6360_REG_TCPCEND:508 fallthrough;509 case MT6360_REG_PMICSTART ... MT6360_REG_PMICEND:510 fallthrough;511 case MT6360_REG_LDOSTART ... MT6360_REG_LDOEND:512 fallthrough;513 case MT6360_REG_PMUSTART ... MT6360_REG_PMUEND:514 return true;515 }516 517 return false;518}519 520static const struct regmap_config mt6360_regmap_config = {521 .reg_bits = 16,522 .val_bits = 8,523 .reg_format_endian = REGMAP_ENDIAN_BIG,524 .max_register = MT6360_REG_PMUEND,525 .writeable_reg = mt6360_is_readwrite_reg,526 .readable_reg = mt6360_is_readwrite_reg,527};528 529static int mt6360_probe(struct i2c_client *client)530{531 struct mt6360_ddata *ddata;532 int i, ret;533 534 ddata = devm_kzalloc(&client->dev, sizeof(*ddata), GFP_KERNEL);535 if (!ddata)536 return -ENOMEM;537 538 ddata->dev = &client->dev;539 i2c_set_clientdata(client, ddata);540 541 for (i = 0; i < MT6360_SLAVE_MAX - 1; i++) {542 ddata->i2c[i] = devm_i2c_new_dummy_device(&client->dev,543 client->adapter,544 mt6360_slave_addr[i]);545 if (IS_ERR(ddata->i2c[i])) {546 dev_err(&client->dev,547 "Failed to get new dummy I2C device for address 0x%x",548 mt6360_slave_addr[i]);549 return PTR_ERR(ddata->i2c[i]);550 }551 }552 ddata->i2c[MT6360_SLAVE_MAX - 1] = client;553 554 crc8_populate_msb(ddata->crc8_tbl, MT6360_CRC8_POLYNOMIAL);555 ddata->regmap = devm_regmap_init(ddata->dev, &mt6360_regmap_bus, ddata,556 &mt6360_regmap_config);557 if (IS_ERR(ddata->regmap)) {558 dev_err(&client->dev, "Failed to register regmap\n");559 return PTR_ERR(ddata->regmap);560 }561 562 ret = mt6360_check_vendor_info(ddata);563 if (ret)564 return ret;565 566 ret = devm_regmap_add_irq_chip(&client->dev, ddata->regmap, client->irq,567 0, 0, &mt6360_irq_chip,568 &ddata->irq_data);569 if (ret) {570 dev_err(&client->dev, "Failed to add Regmap IRQ Chip\n");571 return ret;572 }573 574 ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO,575 mt6360_devs, ARRAY_SIZE(mt6360_devs), NULL,576 0, regmap_irq_get_domain(ddata->irq_data));577 if (ret) {578 dev_err(&client->dev,579 "Failed to register subordinate devices\n");580 return ret;581 }582 583 return 0;584}585 586static int __maybe_unused mt6360_suspend(struct device *dev)587{588 struct i2c_client *i2c = to_i2c_client(dev);589 590 if (device_may_wakeup(dev))591 enable_irq_wake(i2c->irq);592 593 return 0;594}595 596static int __maybe_unused mt6360_resume(struct device *dev)597{598 599 struct i2c_client *i2c = to_i2c_client(dev);600 601 if (device_may_wakeup(dev))602 disable_irq_wake(i2c->irq);603 604 return 0;605}606 607static SIMPLE_DEV_PM_OPS(mt6360_pm_ops, mt6360_suspend, mt6360_resume);608 609static const struct of_device_id __maybe_unused mt6360_of_id[] = {610 { .compatible = "mediatek,mt6360", },611 {},612};613MODULE_DEVICE_TABLE(of, mt6360_of_id);614 615static struct i2c_driver mt6360_driver = {616 .driver = {617 .name = "mt6360",618 .pm = &mt6360_pm_ops,619 .of_match_table = of_match_ptr(mt6360_of_id),620 },621 .probe = mt6360_probe,622};623module_i2c_driver(mt6360_driver);624 625MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>");626MODULE_DESCRIPTION("MT6360 I2C Driver");627MODULE_LICENSE("GPL v2");628