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1// SPDX-License-Identifier: GPL-2.0-only2/* linux/drivers/mfd/sm501.c3 *4 * Copyright (C) 2006 Simtec Electronics5 * Ben Dooks <ben@simtec.co.uk>6 * Vincent Sanders <vince@simtec.co.uk>7 *8 * SM501 MFD driver9*/10 11#include <linux/kernel.h>12#include <linux/module.h>13#include <linux/delay.h>14#include <linux/init.h>15#include <linux/list.h>16#include <linux/device.h>17#include <linux/platform_device.h>18#include <linux/pci.h>19#include <linux/platform_data/i2c-gpio.h>20#include <linux/gpio/driver.h>21#include <linux/gpio/machine.h>22#include <linux/slab.h>23 24#include <linux/sm501.h>25#include <linux/sm501-regs.h>26#include <linux/serial_8250.h>27 28#include <linux/io.h>29 30struct sm501_device {31 struct list_head list;32 struct platform_device pdev;33};34 35struct sm501_gpio;36 37#ifdef CONFIG_MFD_SM501_GPIO38#include <linux/gpio.h>39 40struct sm501_gpio_chip {41 struct gpio_chip gpio;42 struct sm501_gpio *ourgpio; /* to get back to parent. */43 void __iomem *regbase;44 void __iomem *control; /* address of control reg. */45};46 47struct sm501_gpio {48 struct sm501_gpio_chip low;49 struct sm501_gpio_chip high;50 spinlock_t lock;51 52 unsigned int registered : 1;53 void __iomem *regs;54 struct resource *regs_res;55};56#else57struct sm501_gpio {58 /* no gpio support, empty definition for sm501_devdata. */59};60#endif61 62struct sm501_devdata {63 spinlock_t reg_lock;64 struct mutex clock_lock;65 struct list_head devices;66 struct sm501_gpio gpio;67 68 struct device *dev;69 struct resource *io_res;70 struct resource *mem_res;71 struct resource *regs_claim;72 struct sm501_platdata *platdata;73 74 75 unsigned int in_suspend;76 unsigned long pm_misc;77 78 int unit_power[20];79 unsigned int pdev_id;80 unsigned int irq;81 void __iomem *regs;82 unsigned int rev;83};84 85 86#define MHZ (1000 * 1000)87 88#ifdef DEBUG89static const unsigned int div_tab[] = {90 [0] = 1,91 [1] = 2,92 [2] = 4,93 [3] = 8,94 [4] = 16,95 [5] = 32,96 [6] = 64,97 [7] = 128,98 [8] = 3,99 [9] = 6,100 [10] = 12,101 [11] = 24,102 [12] = 48,103 [13] = 96,104 [14] = 192,105 [15] = 384,106 [16] = 5,107 [17] = 10,108 [18] = 20,109 [19] = 40,110 [20] = 80,111 [21] = 160,112 [22] = 320,113 [23] = 604,114};115 116static unsigned long decode_div(unsigned long pll2, unsigned long val,117 unsigned int lshft, unsigned int selbit,118 unsigned long mask)119{120 if (val & selbit)121 pll2 = 288 * MHZ;122 123 return pll2 / div_tab[(val >> lshft) & mask];124}125 126#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)127 128/* sm501_dump_clk129 *130 * Print out the current clock configuration for the device131*/132 133static void sm501_dump_clk(struct sm501_devdata *sm)134{135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);139 unsigned long sdclk0, sdclk1;140 unsigned long pll2 = 0;141 142 switch (misct & 0x30) {143 case 0x00:144 pll2 = 336 * MHZ;145 break;146 case 0x10:147 pll2 = 288 * MHZ;148 break;149 case 0x20:150 pll2 = 240 * MHZ;151 break;152 case 0x30:153 pll2 = 192 * MHZ;154 break;155 }156 157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;158 sdclk0 /= div_tab[((misct >> 8) & 0xf)];159 160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;161 sdclk1 /= div_tab[((misct >> 16) & 0xf)];162 163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",164 misct, pm0, pm1);165 166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",167 fmt_freq(pll2), sdclk0, sdclk1);168 169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);170 171 dev_dbg(sm->dev, "PM0[%c]: "172 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",174 (pmc & 3 ) == 0 ? '*' : '-',175 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),176 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),177 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),178 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));179 180 dev_dbg(sm->dev, "PM1[%c]: "181 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",183 (pmc & 3 ) == 1 ? '*' : '-',184 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),185 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),186 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),187 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));188}189 190static void sm501_dump_regs(struct sm501_devdata *sm)191{192 void __iomem *regs = sm->regs;193 194 dev_info(sm->dev, "System Control %08x\n",195 smc501_readl(regs + SM501_SYSTEM_CONTROL));196 dev_info(sm->dev, "Misc Control %08x\n",197 smc501_readl(regs + SM501_MISC_CONTROL));198 dev_info(sm->dev, "GPIO Control Low %08x\n",199 smc501_readl(regs + SM501_GPIO31_0_CONTROL));200 dev_info(sm->dev, "GPIO Control Hi %08x\n",201 smc501_readl(regs + SM501_GPIO63_32_CONTROL));202 dev_info(sm->dev, "DRAM Control %08x\n",203 smc501_readl(regs + SM501_DRAM_CONTROL));204 dev_info(sm->dev, "Arbitration Ctrl %08x\n",205 smc501_readl(regs + SM501_ARBTRTN_CONTROL));206 dev_info(sm->dev, "Misc Timing %08x\n",207 smc501_readl(regs + SM501_MISC_TIMING));208}209 210static void sm501_dump_gate(struct sm501_devdata *sm)211{212 dev_info(sm->dev, "CurrentGate %08x\n",213 smc501_readl(sm->regs + SM501_CURRENT_GATE));214 dev_info(sm->dev, "CurrentClock %08x\n",215 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));216 dev_info(sm->dev, "PowerModeControl %08x\n",217 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));218}219 220#else221static inline void sm501_dump_gate(struct sm501_devdata *sm) { }222static inline void sm501_dump_regs(struct sm501_devdata *sm) { }223static inline void sm501_dump_clk(struct sm501_devdata *sm) { }224#endif225 226/* sm501_sync_regs227 *228 * ensure the229*/230 231static void sm501_sync_regs(struct sm501_devdata *sm)232{233 smc501_readl(sm->regs);234}235 236static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)237{238 /* during suspend/resume, we are currently not allowed to sleep,239 * so change to using mdelay() instead of msleep() if we240 * are in one of these paths */241 242 if (sm->in_suspend)243 mdelay(delay);244 else245 msleep(delay);246}247 248/* sm501_misc_control249 *250 * alters the miscellaneous control parameters251*/252 253int sm501_misc_control(struct device *dev,254 unsigned long set, unsigned long clear)255{256 struct sm501_devdata *sm = dev_get_drvdata(dev);257 unsigned long misc;258 unsigned long save;259 unsigned long to;260 261 spin_lock_irqsave(&sm->reg_lock, save);262 263 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);264 to = (misc & ~clear) | set;265 266 if (to != misc) {267 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);268 sm501_sync_regs(sm);269 270 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);271 }272 273 spin_unlock_irqrestore(&sm->reg_lock, save);274 return to;275}276 277EXPORT_SYMBOL_GPL(sm501_misc_control);278 279/* sm501_modify_reg280 *281 * Modify a register in the SM501 which may be shared with other282 * drivers.283*/284 285unsigned long sm501_modify_reg(struct device *dev,286 unsigned long reg,287 unsigned long set,288 unsigned long clear)289{290 struct sm501_devdata *sm = dev_get_drvdata(dev);291 unsigned long data;292 unsigned long save;293 294 spin_lock_irqsave(&sm->reg_lock, save);295 296 data = smc501_readl(sm->regs + reg);297 data |= set;298 data &= ~clear;299 300 smc501_writel(data, sm->regs + reg);301 sm501_sync_regs(sm);302 303 spin_unlock_irqrestore(&sm->reg_lock, save);304 305 return data;306}307 308EXPORT_SYMBOL_GPL(sm501_modify_reg);309 310/* sm501_unit_power311 *312 * alters the power active gate to set specific units on or off313 */314 315int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)316{317 struct sm501_devdata *sm = dev_get_drvdata(dev);318 unsigned long mode;319 unsigned long gate;320 unsigned long clock;321 322 mutex_lock(&sm->clock_lock);323 324 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);325 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);326 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);327 328 mode &= 3; /* get current power mode */329 330 if (unit >= ARRAY_SIZE(sm->unit_power)) {331 dev_err(dev, "%s: bad unit %d\n", __func__, unit);332 goto already;333 }334 335 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,336 sm->unit_power[unit], to);337 338 if (to == 0 && sm->unit_power[unit] == 0) {339 dev_err(sm->dev, "unit %d is already shutdown\n", unit);340 goto already;341 }342 343 sm->unit_power[unit] += to ? 1 : -1;344 to = sm->unit_power[unit] ? 1 : 0;345 346 if (to) {347 if (gate & (1 << unit))348 goto already;349 gate |= (1 << unit);350 } else {351 if (!(gate & (1 << unit)))352 goto already;353 gate &= ~(1 << unit);354 }355 356 switch (mode) {357 case 1:358 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);359 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);360 mode = 0;361 break;362 case 2:363 case 0:364 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);365 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);366 mode = 1;367 break;368 369 default:370 gate = -1;371 goto already;372 }373 374 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);375 sm501_sync_regs(sm);376 377 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",378 gate, clock, mode);379 380 sm501_mdelay(sm, 16);381 382 already:383 mutex_unlock(&sm->clock_lock);384 return gate;385}386 387EXPORT_SYMBOL_GPL(sm501_unit_power);388 389/* clock value structure. */390struct sm501_clock {391 unsigned long mclk;392 int divider;393 int shift;394 unsigned int m, n, k;395};396 397/* sm501_calc_clock398 *399 * Calculates the nearest discrete clock frequency that400 * can be achieved with the specified input clock.401 * the maximum divisor is 3 or 5402 */403 404static int sm501_calc_clock(unsigned long freq,405 struct sm501_clock *clock,406 int max_div,407 unsigned long mclk,408 long *best_diff)409{410 int ret = 0;411 int divider;412 int shift;413 long diff;414 415 /* try dividers 1 and 3 for CRT and for panel,416 try divider 5 for panel only.*/417 418 for (divider = 1; divider <= max_div; divider += 2) {419 /* try all 8 shift values.*/420 for (shift = 0; shift < 8; shift++) {421 /* Calculate difference to requested clock */422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;423 if (diff < 0)424 diff = -diff;425 426 /* If it is less than the current, use it */427 if (diff < *best_diff) {428 *best_diff = diff;429 430 clock->mclk = mclk;431 clock->divider = divider;432 clock->shift = shift;433 ret = 1;434 }435 }436 }437 438 return ret;439}440 441/* sm501_calc_pll442 *443 * Calculates the nearest discrete clock frequency that can be444 * achieved using the programmable PLL.445 * the maximum divisor is 3 or 5446 */447 448static unsigned long sm501_calc_pll(unsigned long freq,449 struct sm501_clock *clock,450 int max_div)451{452 unsigned long mclk;453 unsigned int m, n, k;454 long best_diff = 999999999;455 456 /*457 * The SM502 datasheet doesn't specify the min/max values for M and N.458 * N = 1 at least doesn't work in practice.459 */460 for (m = 2; m <= 255; m++) {461 for (n = 2; n <= 127; n++) {462 for (k = 0; k <= 1; k++) {463 mclk = (24000000UL * m / n) >> k;464 465 if (sm501_calc_clock(freq, clock, max_div,466 mclk, &best_diff)) {467 clock->m = m;468 clock->n = n;469 clock->k = k;470 }471 }472 }473 }474 475 /* Return best clock. */476 return clock->mclk / (clock->divider << clock->shift);477}478 479/* sm501_select_clock480 *481 * Calculates the nearest discrete clock frequency that can be482 * achieved using the 288MHz and 336MHz PLLs.483 * the maximum divisor is 3 or 5484 */485 486static unsigned long sm501_select_clock(unsigned long freq,487 struct sm501_clock *clock,488 int max_div)489{490 unsigned long mclk;491 long best_diff = 999999999;492 493 /* Try 288MHz and 336MHz clocks. */494 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {495 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);496 }497 498 /* Return best clock. */499 return clock->mclk / (clock->divider << clock->shift);500}501 502/* sm501_set_clock503 *504 * set one of the four clock sources to the closest available frequency to505 * the one specified506*/507 508unsigned long sm501_set_clock(struct device *dev,509 int clksrc,510 unsigned long req_freq)511{512 struct sm501_devdata *sm = dev_get_drvdata(dev);513 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);514 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);515 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);516 unsigned int pll_reg = 0;517 unsigned long sm501_freq; /* the actual frequency achieved */518 u64 reg;519 520 struct sm501_clock to;521 522 /* find achivable discrete frequency and setup register value523 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK524 * has an extra bit for the divider */525 526 switch (clksrc) {527 case SM501_CLOCK_P2XCLK:528 /* This clock is divided in half so to achieve the529 * requested frequency the value must be multiplied by530 * 2. This clock also has an additional pre divisor */531 532 if (sm->rev >= 0xC0) {533 /* SM502 -> use the programmable PLL */534 sm501_freq = (sm501_calc_pll(2 * req_freq,535 &to, 5) / 2);536 reg = to.shift & 0x07;/* bottom 3 bits are shift */537 if (to.divider == 3)538 reg |= 0x08; /* /3 divider required */539 else if (to.divider == 5)540 reg |= 0x10; /* /5 divider required */541 reg |= 0x40; /* select the programmable PLL */542 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;543 } else {544 sm501_freq = (sm501_select_clock(2 * req_freq,545 &to, 5) / 2);546 reg = to.shift & 0x07;/* bottom 3 bits are shift */547 if (to.divider == 3)548 reg |= 0x08; /* /3 divider required */549 else if (to.divider == 5)550 reg |= 0x10; /* /5 divider required */551 if (to.mclk != 288000000)552 reg |= 0x20; /* which mclk pll is source */553 }554 break;555 556 case SM501_CLOCK_V2XCLK:557 /* This clock is divided in half so to achieve the558 * requested frequency the value must be multiplied by 2. */559 560 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);561 reg=to.shift & 0x07; /* bottom 3 bits are shift */562 if (to.divider == 3)563 reg |= 0x08; /* /3 divider required */564 if (to.mclk != 288000000)565 reg |= 0x10; /* which mclk pll is source */566 break;567 568 case SM501_CLOCK_MCLK:569 case SM501_CLOCK_M1XCLK:570 /* These clocks are the same and not further divided */571 572 sm501_freq = sm501_select_clock( req_freq, &to, 3);573 reg=to.shift & 0x07; /* bottom 3 bits are shift */574 if (to.divider == 3)575 reg |= 0x08; /* /3 divider required */576 if (to.mclk != 288000000)577 reg |= 0x10; /* which mclk pll is source */578 break;579 580 default:581 return 0; /* this is bad */582 }583 584 mutex_lock(&sm->clock_lock);585 586 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);587 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);588 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);589 590 clock = clock & ~(0xFF << clksrc);591 clock |= reg<<clksrc;592 593 mode &= 3; /* find current mode */594 595 switch (mode) {596 case 1:597 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);598 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);599 mode = 0;600 break;601 case 2:602 case 0:603 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);604 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);605 mode = 1;606 break;607 608 default:609 mutex_unlock(&sm->clock_lock);610 return -1;611 }612 613 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);614 615 if (pll_reg)616 smc501_writel(pll_reg,617 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);618 619 sm501_sync_regs(sm);620 621 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",622 gate, clock, mode);623 624 sm501_mdelay(sm, 16);625 mutex_unlock(&sm->clock_lock);626 627 sm501_dump_clk(sm);628 629 return sm501_freq;630}631 632EXPORT_SYMBOL_GPL(sm501_set_clock);633 634/* sm501_find_clock635 *636 * finds the closest available frequency for a given clock637*/638 639unsigned long sm501_find_clock(struct device *dev,640 int clksrc,641 unsigned long req_freq)642{643 struct sm501_devdata *sm = dev_get_drvdata(dev);644 unsigned long sm501_freq; /* the frequency achieveable by the 501 */645 struct sm501_clock to;646 647 switch (clksrc) {648 case SM501_CLOCK_P2XCLK:649 if (sm->rev >= 0xC0) {650 /* SM502 -> use the programmable PLL */651 sm501_freq = (sm501_calc_pll(2 * req_freq,652 &to, 5) / 2);653 } else {654 sm501_freq = (sm501_select_clock(2 * req_freq,655 &to, 5) / 2);656 }657 break;658 659 case SM501_CLOCK_V2XCLK:660 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);661 break;662 663 case SM501_CLOCK_MCLK:664 case SM501_CLOCK_M1XCLK:665 sm501_freq = sm501_select_clock(req_freq, &to, 3);666 break;667 668 default:669 sm501_freq = 0; /* error */670 }671 672 return sm501_freq;673}674 675EXPORT_SYMBOL_GPL(sm501_find_clock);676 677static struct sm501_device *to_sm_device(struct platform_device *pdev)678{679 return container_of(pdev, struct sm501_device, pdev);680}681 682/* sm501_device_release683 *684 * A release function for the platform devices we create to allow us to685 * free any items we allocated686*/687 688static void sm501_device_release(struct device *dev)689{690 kfree(to_sm_device(to_platform_device(dev)));691}692 693/* sm501_create_subdev694 *695 * Create a skeleton platform device with resources for passing to a696 * sub-driver697*/698 699static struct platform_device *700sm501_create_subdev(struct sm501_devdata *sm, char *name,701 unsigned int res_count, unsigned int platform_data_size)702{703 struct sm501_device *smdev;704 705 smdev = kzalloc(sizeof(struct sm501_device) +706 (sizeof(struct resource) * res_count) +707 platform_data_size, GFP_KERNEL);708 if (!smdev)709 return NULL;710 711 smdev->pdev.dev.release = sm501_device_release;712 713 smdev->pdev.name = name;714 smdev->pdev.id = sm->pdev_id;715 smdev->pdev.dev.parent = sm->dev;716 smdev->pdev.dev.coherent_dma_mask = 0xffffffff;717 718 if (res_count) {719 smdev->pdev.resource = (struct resource *)(smdev+1);720 smdev->pdev.num_resources = res_count;721 }722 if (platform_data_size)723 smdev->pdev.dev.platform_data = (void *)(smdev+1);724 725 return &smdev->pdev;726}727 728/* sm501_register_device729 *730 * Register a platform device created with sm501_create_subdev()731*/732 733static int sm501_register_device(struct sm501_devdata *sm,734 struct platform_device *pdev)735{736 struct sm501_device *smdev = to_sm_device(pdev);737 int ptr;738 int ret;739 740 for (ptr = 0; ptr < pdev->num_resources; ptr++) {741 printk(KERN_DEBUG "%s[%d] %pR\n",742 pdev->name, ptr, &pdev->resource[ptr]);743 }744 745 ret = platform_device_register(pdev);746 747 if (ret >= 0) {748 dev_dbg(sm->dev, "registered %s\n", pdev->name);749 list_add_tail(&smdev->list, &sm->devices);750 } else751 dev_err(sm->dev, "error registering %s (%d)\n",752 pdev->name, ret);753 754 return ret;755}756 757/* sm501_create_subio758 *759 * Fill in an IO resource for a sub device760*/761 762static void sm501_create_subio(struct sm501_devdata *sm,763 struct resource *res,764 resource_size_t offs,765 resource_size_t size)766{767 res->flags = IORESOURCE_MEM;768 res->parent = sm->io_res;769 res->start = sm->io_res->start + offs;770 res->end = res->start + size - 1;771}772 773/* sm501_create_mem774 *775 * Fill in an MEM resource for a sub device776*/777 778static void sm501_create_mem(struct sm501_devdata *sm,779 struct resource *res,780 resource_size_t *offs,781 resource_size_t size)782{783 *offs -= size; /* adjust memory size */784 785 res->flags = IORESOURCE_MEM;786 res->parent = sm->mem_res;787 res->start = sm->mem_res->start + *offs;788 res->end = res->start + size - 1;789}790 791/* sm501_create_irq792 *793 * Fill in an IRQ resource for a sub device794*/795 796static void sm501_create_irq(struct sm501_devdata *sm,797 struct resource *res)798{799 res->flags = IORESOURCE_IRQ;800 res->parent = NULL;801 res->start = res->end = sm->irq;802}803 804static int sm501_register_usbhost(struct sm501_devdata *sm,805 resource_size_t *mem_avail)806{807 struct platform_device *pdev;808 809 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);810 if (!pdev)811 return -ENOMEM;812 813 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);814 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);815 sm501_create_irq(sm, &pdev->resource[2]);816 817 return sm501_register_device(sm, pdev);818}819 820static void sm501_setup_uart_data(struct sm501_devdata *sm,821 struct plat_serial8250_port *uart_data,822 unsigned int offset)823{824 uart_data->membase = sm->regs + offset;825 uart_data->mapbase = sm->io_res->start + offset;826 uart_data->iotype = UPIO_MEM;827 uart_data->irq = sm->irq;828 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;829 uart_data->regshift = 2;830 uart_data->uartclk = (9600 * 16);831}832 833static int sm501_register_uart(struct sm501_devdata *sm, int devices)834{835 struct platform_device *pdev;836 struct plat_serial8250_port *uart_data;837 838 pdev = sm501_create_subdev(sm, "serial8250", 0,839 sizeof(struct plat_serial8250_port) * 3);840 if (!pdev)841 return -ENOMEM;842 843 uart_data = dev_get_platdata(&pdev->dev);844 845 if (devices & SM501_USE_UART0) {846 sm501_setup_uart_data(sm, uart_data++, 0x30000);847 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);848 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);849 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);850 }851 if (devices & SM501_USE_UART1) {852 sm501_setup_uart_data(sm, uart_data++, 0x30020);853 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);854 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);855 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);856 }857 858 pdev->id = PLAT8250_DEV_SM501;859 860 return sm501_register_device(sm, pdev);861}862 863static int sm501_register_display(struct sm501_devdata *sm,864 resource_size_t *mem_avail)865{866 struct platform_device *pdev;867 868 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);869 if (!pdev)870 return -ENOMEM;871 872 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);873 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);874 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);875 sm501_create_irq(sm, &pdev->resource[3]);876 877 return sm501_register_device(sm, pdev);878}879 880#ifdef CONFIG_MFD_SM501_GPIO881 882static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)883{884 return container_of(gpio, struct sm501_devdata, gpio);885}886 887static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)888 889{890 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);891 unsigned long result;892 893 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);894 result >>= offset;895 896 return result & 1UL;897}898 899static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,900 unsigned long bit)901{902 unsigned long ctrl;903 904 /* check and modify if this pin is not set as gpio. */905 906 if (smc501_readl(smchip->control) & bit) {907 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,908 "changing mode of gpio, bit %08lx\n", bit);909 910 ctrl = smc501_readl(smchip->control);911 ctrl &= ~bit;912 smc501_writel(ctrl, smchip->control);913 914 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));915 }916}917 918static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)919 920{921 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);922 struct sm501_gpio *smgpio = smchip->ourgpio;923 unsigned long bit = 1 << offset;924 void __iomem *regs = smchip->regbase;925 unsigned long save;926 unsigned long val;927 928 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",929 __func__, chip, offset);930 931 spin_lock_irqsave(&smgpio->lock, save);932 933 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;934 if (value)935 val |= bit;936 smc501_writel(val, regs);937 938 sm501_sync_regs(sm501_gpio_to_dev(smgpio));939 sm501_gpio_ensure_gpio(smchip, bit);940 941 spin_unlock_irqrestore(&smgpio->lock, save);942}943 944static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)945{946 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);947 struct sm501_gpio *smgpio = smchip->ourgpio;948 void __iomem *regs = smchip->regbase;949 unsigned long bit = 1 << offset;950 unsigned long save;951 unsigned long ddr;952 953 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",954 __func__, chip, offset);955 956 spin_lock_irqsave(&smgpio->lock, save);957 958 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);959 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);960 961 sm501_sync_regs(sm501_gpio_to_dev(smgpio));962 sm501_gpio_ensure_gpio(smchip, bit);963 964 spin_unlock_irqrestore(&smgpio->lock, save);965 966 return 0;967}968 969static int sm501_gpio_output(struct gpio_chip *chip,970 unsigned offset, int value)971{972 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);973 struct sm501_gpio *smgpio = smchip->ourgpio;974 unsigned long bit = 1 << offset;975 void __iomem *regs = smchip->regbase;976 unsigned long save;977 unsigned long val;978 unsigned long ddr;979 980 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",981 __func__, chip, offset, value);982 983 spin_lock_irqsave(&smgpio->lock, save);984 985 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);986 if (value)987 val |= bit;988 else989 val &= ~bit;990 smc501_writel(val, regs);991 992 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);993 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);994 995 sm501_sync_regs(sm501_gpio_to_dev(smgpio));996 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);997 998 sm501_sync_regs(sm501_gpio_to_dev(smgpio));999 spin_unlock_irqrestore(&smgpio->lock, save);1000 1001 return 0;1002}1003 1004static const struct gpio_chip gpio_chip_template = {1005 .ngpio = 32,1006 .direction_input = sm501_gpio_input,1007 .direction_output = sm501_gpio_output,1008 .set = sm501_gpio_set,1009 .get = sm501_gpio_get,1010};1011 1012static int sm501_gpio_register_chip(struct sm501_devdata *sm,1013 struct sm501_gpio *gpio,1014 struct sm501_gpio_chip *chip)1015{1016 struct sm501_platdata *pdata = sm->platdata;1017 struct gpio_chip *gchip = &chip->gpio;1018 int base = pdata->gpio_base;1019 1020 chip->gpio = gpio_chip_template;1021 1022 if (chip == &gpio->high) {1023 if (base > 0)1024 base += 32;1025 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;1026 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;1027 gchip->label = "SM501-HIGH";1028 } else {1029 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;1030 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;1031 gchip->label = "SM501-LOW";1032 }1033 1034 gchip->base = base;1035 chip->ourgpio = gpio;1036 1037 return gpiochip_add_data(gchip, chip);1038}1039 1040static int sm501_register_gpio(struct sm501_devdata *sm)1041{1042 struct sm501_gpio *gpio = &sm->gpio;1043 resource_size_t iobase = sm->io_res->start + SM501_GPIO;1044 int ret;1045 1046 dev_dbg(sm->dev, "registering gpio block %08llx\n",1047 (unsigned long long)iobase);1048 1049 spin_lock_init(&gpio->lock);1050 1051 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");1052 if (!gpio->regs_res) {1053 dev_err(sm->dev, "gpio: failed to request region\n");1054 return -ENXIO;1055 }1056 1057 gpio->regs = ioremap(iobase, 0x20);1058 if (!gpio->regs) {1059 dev_err(sm->dev, "gpio: failed to remap registers\n");1060 ret = -ENXIO;1061 goto err_claimed;1062 }1063 1064 /* Register both our chips. */1065 1066 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);1067 if (ret) {1068 dev_err(sm->dev, "failed to add low chip\n");1069 goto err_mapped;1070 }1071 1072 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);1073 if (ret) {1074 dev_err(sm->dev, "failed to add high chip\n");1075 goto err_low_chip;1076 }1077 1078 gpio->registered = 1;1079 1080 return 0;1081 1082 err_low_chip:1083 gpiochip_remove(&gpio->low.gpio);1084 1085 err_mapped:1086 iounmap(gpio->regs);1087 1088 err_claimed:1089 release_mem_region(iobase, 0x20);1090 1091 return ret;1092}1093 1094static void sm501_gpio_remove(struct sm501_devdata *sm)1095{1096 struct sm501_gpio *gpio = &sm->gpio;1097 resource_size_t iobase = sm->io_res->start + SM501_GPIO;1098 1099 if (!sm->gpio.registered)1100 return;1101 1102 gpiochip_remove(&gpio->low.gpio);1103 gpiochip_remove(&gpio->high.gpio);1104 1105 iounmap(gpio->regs);1106 release_mem_region(iobase, 0x20);1107}1108 1109static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)1110{1111 return sm->gpio.registered;1112}1113#else1114static inline int sm501_register_gpio(struct sm501_devdata *sm)1115{1116 return 0;1117}1118 1119static inline void sm501_gpio_remove(struct sm501_devdata *sm)1120{1121}1122 1123static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)1124{1125 return 0;1126}1127#endif1128 1129static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,1130 struct sm501_platdata_gpio_i2c *iic)1131{1132 struct i2c_gpio_platform_data *icd;1133 struct platform_device *pdev;1134 struct gpiod_lookup_table *lookup;1135 1136 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,1137 sizeof(struct i2c_gpio_platform_data));1138 if (!pdev)1139 return -ENOMEM;1140 1141 /* Create a gpiod lookup using gpiochip-local offsets */1142 lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3),1143 GFP_KERNEL);1144 if (!lookup)1145 return -ENOMEM;1146 1147 lookup->dev_id = "i2c-gpio";1148 lookup->table[0] = (struct gpiod_lookup)1149 GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH",1150 iic->pin_sda % 32, NULL, 0,1151 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);1152 lookup->table[1] = (struct gpiod_lookup)1153 GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH",1154 iic->pin_scl % 32, NULL, 1,1155 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);1156 gpiod_add_lookup_table(lookup);1157 1158 icd = dev_get_platdata(&pdev->dev);1159 icd->timeout = iic->timeout;1160 icd->udelay = iic->udelay;1161 1162 /* note, we can't use either of the pin numbers, as the i2c-gpio1163 * driver uses the platform.id field to generate the bus number1164 * to register with the i2c core; The i2c core doesn't have enough1165 * entries to deal with anything we currently use.1166 */1167 1168 pdev->id = iic->bus_num;1169 1170 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",1171 iic->bus_num,1172 iic->pin_sda, iic->pin_scl);1173 1174 return sm501_register_device(sm, pdev);1175}1176 1177static int sm501_register_gpio_i2c(struct sm501_devdata *sm,1178 struct sm501_platdata *pdata)1179{1180 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;1181 int index;1182 int ret;1183 1184 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {1185 ret = sm501_register_gpio_i2c_instance(sm, iic);1186 if (ret < 0)1187 return ret;1188 }1189 1190 return 0;1191}1192 1193/* dbg_regs_show1194 *1195 * Debug attribute to attach to parent device to show core registers1196*/1197 1198static ssize_t dbg_regs_show(struct device *dev,1199 struct device_attribute *attr, char *buff)1200{1201 struct sm501_devdata *sm = dev_get_drvdata(dev) ;1202 unsigned int reg;1203 char *ptr = buff;1204 int ret;1205 1206 for (reg = 0x00; reg < 0x70; reg += 4) {1207 ret = sprintf(ptr, "%08x = %08x\n",1208 reg, smc501_readl(sm->regs + reg));1209 ptr += ret;1210 }1211 1212 return ptr - buff;1213}1214 1215 1216static DEVICE_ATTR_RO(dbg_regs);1217 1218/* sm501_init_reg1219 *1220 * Helper function for the init code to setup a register1221 *1222 * clear the bits which are set in r->mask, and then set1223 * the bits set in r->set.1224*/1225 1226static inline void sm501_init_reg(struct sm501_devdata *sm,1227 unsigned long reg,1228 struct sm501_reg_init *r)1229{1230 unsigned long tmp;1231 1232 tmp = smc501_readl(sm->regs + reg);1233 tmp &= ~r->mask;1234 tmp |= r->set;1235 smc501_writel(tmp, sm->regs + reg);1236}1237 1238/* sm501_init_regs1239 *1240 * Setup core register values1241*/1242 1243static void sm501_init_regs(struct sm501_devdata *sm,1244 struct sm501_initdata *init)1245{1246 sm501_misc_control(sm->dev,1247 init->misc_control.set,1248 init->misc_control.mask);1249 1250 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);1251 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);1252 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);1253 1254 if (init->m1xclk) {1255 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);1256 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);1257 }1258 1259 if (init->mclk) {1260 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);1261 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);1262 }1263 1264}1265 1266/* Check the PLL sources for the M1CLK and M1XCLK1267 *1268 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then1269 * there is a risk (see errata AB-5) that the SM501 will cease proper1270 * function. If this happens, then it is likely the SM501 will1271 * hang the system.1272*/1273 1274static int sm501_check_clocks(struct sm501_devdata *sm)1275{1276 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);1277 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);1278 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);1279 1280 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));1281}1282 1283static unsigned int sm501_mem_local[] = {1284 [0] = 4*1024*1024,1285 [1] = 8*1024*1024,1286 [2] = 16*1024*1024,1287 [3] = 32*1024*1024,1288 [4] = 64*1024*1024,1289 [5] = 2*1024*1024,1290};1291 1292/* sm501_init_dev1293 *1294 * Common init code for an SM5011295*/1296 1297static int sm501_init_dev(struct sm501_devdata *sm)1298{1299 struct sm501_initdata *idata;1300 struct sm501_platdata *pdata;1301 resource_size_t mem_avail;1302 unsigned long dramctrl;1303 unsigned long devid;1304 int ret;1305 1306 mutex_init(&sm->clock_lock);1307 spin_lock_init(&sm->reg_lock);1308 1309 INIT_LIST_HEAD(&sm->devices);1310 1311 devid = smc501_readl(sm->regs + SM501_DEVICEID);1312 1313 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {1314 dev_err(sm->dev, "incorrect device id %08lx\n", devid);1315 return -EINVAL;1316 }1317 1318 /* disable irqs */1319 smc501_writel(0, sm->regs + SM501_IRQ_MASK);1320 1321 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);1322 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];1323 1324 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",1325 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);1326 1327 sm->rev = devid & SM501_DEVICEID_REVMASK;1328 1329 sm501_dump_gate(sm);1330 1331 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);1332 if (ret)1333 dev_err(sm->dev, "failed to create debug regs file\n");1334 1335 sm501_dump_clk(sm);1336 1337 /* check to see if we have some device initialisation */1338 1339 pdata = sm->platdata;1340 idata = pdata ? pdata->init : NULL;1341 1342 if (idata) {1343 sm501_init_regs(sm, idata);1344 1345 if (idata->devices & SM501_USE_USB_HOST)1346 sm501_register_usbhost(sm, &mem_avail);1347 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))1348 sm501_register_uart(sm, idata->devices);1349 if (idata->devices & SM501_USE_GPIO)1350 sm501_register_gpio(sm);1351 }1352 1353 if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) {1354 if (!sm501_gpio_isregistered(sm))1355 dev_err(sm->dev, "no gpio available for i2c gpio.\n");1356 else1357 sm501_register_gpio_i2c(sm, pdata);1358 }1359 1360 ret = sm501_check_clocks(sm);1361 if (ret) {1362 dev_err(sm->dev, "M1X and M clocks sourced from different "1363 "PLLs\n");1364 return -EINVAL;1365 }1366 1367 /* always create a framebuffer */1368 sm501_register_display(sm, &mem_avail);1369 1370 return 0;1371}1372 1373static int sm501_plat_probe(struct platform_device *dev)1374{1375 struct sm501_devdata *sm;1376 int ret;1377 1378 sm = kzalloc(sizeof(*sm), GFP_KERNEL);1379 if (!sm) {1380 ret = -ENOMEM;1381 goto err1;1382 }1383 1384 sm->dev = &dev->dev;1385 sm->pdev_id = dev->id;1386 sm->platdata = dev_get_platdata(&dev->dev);1387 1388 ret = platform_get_irq(dev, 0);1389 if (ret < 0)1390 goto err_res;1391 sm->irq = ret;1392 1393 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);1394 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);1395 if (!sm->io_res || !sm->mem_res) {1396 dev_err(&dev->dev, "failed to get IO resource\n");1397 ret = -ENOENT;1398 goto err_res;1399 }1400 1401 sm->regs_claim = request_mem_region(sm->io_res->start,1402 0x100, "sm501");1403 if (!sm->regs_claim) {1404 dev_err(&dev->dev, "cannot claim registers\n");1405 ret = -EBUSY;1406 goto err_res;1407 }1408 1409 platform_set_drvdata(dev, sm);1410 1411 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));1412 if (!sm->regs) {1413 dev_err(&dev->dev, "cannot remap registers\n");1414 ret = -EIO;1415 goto err_claim;1416 }1417 1418 ret = sm501_init_dev(sm);1419 if (ret)1420 goto err_unmap;1421 1422 return 0;1423 1424 err_unmap:1425 iounmap(sm->regs);1426 err_claim:1427 release_mem_region(sm->io_res->start, 0x100);1428 err_res:1429 kfree(sm);1430 err1:1431 return ret;1432 1433}1434 1435/* power management support */1436 1437static void sm501_set_power(struct sm501_devdata *sm, int on)1438{1439 struct sm501_platdata *pd = sm->platdata;1440 1441 if (!pd)1442 return;1443 1444 if (pd->get_power) {1445 if (pd->get_power(sm->dev) == on) {1446 dev_dbg(sm->dev, "is already %d\n", on);1447 return;1448 }1449 }1450 1451 if (pd->set_power) {1452 dev_dbg(sm->dev, "setting power to %d\n", on);1453 1454 pd->set_power(sm->dev, on);1455 sm501_mdelay(sm, 10);1456 }1457}1458 1459static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)1460{1461 struct sm501_devdata *sm = platform_get_drvdata(pdev);1462 1463 sm->in_suspend = 1;1464 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);1465 1466 sm501_dump_regs(sm);1467 1468 if (sm->platdata) {1469 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)1470 sm501_set_power(sm, 0);1471 }1472 1473 return 0;1474}1475 1476static int sm501_plat_resume(struct platform_device *pdev)1477{1478 struct sm501_devdata *sm = platform_get_drvdata(pdev);1479 1480 sm501_set_power(sm, 1);1481 1482 sm501_dump_regs(sm);1483 sm501_dump_gate(sm);1484 sm501_dump_clk(sm);1485 1486 /* check to see if we are in the same state as when suspended */1487 1488 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {1489 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");1490 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);1491 1492 /* our suspend causes the controller state to change,1493 * either by something attempting setup, power loss,1494 * or an external reset event on power change */1495 1496 if (sm->platdata && sm->platdata->init) {1497 sm501_init_regs(sm, sm->platdata->init);1498 }1499 }1500 1501 /* dump our state from resume */1502 1503 sm501_dump_regs(sm);1504 sm501_dump_clk(sm);1505 1506 sm->in_suspend = 0;1507 1508 return 0;1509}1510 1511/* Initialisation data for PCI devices */1512 1513static struct sm501_initdata sm501_pci_initdata = {1514 .gpio_high = {1515 .set = 0x3F000000, /* 24bit panel */1516 .mask = 0x0,1517 },1518 .misc_timing = {1519 .set = 0x010100, /* SDRAM timing */1520 .mask = 0x1F1F00,1521 },1522 .misc_control = {1523 .set = SM501_MISC_PNL_24BIT,1524 .mask = 0,1525 },1526 1527 .devices = SM501_USE_ALL,1528 1529 /* Errata AB-3 says that 72MHz is the fastest available1530 * for 33MHZ PCI with proper bus-mastering operation */1531 1532 .mclk = 72 * MHZ,1533 .m1xclk = 144 * MHZ,1534};1535 1536static struct sm501_platdata_fbsub sm501_pdata_fbsub = {1537 .flags = (SM501FB_FLAG_USE_INIT_MODE |1538 SM501FB_FLAG_USE_HWCURSOR |1539 SM501FB_FLAG_USE_HWACCEL |1540 SM501FB_FLAG_DISABLE_AT_EXIT),1541};1542 1543static struct sm501_platdata_fb sm501_fb_pdata = {1544 .fb_route = SM501_FB_OWN,1545 .fb_crt = &sm501_pdata_fbsub,1546 .fb_pnl = &sm501_pdata_fbsub,1547};1548 1549static struct sm501_platdata sm501_pci_platdata = {1550 .init = &sm501_pci_initdata,1551 .fb = &sm501_fb_pdata,1552 .gpio_base = -1,1553};1554 1555static int sm501_pci_probe(struct pci_dev *dev,1556 const struct pci_device_id *id)1557{1558 struct sm501_devdata *sm;1559 int err;1560 1561 sm = kzalloc(sizeof(*sm), GFP_KERNEL);1562 if (!sm) {1563 err = -ENOMEM;1564 goto err1;1565 }1566 1567 /* set a default set of platform data */1568 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;1569 1570 /* set a hopefully unique id for our child platform devices */1571 sm->pdev_id = 32 + dev->devfn;1572 1573 pci_set_drvdata(dev, sm);1574 1575 err = pci_enable_device(dev);1576 if (err) {1577 dev_err(&dev->dev, "cannot enable device\n");1578 goto err2;1579 }1580 1581 sm->dev = &dev->dev;1582 sm->irq = dev->irq;1583 1584#ifdef __BIG_ENDIAN1585 /* if the system is big-endian, we most probably have a1586 * translation in the IO layer making the PCI bus little endian1587 * so make the framebuffer swapped pixels */1588 1589 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;1590#endif1591 1592 /* check our resources */1593 1594 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {1595 dev_err(&dev->dev, "region #0 is not memory?\n");1596 err = -EINVAL;1597 goto err3;1598 }1599 1600 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {1601 dev_err(&dev->dev, "region #1 is not memory?\n");1602 err = -EINVAL;1603 goto err3;1604 }1605 1606 /* make our resources ready for sharing */1607 1608 sm->io_res = &dev->resource[1];1609 sm->mem_res = &dev->resource[0];1610 1611 sm->regs_claim = request_mem_region(sm->io_res->start,1612 0x100, "sm501");1613 if (!sm->regs_claim) {1614 dev_err(&dev->dev, "cannot claim registers\n");1615 err= -EBUSY;1616 goto err3;1617 }1618 1619 sm->regs = pci_ioremap_bar(dev, 1);1620 if (!sm->regs) {1621 dev_err(&dev->dev, "cannot remap registers\n");1622 err = -EIO;1623 goto err4;1624 }1625 1626 sm501_init_dev(sm);1627 return 0;1628 1629 err4:1630 release_mem_region(sm->io_res->start, 0x100);1631 err3:1632 pci_disable_device(dev);1633 err2:1634 kfree(sm);1635 err1:1636 return err;1637}1638 1639static void sm501_remove_sub(struct sm501_devdata *sm,1640 struct sm501_device *smdev)1641{1642 list_del(&smdev->list);1643 platform_device_unregister(&smdev->pdev);1644}1645 1646static void sm501_dev_remove(struct sm501_devdata *sm)1647{1648 struct sm501_device *smdev, *tmp;1649 1650 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)1651 sm501_remove_sub(sm, smdev);1652 1653 device_remove_file(sm->dev, &dev_attr_dbg_regs);1654 1655 sm501_gpio_remove(sm);1656}1657 1658static void sm501_pci_remove(struct pci_dev *dev)1659{1660 struct sm501_devdata *sm = pci_get_drvdata(dev);1661 1662 sm501_dev_remove(sm);1663 iounmap(sm->regs);1664 1665 release_mem_region(sm->io_res->start, 0x100);1666 1667 pci_disable_device(dev);1668}1669 1670static void sm501_plat_remove(struct platform_device *dev)1671{1672 struct sm501_devdata *sm = platform_get_drvdata(dev);1673 1674 sm501_dev_remove(sm);1675 iounmap(sm->regs);1676 1677 release_mem_region(sm->io_res->start, 0x100);1678}1679 1680static const struct pci_device_id sm501_pci_tbl[] = {1681 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },1682 { 0, },1683};1684 1685MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);1686 1687static struct pci_driver sm501_pci_driver = {1688 .name = "sm501",1689 .id_table = sm501_pci_tbl,1690 .probe = sm501_pci_probe,1691 .remove = sm501_pci_remove,1692};1693 1694MODULE_ALIAS("platform:sm501");1695 1696static const struct of_device_id of_sm501_match_tbl[] = {1697 { .compatible = "smi,sm501", },1698 { /* end */ }1699};1700MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);1701 1702static struct platform_driver sm501_plat_driver = {1703 .driver = {1704 .name = "sm501",1705 .of_match_table = of_sm501_match_tbl,1706 },1707 .probe = sm501_plat_probe,1708 .remove_new = sm501_plat_remove,1709 .suspend = pm_sleep_ptr(sm501_plat_suspend),1710 .resume = pm_sleep_ptr(sm501_plat_resume),1711};1712 1713static int __init sm501_base_init(void)1714{1715 int ret;1716 1717 ret = platform_driver_register(&sm501_plat_driver);1718 if (ret < 0)1719 return ret;1720 1721 return pci_register_driver(&sm501_pci_driver);1722}1723 1724static void __exit sm501_base_exit(void)1725{1726 platform_driver_unregister(&sm501_plat_driver);1727 pci_unregister_driver(&sm501_pci_driver);1728}1729 1730module_init(sm501_base_init);1731module_exit(sm501_base_exit);1732 1733MODULE_DESCRIPTION("SM501 Core Driver");1734MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");1735MODULE_LICENSE("GPL v2");1736