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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) ST-Ericsson SA 20104 *5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson6 */7 8#ifndef __STMPE_H9#define __STMPE_H10 11#include <linux/device.h>12#include <linux/mfd/core.h>13#include <linux/mfd/stmpe.h>14#include <linux/printk.h>15#include <linux/types.h>16 17extern const struct dev_pm_ops stmpe_dev_pm_ops;18 19#ifdef STMPE_DUMP_BYTES20static inline void stmpe_dump_bytes(const char *str, const void *buf,21 size_t len)22{23 print_hex_dump_bytes(str, DUMP_PREFIX_OFFSET, buf, len);24}25#else26static inline void stmpe_dump_bytes(const char *str, const void *buf,27 size_t len)28{29}30#endif31 32/**33 * struct stmpe_variant_block - information about block34 * @cell: base mfd cell35 * @irq: interrupt number to be added to each IORESOURCE_IRQ36 * in the cell37 * @block: block id; used for identification with platform data and for38 * enable and altfunc callbacks39 */40struct stmpe_variant_block {41 const struct mfd_cell *cell;42 int irq;43 enum stmpe_block block;44};45 46/**47 * struct stmpe_variant_info - variant-specific information48 * @name: part name49 * @id_val: content of CHIPID register50 * @id_mask: bits valid in CHIPID register for comparison with id_val51 * @num_gpios: number of GPIOS52 * @af_bits: number of bits used to specify the alternate function53 * @regs: variant specific registers.54 * @blocks: list of blocks present on this device55 * @num_blocks: number of blocks present on this device56 * @num_irqs: number of internal IRQs available on this device57 * @enable: callback to enable the specified blocks.58 * Called with the I/O lock held.59 * @get_altfunc: callback to get the alternate function number for the60 * specific block61 * @enable_autosleep: callback to configure autosleep with specified timeout62 */63struct stmpe_variant_info {64 const char *name;65 u16 id_val;66 u16 id_mask;67 int num_gpios;68 int af_bits;69 const u8 *regs;70 struct stmpe_variant_block *blocks;71 int num_blocks;72 int num_irqs;73 int (*enable)(struct stmpe *stmpe, unsigned int blocks, bool enable);74 int (*get_altfunc)(struct stmpe *stmpe, enum stmpe_block block);75 int (*enable_autosleep)(struct stmpe *stmpe, int autosleep_timeout);76};77 78/**79 * struct stmpe_client_info - i2c or spi specific routines/info80 * @data: client specific data81 * @read_byte: read single byte82 * @write_byte: write single byte83 * @read_block: read block or multiple bytes84 * @write_block: write block or multiple bytes85 * @init: client init routine, called during probe86 */87struct stmpe_client_info {88 void *data;89 int irq;90 void *client;91 struct device *dev;92 int (*read_byte)(struct stmpe *stmpe, u8 reg);93 int (*write_byte)(struct stmpe *stmpe, u8 reg, u8 val);94 int (*read_block)(struct stmpe *stmpe, u8 reg, u8 len, u8 *values);95 int (*write_block)(struct stmpe *stmpe, u8 reg, u8 len,96 const u8 *values);97 void (*init)(struct stmpe *stmpe);98};99 100int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum);101void stmpe_remove(struct stmpe *stmpe);102 103#define STMPE_ICR_LSB_HIGH (1 << 2)104#define STMPE_ICR_LSB_EDGE (1 << 1)105#define STMPE_ICR_LSB_GIM (1 << 0)106 107#define STMPE_SYS_CTRL_RESET (1 << 7)108#define STMPE_SYS_CTRL_INT_EN (1 << 2)109#define STMPE_SYS_CTRL_INT_HI (1 << 0)110 111/*112 * STMPE801113 */114#define STMPE801_ID 0x0108115#define STMPE801_NR_INTERNAL_IRQS 1116 117#define STMPE801_REG_CHIP_ID 0x00118#define STMPE801_REG_VERSION_ID 0x02119#define STMPE801_REG_SYS_CTRL 0x04120#define STMPE801_REG_GPIO_INT_EN 0x08121#define STMPE801_REG_GPIO_INT_STA 0x09122#define STMPE801_REG_GPIO_MP_STA 0x10123#define STMPE801_REG_GPIO_SET_PIN 0x11124#define STMPE801_REG_GPIO_DIR 0x12125 126/*127 * STMPE811128 */129#define STMPE811_ID 0x0811130 131#define STMPE811_IRQ_TOUCH_DET 0132#define STMPE811_IRQ_FIFO_TH 1133#define STMPE811_IRQ_FIFO_OFLOW 2134#define STMPE811_IRQ_FIFO_FULL 3135#define STMPE811_IRQ_FIFO_EMPTY 4136#define STMPE811_IRQ_TEMP_SENS 5137#define STMPE811_IRQ_ADC 6138#define STMPE811_IRQ_GPIOC 7139#define STMPE811_NR_INTERNAL_IRQS 8140 141#define STMPE811_REG_CHIP_ID 0x00142#define STMPE811_REG_SYS_CTRL 0x03143#define STMPE811_REG_SYS_CTRL2 0x04144#define STMPE811_REG_SPI_CFG 0x08145#define STMPE811_REG_INT_CTRL 0x09146#define STMPE811_REG_INT_EN 0x0A147#define STMPE811_REG_INT_STA 0x0B148#define STMPE811_REG_GPIO_INT_EN 0x0C149#define STMPE811_REG_GPIO_INT_STA 0x0D150#define STMPE811_REG_GPIO_SET_PIN 0x10151#define STMPE811_REG_GPIO_CLR_PIN 0x11152#define STMPE811_REG_GPIO_MP_STA 0x12153#define STMPE811_REG_GPIO_DIR 0x13154#define STMPE811_REG_GPIO_ED 0x14155#define STMPE811_REG_GPIO_RE 0x15156#define STMPE811_REG_GPIO_FE 0x16157#define STMPE811_REG_GPIO_AF 0x17158 159#define STMPE811_SYS_CTRL_RESET (1 << 1)160 161#define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)162#define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)163#define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)164#define STMPE811_SYS_CTRL2_TS_OFF (1 << 3)165 166/*167 * STMPE1600168 */169#define STMPE1600_ID 0x0016170#define STMPE1600_NR_INTERNAL_IRQS 16171 172#define STMPE1600_REG_CHIP_ID 0x00173#define STMPE1600_REG_SYS_CTRL 0x03174#define STMPE1600_REG_IEGPIOR_LSB 0x08175#define STMPE1600_REG_IEGPIOR_MSB 0x09176#define STMPE1600_REG_ISGPIOR_LSB 0x0A177#define STMPE1600_REG_ISGPIOR_MSB 0x0B178#define STMPE1600_REG_GPMR_LSB 0x10179#define STMPE1600_REG_GPMR_MSB 0x11180#define STMPE1600_REG_GPSR_LSB 0x12181#define STMPE1600_REG_GPSR_MSB 0x13182#define STMPE1600_REG_GPDR_LSB 0x14183#define STMPE1600_REG_GPDR_MSB 0x15184#define STMPE1600_REG_GPPIR_LSB 0x16185#define STMPE1600_REG_GPPIR_MSB 0x17186 187/*188 * STMPE1601189 */190 191#define STMPE1601_IRQ_GPIOC 8192#define STMPE1601_IRQ_PWM3 7193#define STMPE1601_IRQ_PWM2 6194#define STMPE1601_IRQ_PWM1 5195#define STMPE1601_IRQ_PWM0 4196#define STMPE1601_IRQ_KEYPAD_OVER 2197#define STMPE1601_IRQ_KEYPAD 1198#define STMPE1601_IRQ_WAKEUP 0199#define STMPE1601_NR_INTERNAL_IRQS 9200 201#define STMPE1601_REG_SYS_CTRL 0x02202#define STMPE1601_REG_SYS_CTRL2 0x03203#define STMPE1601_REG_ICR_MSB 0x10204#define STMPE1601_REG_ICR_LSB 0x11205#define STMPE1601_REG_IER_MSB 0x12206#define STMPE1601_REG_IER_LSB 0x13207#define STMPE1601_REG_ISR_MSB 0x14208#define STMPE1601_REG_ISR_LSB 0x15209#define STMPE1601_REG_INT_EN_GPIO_MASK_MSB 0x16210#define STMPE1601_REG_INT_EN_GPIO_MASK_LSB 0x17211#define STMPE1601_REG_INT_STA_GPIO_MSB 0x18212#define STMPE1601_REG_INT_STA_GPIO_LSB 0x19213#define STMPE1601_REG_CHIP_ID 0x80214#define STMPE1601_REG_GPIO_SET_MSB 0x82215#define STMPE1601_REG_GPIO_SET_LSB 0x83216#define STMPE1601_REG_GPIO_CLR_MSB 0x84217#define STMPE1601_REG_GPIO_CLR_LSB 0x85218#define STMPE1601_REG_GPIO_MP_MSB 0x86219#define STMPE1601_REG_GPIO_MP_LSB 0x87220#define STMPE1601_REG_GPIO_SET_DIR_MSB 0x88221#define STMPE1601_REG_GPIO_SET_DIR_LSB 0x89222#define STMPE1601_REG_GPIO_ED_MSB 0x8A223#define STMPE1601_REG_GPIO_ED_LSB 0x8B224#define STMPE1601_REG_GPIO_RE_MSB 0x8C225#define STMPE1601_REG_GPIO_RE_LSB 0x8D226#define STMPE1601_REG_GPIO_FE_MSB 0x8E227#define STMPE1601_REG_GPIO_FE_LSB 0x8F228#define STMPE1601_REG_GPIO_PU_MSB 0x90229#define STMPE1601_REG_GPIO_PU_LSB 0x91230#define STMPE1601_REG_GPIO_AF_U_MSB 0x92231 232#define STMPE1601_SYS_CTRL_ENABLE_GPIO (1 << 3)233#define STMPE1601_SYS_CTRL_ENABLE_KPC (1 << 1)234#define STMPE1601_SYS_CTRL_ENABLE_SPWM (1 << 0)235 236/* The 1601/2403 share the same masks */237#define STMPE1601_AUTOSLEEP_TIMEOUT_MASK (0x7)238#define STPME1601_AUTOSLEEP_ENABLE (1 << 3)239 240/*241 * STMPE1801242 */243#define STMPE1801_ID 0xc110244#define STMPE1801_NR_INTERNAL_IRQS 5245#define STMPE1801_IRQ_KEYPAD_COMBI 4246#define STMPE1801_IRQ_GPIOC 3247#define STMPE1801_IRQ_KEYPAD_OVER 2248#define STMPE1801_IRQ_KEYPAD 1249#define STMPE1801_IRQ_WAKEUP 0250 251#define STMPE1801_REG_CHIP_ID 0x00252#define STMPE1801_REG_SYS_CTRL 0x02253#define STMPE1801_REG_INT_CTRL_LOW 0x04254#define STMPE1801_REG_INT_EN_MASK_LOW 0x06255#define STMPE1801_REG_INT_STA_LOW 0x08256#define STMPE1801_REG_INT_EN_GPIO_MASK_LOW 0x0A257#define STMPE1801_REG_INT_EN_GPIO_MASK_MID 0x0B258#define STMPE1801_REG_INT_EN_GPIO_MASK_HIGH 0x0C259#define STMPE1801_REG_INT_STA_GPIO_LOW 0x0D260#define STMPE1801_REG_INT_STA_GPIO_MID 0x0E261#define STMPE1801_REG_INT_STA_GPIO_HIGH 0x0F262#define STMPE1801_REG_GPIO_SET_LOW 0x10263#define STMPE1801_REG_GPIO_SET_MID 0x11264#define STMPE1801_REG_GPIO_SET_HIGH 0x12265#define STMPE1801_REG_GPIO_CLR_LOW 0x13266#define STMPE1801_REG_GPIO_CLR_MID 0x14267#define STMPE1801_REG_GPIO_CLR_HIGH 0x15268#define STMPE1801_REG_GPIO_MP_LOW 0x16269#define STMPE1801_REG_GPIO_MP_MID 0x17270#define STMPE1801_REG_GPIO_MP_HIGH 0x18271#define STMPE1801_REG_GPIO_SET_DIR_LOW 0x19272#define STMPE1801_REG_GPIO_SET_DIR_MID 0x1A273#define STMPE1801_REG_GPIO_SET_DIR_HIGH 0x1B274#define STMPE1801_REG_GPIO_RE_LOW 0x1C275#define STMPE1801_REG_GPIO_RE_MID 0x1D276#define STMPE1801_REG_GPIO_RE_HIGH 0x1E277#define STMPE1801_REG_GPIO_FE_LOW 0x1F278#define STMPE1801_REG_GPIO_FE_MID 0x20279#define STMPE1801_REG_GPIO_FE_HIGH 0x21280#define STMPE1801_REG_GPIO_PULL_UP_LOW 0x22281#define STMPE1801_REG_GPIO_PULL_UP_MID 0x23282#define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24283 284#define STMPE1801_MSK_INT_EN_KPC (1 << 1)285#define STMPE1801_MSK_INT_EN_GPIO (1 << 3)286 287/*288 * STMPE24xx289 */290 291#define STMPE24XX_IRQ_GPIOC 8292#define STMPE24XX_IRQ_PWM2 7293#define STMPE24XX_IRQ_PWM1 6294#define STMPE24XX_IRQ_PWM0 5295#define STMPE24XX_IRQ_ROT_OVER 4296#define STMPE24XX_IRQ_ROT 3297#define STMPE24XX_IRQ_KEYPAD_OVER 2298#define STMPE24XX_IRQ_KEYPAD 1299#define STMPE24XX_IRQ_WAKEUP 0300#define STMPE24XX_NR_INTERNAL_IRQS 9301 302#define STMPE24XX_REG_SYS_CTRL 0x02303#define STMPE24XX_REG_SYS_CTRL2 0x03304#define STMPE24XX_REG_ICR_MSB 0x10305#define STMPE24XX_REG_ICR_LSB 0x11306#define STMPE24XX_REG_IER_MSB 0x12307#define STMPE24XX_REG_IER_LSB 0x13308#define STMPE24XX_REG_ISR_MSB 0x14309#define STMPE24XX_REG_ISR_LSB 0x15310#define STMPE24XX_REG_IEGPIOR_MSB 0x16311#define STMPE24XX_REG_IEGPIOR_CSB 0x17312#define STMPE24XX_REG_IEGPIOR_LSB 0x18313#define STMPE24XX_REG_ISGPIOR_MSB 0x19314#define STMPE24XX_REG_ISGPIOR_CSB 0x1A315#define STMPE24XX_REG_ISGPIOR_LSB 0x1B316#define STMPE24XX_REG_CHIP_ID 0x80317#define STMPE24XX_REG_GPSR_MSB 0x83318#define STMPE24XX_REG_GPSR_CSB 0x84319#define STMPE24XX_REG_GPSR_LSB 0x85320#define STMPE24XX_REG_GPCR_MSB 0x86321#define STMPE24XX_REG_GPCR_CSB 0x87322#define STMPE24XX_REG_GPCR_LSB 0x88323#define STMPE24XX_REG_GPDR_MSB 0x89324#define STMPE24XX_REG_GPDR_CSB 0x8A325#define STMPE24XX_REG_GPDR_LSB 0x8B326#define STMPE24XX_REG_GPEDR_MSB 0x8C327#define STMPE24XX_REG_GPEDR_CSB 0x8D328#define STMPE24XX_REG_GPEDR_LSB 0x8E329#define STMPE24XX_REG_GPRER_MSB 0x8F330#define STMPE24XX_REG_GPRER_CSB 0x90331#define STMPE24XX_REG_GPRER_LSB 0x91332#define STMPE24XX_REG_GPFER_MSB 0x92333#define STMPE24XX_REG_GPFER_CSB 0x93334#define STMPE24XX_REG_GPFER_LSB 0x94335#define STMPE24XX_REG_GPPUR_MSB 0x95336#define STMPE24XX_REG_GPPUR_CSB 0x96337#define STMPE24XX_REG_GPPUR_LSB 0x97338#define STMPE24XX_REG_GPPDR_MSB 0x98339#define STMPE24XX_REG_GPPDR_CSB 0x99340#define STMPE24XX_REG_GPPDR_LSB 0x9A341#define STMPE24XX_REG_GPAFR_U_MSB 0x9B342#define STMPE24XX_REG_GPMR_MSB 0xA2343#define STMPE24XX_REG_GPMR_CSB 0xA3344#define STMPE24XX_REG_GPMR_LSB 0xA4345#define STMPE24XX_SYS_CTRL_ENABLE_GPIO (1 << 3)346#define STMPE24XX_SYSCON_ENABLE_PWM (1 << 2)347#define STMPE24XX_SYS_CTRL_ENABLE_KPC (1 << 1)348#define STMPE24XX_SYSCON_ENABLE_ROT (1 << 0)349 350#endif351