131 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * timberdale.h timberdale FPGA MFD driver defines4 * Copyright (c) 2009 Intel Corporation5 */6 7/* Supports:8 * Timberdale FPGA9 */10 11#ifndef MFD_TIMBERDALE_H12#define MFD_TIMBERDALE_H13 14#define DRV_VERSION "0.3"15 16/* This driver only support versions >= 3.8 and < 4.0 */17#define TIMB_SUPPORTED_MAJOR 318 19/* This driver only support minor >= 8 */20#define TIMB_REQUIRED_MINOR 821 22/* Registers of the control area */23#define TIMB_REV_MAJOR 0x0024#define TIMB_REV_MINOR 0x0425#define TIMB_HW_CONFIG 0x0826#define TIMB_SW_RST 0x4027 28/* bits in the TIMB_HW_CONFIG register */29#define TIMB_HW_CONFIG_SPI_8BIT 0x8030 31#define TIMB_HW_VER_MASK 0x0f32#define TIMB_HW_VER0 0x0033#define TIMB_HW_VER1 0x0134#define TIMB_HW_VER2 0x0235#define TIMB_HW_VER3 0x0336 37#define OCORESOFFSET 0x038#define OCORESEND 0x1f39 40#define SPIOFFSET 0x8041#define SPIEND 0xff42 43#define UARTLITEOFFSET 0x10044#define UARTLITEEND 0x10f45 46#define RDSOFFSET 0x18047#define RDSEND 0x18348 49#define ETHOFFSET 0x30050#define ETHEND 0x3ff51 52#define GPIOOFFSET 0x40053#define GPIOEND 0x7ff54 55#define CHIPCTLOFFSET 0x80056#define CHIPCTLEND 0x8ff57#define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET + 1)58 59#define INTCOFFSET 0xc0060#define INTCEND 0xfff61#define INTCSIZE (INTCEND - INTCOFFSET)62 63#define MOSTOFFSET 0x100064#define MOSTEND 0x13ff65 66#define UARTOFFSET 0x140067#define UARTEND 0x17ff68 69#define XIICOFFSET 0x180070#define XIICEND 0x19ff71 72#define I2SOFFSET 0x1C0073#define I2SEND 0x1fff74 75#define LOGIWOFFSET 0x3000076#define LOGIWEND 0x37fff77 78#define MLCOREOFFSET 0x4000079#define MLCOREEND 0x43fff80 81#define DMAOFFSET 0x0100000082#define DMAEND 0x013fffff83 84/* SDHC0 is placed in PCI bar 1 */85#define SDHC0OFFSET 0x0086#define SDHC0END 0xff87 88/* SDHC1 is placed in PCI bar 2 */89#define SDHC1OFFSET 0x0090#define SDHC1END 0xff91 92#define PCI_VENDOR_ID_TIMB 0x10ee93#define PCI_DEVICE_ID_TIMB 0xa12394 95#define IRQ_TIMBERDALE_INIC 096#define IRQ_TIMBERDALE_MLB 197#define IRQ_TIMBERDALE_GPIO 298#define IRQ_TIMBERDALE_I2C 399#define IRQ_TIMBERDALE_UART 4100#define IRQ_TIMBERDALE_DMA 5101#define IRQ_TIMBERDALE_I2S 6102#define IRQ_TIMBERDALE_TSC_INT 7103#define IRQ_TIMBERDALE_SDHC 8104#define IRQ_TIMBERDALE_ADV7180 9105#define IRQ_TIMBERDALE_ETHSW_IF 10106#define IRQ_TIMBERDALE_SPI 11107#define IRQ_TIMBERDALE_UARTLITE 12108#define IRQ_TIMBERDALE_MLCORE 13109#define IRQ_TIMBERDALE_MLCORE_BUF 14110#define IRQ_TIMBERDALE_RDS 15111#define TIMBERDALE_NR_IRQS 16112 113#define GPIO_PIN_ASCB 8114#define GPIO_PIN_INIC_RST 14115#define GPIO_PIN_BT_RST 15116#define GPIO_NR_PINS 16117 118/* DMA Channels */119#define DMA_UART_RX 0120#define DMA_UART_TX 1121#define DMA_MLB_RX 2122#define DMA_MLB_TX 3123#define DMA_VIDEO_RX 4124#define DMA_VIDEO_DROP 5125#define DMA_SDHCI_RX 6126#define DMA_SDHCI_TX 7127#define DMA_ETH_RX 8128#define DMA_ETH_TX 9129 130#endif131