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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * Copyright (c) 2013-2014, Intel Corporation. All rights reserved.4 * Intel Management Engine Interface (Intel MEI) Linux driver5 */6#ifndef _MEI_HW_TXE_REGS_H_7#define _MEI_HW_TXE_REGS_H_8 9#include "hw.h"10 11#define SEC_ALIVENESS_TIMER_TIMEOUT (5 * MSEC_PER_SEC)12#define SEC_ALIVENESS_WAIT_TIMEOUT (1 * MSEC_PER_SEC)13#define SEC_RESET_WAIT_TIMEOUT (1 * MSEC_PER_SEC)14#define SEC_READY_WAIT_TIMEOUT (5 * MSEC_PER_SEC)15#define START_MESSAGE_RESPONSE_WAIT_TIMEOUT (5 * MSEC_PER_SEC)16#define RESET_CANCEL_WAIT_TIMEOUT (1 * MSEC_PER_SEC)17 18enum {19 SEC_BAR,20 BRIDGE_BAR,21 22 NUM_OF_MEM_BARS23};24 25/* SeC FW Status Register26 *27 * FW uses this register in order to report its status to host.28 * This register resides in PCI-E config space.29 */30#define PCI_CFG_TXE_FW_STS0 0x4031# define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK 0x0000000F32# define PCI_CFG_TXE_FW_STS0_OP_ST_MSK 0x000001C033# define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x0000020034# define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK 0x0000F00035# define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK 0x000F000036# define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK 0x00F0000037#define PCI_CFG_TXE_FW_STS1 0x4838 39#define IPC_BASE_ADDR 0x80400 /* SeC IPC Base Address */40 41/* IPC Input Doorbell Register */42#define SEC_IPC_INPUT_DOORBELL_REG (0x0000 + IPC_BASE_ADDR)43 44/* IPC Input Status Register45 * This register indicates whether or not processing of46 * the most recent command has been completed by the SEC47 * New commands and payloads should not be written by the Host48 * until this indicates that the previous command has been processed.49 */50#define SEC_IPC_INPUT_STATUS_REG (0x0008 + IPC_BASE_ADDR)51# define SEC_IPC_INPUT_STATUS_RDY BIT(0)52 53/* IPC Host Interrupt Status Register */54#define SEC_IPC_HOST_INT_STATUS_REG (0x0010 + IPC_BASE_ADDR)55#define SEC_IPC_HOST_INT_STATUS_OUT_DB BIT(0)56#define SEC_IPC_HOST_INT_STATUS_IN_RDY BIT(1)57#define SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD BIT(5)58#define SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS BIT(17)59#define SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR BIT(18)60#define SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR BIT(19)61#define SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW BIT(21)62 63/* Convenient mask for pending interrupts */64#define SEC_IPC_HOST_INT_STATUS_PENDING \65 (SEC_IPC_HOST_INT_STATUS_OUT_DB| \66 SEC_IPC_HOST_INT_STATUS_IN_RDY)67 68/* IPC Host Interrupt Mask Register */69#define SEC_IPC_HOST_INT_MASK_REG (0x0014 + IPC_BASE_ADDR)70 71# define SEC_IPC_HOST_INT_MASK_OUT_DB BIT(0) /* Output Doorbell Int Mask */72# define SEC_IPC_HOST_INT_MASK_IN_RDY BIT(1) /* Input Ready Int Mask */73 74/* IPC Input Payload RAM */75#define SEC_IPC_INPUT_PAYLOAD_REG (0x0100 + IPC_BASE_ADDR)76/* IPC Shared Payload RAM */77#define IPC_SHARED_PAYLOAD_REG (0x0200 + IPC_BASE_ADDR)78 79/* SeC Address Translation Table Entry 2 - Ctrl80 *81 * This register resides also in SeC's PCI-E Memory space.82 */83#define SATT2_CTRL_REG 0x104084# define SATT2_CTRL_VALID_MSK BIT(0)85# define SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT 886# define SATT2_CTRL_BRIDGE_HOST_EN_MSK BIT(12)87 88/* SATT Table Entry 2 SAP Base Address Register */89#define SATT2_SAP_BA_REG 0x104490/* SATT Table Entry 2 SAP Size Register. */91#define SATT2_SAP_SIZE_REG 0x104892 /* SATT Table Entry 2 SAP Bridge Address - LSB Register */93#define SATT2_BRG_BA_LSB_REG 0x104C94 95/* Host High-level Interrupt Status Register */96#define HHISR_REG 0x202097/* Host High-level Interrupt Enable Register98 *99 * Resides in PCI memory space. This is the top hierarchy for100 * interrupts from SeC to host, aggregating both interrupts that101 * arrive through HICR registers as well as interrupts102 * that arrive via IPC.103 */104#define HHIER_REG 0x2024105#define IPC_HHIER_SEC BIT(0)106#define IPC_HHIER_BRIDGE BIT(1)107#define IPC_HHIER_MSK (IPC_HHIER_SEC | IPC_HHIER_BRIDGE)108 109/* Host High-level Interrupt Mask Register.110 *111 * Resides in PCI memory space.112 * This is the top hierarchy for masking interrupts from SeC to host.113 */114#define HHIMR_REG 0x2028115#define IPC_HHIMR_SEC BIT(0)116#define IPC_HHIMR_BRIDGE BIT(1)117 118/* Host High-level IRQ Status Register */119#define HHIRQSR_REG 0x202C120 121/* Host Interrupt Cause Register 0 - SeC IPC Readiness122 *123 * This register is both an ICR to Host from PCI Memory Space124 * and it is also exposed in the SeC memory space.125 * This register is used by SeC's IPC driver in order126 * to synchronize with host about IPC interface state.127 */128#define HICR_SEC_IPC_READINESS_REG 0x2040129#define HICR_SEC_IPC_READINESS_HOST_RDY BIT(0)130#define HICR_SEC_IPC_READINESS_SEC_RDY BIT(1)131#define HICR_SEC_IPC_READINESS_SYS_RDY \132 (HICR_SEC_IPC_READINESS_HOST_RDY | \133 HICR_SEC_IPC_READINESS_SEC_RDY)134#define HICR_SEC_IPC_READINESS_RDY_CLR BIT(2)135 136/* Host Interrupt Cause Register 1 - Aliveness Response */137/* This register is both an ICR to Host from PCI Memory Space138 * and it is also exposed in the SeC memory space.139 * The register may be used by SeC to ACK a host request for aliveness.140 */141#define HICR_HOST_ALIVENESS_RESP_REG 0x2044142#define HICR_HOST_ALIVENESS_RESP_ACK BIT(0)143 144/* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */145#define HICR_SEC_IPC_OUTPUT_DOORBELL_REG 0x2048146 147/* Host Interrupt Status Register.148 *149 * Resides in PCI memory space.150 * This is the main register involved in generating interrupts151 * from SeC to host via HICRs.152 * The interrupt generation rules are as follows:153 * An interrupt will be generated whenever for any i,154 * there is a transition from a state where at least one of155 * the following conditions did not hold, to a state where156 * ALL the following conditions hold:157 * A) HISR.INT[i]_STS == 1.158 * B) HIER.INT[i]_EN == 1.159 */160#define HISR_REG 0x2060161#define HISR_INT_0_STS BIT(0)162#define HISR_INT_1_STS BIT(1)163#define HISR_INT_2_STS BIT(2)164#define HISR_INT_3_STS BIT(3)165#define HISR_INT_4_STS BIT(4)166#define HISR_INT_5_STS BIT(5)167#define HISR_INT_6_STS BIT(6)168#define HISR_INT_7_STS BIT(7)169#define HISR_INT_STS_MSK \170 (HISR_INT_0_STS | HISR_INT_1_STS | HISR_INT_2_STS)171 172/* Host Interrupt Enable Register. Resides in PCI memory space. */173#define HIER_REG 0x2064174#define HIER_INT_0_EN BIT(0)175#define HIER_INT_1_EN BIT(1)176#define HIER_INT_2_EN BIT(2)177#define HIER_INT_3_EN BIT(3)178#define HIER_INT_4_EN BIT(4)179#define HIER_INT_5_EN BIT(5)180#define HIER_INT_6_EN BIT(6)181#define HIER_INT_7_EN BIT(7)182 183#define HIER_INT_EN_MSK \184 (HIER_INT_0_EN | HIER_INT_1_EN | HIER_INT_2_EN)185 186 187/* SEC Memory Space IPC output payload.188 *189 * This register is part of the output payload which SEC provides to host.190 */191#define BRIDGE_IPC_OUTPUT_PAYLOAD_REG 0x20C0192 193/* SeC Interrupt Cause Register - Host Aliveness Request194 * This register is both an ICR to SeC and it is also exposed195 * in the host-visible PCI memory space.196 * The register is used by host to request SeC aliveness.197 */198#define SICR_HOST_ALIVENESS_REQ_REG 0x214C199#define SICR_HOST_ALIVENESS_REQ_REQUESTED BIT(0)200 201 202/* SeC Interrupt Cause Register - Host IPC Readiness203 *204 * This register is both an ICR to SeC and it is also exposed205 * in the host-visible PCI memory space.206 * This register is used by the host's SeC driver uses in order207 * to synchronize with SeC about IPC interface state.208 */209#define SICR_HOST_IPC_READINESS_REQ_REG 0x2150210 211 212#define SICR_HOST_IPC_READINESS_HOST_RDY BIT(0)213#define SICR_HOST_IPC_READINESS_SEC_RDY BIT(1)214#define SICR_HOST_IPC_READINESS_SYS_RDY \215 (SICR_HOST_IPC_READINESS_HOST_RDY | \216 SICR_HOST_IPC_READINESS_SEC_RDY)217#define SICR_HOST_IPC_READINESS_RDY_CLR BIT(2)218 219/* SeC Interrupt Cause Register - SeC IPC Output Status220 *221 * This register indicates whether or not processing of the most recent222 * command has been completed by the Host.223 * New commands and payloads should not be written by SeC until this224 * register indicates that the previous command has been processed.225 */226#define SICR_SEC_IPC_OUTPUT_STATUS_REG 0x2154227# define SEC_IPC_OUTPUT_STATUS_RDY BIT(0)228 229 230 231/* MEI IPC Message payload size 64 bytes */232#define PAYLOAD_SIZE 64233 234/* MAX size for SATT range 32MB */235#define SATT_RANGE_MAX (32 << 20)236 237 238#endif /* _MEI_HW_TXE_REGS_H_ */239 240